Lines Matching +full:0 +full:x0e00
58 #define REG_RCR_PI_CINH 0x0000
59 #define REG_RCR_CI_CINH 0x0004
60 #define REG_RCR_ITR 0x0008
61 #define REG_CFG 0x0100
62 #define REG_SCN(n) (0x0200 + ((n) << 2))
63 #define REG_ISR 0x0e00
64 #define REG_IER 0x0e04
65 #define REG_ISDR 0x0e08
66 #define REG_IIR 0x0e0c
69 #define CL_CR 0x0000
70 #define CL_RR0 0x0100
71 #define CL_RR1 0x0140
72 #define CL_RCR 0x1000
73 #define CL_RCR_PI_CENA 0x3000
74 #define CL_RCR_CI_CENA 0x3100
190 rcr->vbit = (uint8_t)((bm_in(RCR_PI_CINH) & BM_RCR_SIZE) ? BM_RCR_VERB_VBIT : 0); in bm_rcr_init()
194 rcr->busy = 0; in bm_rcr_init()
200 cfg = (bm_in(CFG) & 0xffffffe0) | (pmode & 0x3); /* BCSP_CFG::RPM */ in bm_rcr_init()
202 return 0; in bm_rcr_init()
237 rcr->busy = 0; in bm_rcr_abort()
269 rcr->busy = 0; in bm_rcr_pci_commit()
291 rcr->busy = 0; in bm_rcr_pce_commit()
308 rcr->busy = 0; in bm_rcr_pvb_commit()
389 0 : 1); in bm_mc_init()
390 mc->vbit = (uint8_t)(mc->rridx ? BM_MCC_VERB_VBIT : 0); in bm_mc_init()
394 return 0; in bm_mc_init()
473 #define SCN_BIT(bpid) (0x80000000 >> (bpid & 31))
478 /* REG_SCN for bpid=0..31, REG_SCN+4 for bpid=32..63 */ in bm_isr_bscn_mask()