Lines Matching +full:0 +full:x0e00
38 #define AMDIOMMU_DEVTAB_BASE 0x0000
39 #define AMDIOMMU_CMDBUF_BASE 0x0008
40 #define AMDIOMMU_EVNTLOG_BASE 0x0010
41 #define AMDIOMMU_CTRL 0x0018
42 #define AMDIOMMU_EXCL_BASE 0x0020
43 #define AMDIOMMU_EXCL_RANGE 0x0028
44 #define AMDIOMMU_EFR 0x0030
45 #define AMDIOMMU_PPRLOG_BASE 0x0038
46 #define AMDIOMMU_HWEV_UPPER 0x0040
47 #define AMDIOMMU_HWEV_LOWER 0x0048
48 #define AMDIOMMU_HWEV_STATUS 0x0050
50 #define AMDIOMMU_SMIF_0 0x0060
51 #define AMDIOMMU_SMIF_1 0x0068
52 #define AMDIOMMU_SMIF_2 0x0070
53 #define AMDIOMMU_SMIF_3 0x0078
54 #define AMDIOMMU_SMIF_4 0x0080
55 #define AMDIOMMU_SMIF_5 0x0088
56 #define AMDIOMMU_SMIF_6 0x0090
57 #define AMDIOMMU_SMIF_7 0x0098
58 #define AMDIOMMU_SMIF_8 0x00a0
59 #define AMDIOMMU_SMIF_9 0x00a8
60 #define AMDIOMMU_SMIF_10 0x00b0
61 #define AMDIOMMU_SMIF_11 0x00b8
62 #define AMDIOMMU_SMIF_12 0x00c0
63 #define AMDIOMMU_SMIF_13 0x00c8
64 #define AMDIOMMU_SMIF_14 0x00d0
65 #define AMDIOMMU_SMIF_15 0x00d8
67 #define AMDIOMMU_VAPIC_LOG_BASE 0x00e0
68 #define AMDIOMMU_VAPIC_LOG_TAIL 0x00e8
69 #define AMDIOMMU_PPRLOGB_BASE 0x00f0
70 #define AMDIOMMU_EVNTLOGB_BASE 0x00f0
72 #define AMDIOMMU_DEVTAB_S1_BASE 0x0100
73 #define AMDIOMMU_DEVTAB_S2_BASE 0x0108
74 #define AMDIOMMU_DEVTAB_S3_BASE 0x0110
75 #define AMDIOMMU_DEVTAB_S4_BASE 0x0118
76 #define AMDIOMMU_DEVTAB_S5_BASE 0x0120
77 #define AMDIOMMU_DEVTAB_S6_BASE 0x0128
78 #define AMDIOMMU_DEVTAB_S7_BASE 0x0130
80 #define AMDIOMMU_DSFX 0x0138
81 #define AMDIOMMU_DSCX 0x0140
82 #define AMDIOMMU_DSSX 0x0148
84 #define AMDIOMMU_MSI_VEC0 0x0150
85 #define AMDIOMMU_MSI_VEC1 0x0154
86 #define AMDIOMMU_MSI_CAP_H 0x0158
87 #define AMDIOMMU_MSI_ADDR_LOW 0x015c
88 #define AMDIOMMU_MSI_ADDR_HIGH 0x0160
89 #define AMDIOMMU_MSI_DATA 0x0164
90 #define AMDIOMMU_MSI_MAPCAP 0x0168
92 #define AMDIOMMU_PERFOPT 0x016c
94 #define AMDIOMMU_x2APIC_CTRL 0x0170
95 #define AMDIOMMU_PPRI_CTRL 0x0178
96 #define AMDIOMMU_GALOGI_CTRL 0x0180
98 #define AMDIOMMU_vIOMMU_STATUS 0x0190
100 #define AMDIOMMU_MARC0_BASE 0x0200
101 #define AMDIOMMU_MARC0_RELOC 0x0208
102 #define AMDIOMMU_MARC0_LEN 0x0210
103 #define AMDIOMMU_MARC1_BASE 0x0218
104 #define AMDIOMMU_MARC1_RELOC 0x0220
105 #define AMDIOMMU_MARC1_LEN 0x0228
106 #define AMDIOMMU_MARC2_BASE 0x0230
107 #define AMDIOMMU_MARC2_RELOC 0x0238
108 #define AMDIOMMU_MARC2_LEN 0x0240
109 #define AMDIOMMU_MARC3_BASE 0x0248
110 #define AMDIOMMU_MARC3_RELOC 0x0250
111 #define AMDIOMMU_MARC3_LEN 0x0258
113 #define AMDIOMMU_EFR2 0x01a0
115 #define AMDIOMMU_CMDBUF_HEAD 0x2000
116 #define AMDIOMMU_CMDBUF_TAIL 0x2008
117 #define AMDIOMMU_EVNTLOG_HEAD 0x2010
118 #define AMDIOMMU_EVNTLOG_TAIL 0x2018
119 #define AMDIOMMU_CMDEV_STATUS 0x2020
120 #define AMDIOMMU_PPRLOG_HEAD 0x2030
121 #define AMDIOMMU_PPRLOG_TAIL 0x2038
122 #define AMDIOMMU_vAPICLOG_HEAD 0x2040
123 #define AMDIOMMU_vAPICLOG_TAIL 0x2048
124 #define AMDIOMMU_PPRLOGB_HEAD 0x2050
125 #define AMDIOMMU_PPRLOGB_TAIL 0x2058
126 #define AMDIOMMU_EVNTLOGB_HEAD 0x2070
127 #define AMDIOMMU_EVNTLOGB_TAIL 0x2078
128 #define AMDIOMMU_PPRLOG_AUR 0x2080
129 #define AMDIOMMU_PPRLOG_EAI 0x2088
130 #define AMDIOMMU_PPRLOGB_AUR 0x2090
135 #define AMDIOMMU_CTRL_EN 0x0000000000000001ull /* IOMMU En */
136 #define AMDIOMMU_CTRL_HTTUN_EN 0x0000000000000002ull /* HT Tun Trans En */
137 #define AMDIOMMU_CTRL_EVNTLOG_EN 0x0000000000000004ull /* Event Log En */
138 #define AMDIOMMU_CTRL_EVENTINT_EN 0x0000000000000008ull /* Event Log Intr En */
139 #define AMDIOMMU_CTRL_COMWINT_EN 0x0000000000000010ull /* Compl Wait Intr En */
140 #define AMDIOMMU_CTRL_INVTOUT_MASK 0x00000000000000e0ull /* IOTLB Inv Timeout*/
141 #define AMDIOMMU_CTRL_INVTOUT_NO 0x0000000000000000ull
142 #define AMDIOMMU_CTRL_INVTOUT_1MS 0x0000000000000020ull
143 #define AMDIOMMU_CTRL_INVTOUT_10MS 0x0000000000000040ull
144 #define AMDIOMMU_CTRL_INVTOUT_100MS 0x0000000000000060ull
145 #define AMDIOMMU_CTRL_INVTOUT_1S 0x0000000000000080ull
146 #define AMDIOMMU_CTRL_INVTOUT_10S 0x00000000000000a0ull
147 #define AMDIOMMU_CTRL_INVTOUT_100S 0x00000000000000b0ull
148 #define AMDIOMMU_CTRL_INVTOUT_RSRV 0x00000000000000e0ull
149 #define AMDIOMMU_CTRL_PASSPW 0x0000000000000100ull /* HT Pass Posted Wr */
150 #define AMDIOMMU_CTRL_REPASSPW 0x0000000000000200ull /* HT Resp Pass Posted Wr */
151 #define AMDIOMMU_CTRL_COHERENT 0x0000000000000400ull /* HT Coherent Reads */
152 #define AMDIOMMU_CTRL_ISOC 0x0000000000000800ull /* HT Isoc Reads */
153 #define AMDIOMMU_CTRL_CMDBUF_EN 0x0000000000001000ull /* Start CMD proc En */
154 #define AMDIOMMU_CTRL_PPRLOG_EN 0x0000000000002000ull /* Periph Page Req Log En */
155 #define AMDIOMMU_CTRL_PPRINT_EN 0x0000000000004000ull /* Periph Page Req Intr En */
156 #define AMDIOMMU_CTRL_PPR_EN 0x0000000000008000ull /* Periph Page Req En */
157 #define AMDIOMMU_CTRL_GT_EN 0x0000000000010000ull /* Guest En */
158 #define AMDIOMMU_CTRL_GA_EN 0x0000000000020000ull /* Guest vAPIC En */
159 #define AMDIOMMU_CTRL_SMIF_EN 0x0000000000400000ull /* SMI Filter En */
160 #define AMDIOMMU_CTRL_SLFWB_DIS 0x0000000000800000ull /* Self WriteBack Dis */
161 #define AMDIOMMU_CTRL_SMIFLOG_EN 0x0000000001000000ull /* SMI Filter Log En */
162 #define AMDIOMMU_CTRL_GAM_EN_MASK 0x000000000e000000ull /* Guest vAPIC Mode En */
163 #define AMDIOMMU_CTRL_GAM_EN_vAPIC_GM0 0x0000000000000000ull /* IRTE.GM = 0 */
164 #define AMDIOMMU_CTRL_GAM_EN_vAPIC_GM1 0x0000000002000000ull /* IRTE.GM = 1 */
165 #define AMDIOMMU_CTRL_GALOG_EN 0x0000000010000000ull /* Guest vAPIC GA Log En */
166 #define AMDIOMMU_CTRL_GAINT_EN 0x0000000020000000ull /* Guest vAPIC GA Intr En */
167 #define AMDIOMMU_CTRL_DUALPPRLOG_MASK 0x00000000c0000000ull /* Dual Periph Page Req Log En */
168 #define AMDIOMMU_CTRL_DUALPPRLOG_A 0x0000000000000000ull /* Use Log A */
169 #define AMDIOMMU_CTRL_DUALPPRLOG_B 0x0000000040000000ull /* Use Log B */
170 #define AMDIOMMU_CTRL_DUALPPRLOG_SWAP 0x0000000080000000ull /* Auto-swap on full */
171 #define AMDIOMMU_CTRL_DUALPPRLOG_RSRV 0x00000000c0000000ull
172 #define AMDIOMMU_CTRL_DUALEVNTLOG_MASK 0x0000000300000000ull /* Dual Event Log En */
173 #define AMDIOMMU_CTRL_DUALEVNTLOG_A 0x0000000000000000ull /* Use Log A Buf */
174 #define AMDIOMMU_CTRL_DUALEVNTLOG_B 0x0000000100000000ull /* Use Log B Buf */
175 #define AMDIOMMU_CTRL_DUALEVNTLOG_SWAP 0x0000000200000000ull /* Auto-swap on full */
176 #define AMDIOMMU_CTRL_DUALEVNTLOG_RSRV 0x0000000300000000ull
177 #define AMDIOMMU_CTRL_DEVTABSEG_MASK 0x0000001c00000000ull /* Dev Table Segm */
178 #define AMDIOMMU_CTRL_DEVTABSEG_1 0x0000000000000000ull /* 1 Segment */
179 #define AMDIOMMU_CTRL_DEVTABSEG_2 0x0000000400000000ull /* 2 Segments */
180 #define AMDIOMMU_CTRL_DEVTABSEG_4 0x0000000800000000ull /* 4 Segments */
181 #define AMDIOMMU_CTRL_DEVTABSEG_8 0x0000000c00000000ull /* 8 Segments */
182 #define AMDIOMMU_CTRL_PRIVABRT_MASK 0x0000006000000000ull /* Privilege Abort En */
183 #define AMDIOMMU_CTRL_PRIVABRT_USR 0x0000000000000000ull /* Privilege Abort User */
184 #define AMDIOMMU_CTRL_PRIVABRT_ALL 0x0000002000000000ull /* Privilege Abort Always */
185 #define AMDIOMMU_CTRL_PPRAUTORSP_EN 0x0000008000000000ull /* PPR Auto Resp En */
186 #define AMDIOMMU_CTRL_MARC_EN 0x0000010000000000ull /* Memory Addr Routing En */
187 #define AMDIOMMU_CTRL_BLKSTOPMRK_EN 0x0000020000000000ull /* Block StopMark En */
188 #define AMDIOMMU_CTRL_PPRAUTORESPA_EN 0x0000040000000000ull /* PPR Auto Resp Always En */
189 #define AMDIOMMU_CTRL_NUMINTRREMAP_MASK 0x0000180000000000ull /* Remapping MSI mode */
190 #define AMDIOMMU_CTRL_NUMINTRREMAP_512 0x0000000000000000ull /* 512 max */
191 #define AMDIOMMU_CTRL_NUMINTRREMAP_2048 0x0000080000000000ull /* 2048 max */
192 #define AMDIOMMU_CTRL_EPH_EN 0x0000200000000000ull /* Enh PPR Handling En */
193 #define AMDIOMMU_CTRL_HADUP_MASK 0x0000c00000000000ull /* Access and Dirty in host PT */
194 #define AMDIOMMU_CTRL_GDUP_DIS 0x0001000000000000ull /* Dis Dirty in guest PT */
195 #define AMDIOMMU_CTRL_XT_EN 0x0004000000000000ull /* x2APIC mode */
196 #define AMDIOMMU_CTRL_INTCAPXT_EN 0x0008000000000000ull /* x2APIC mode for IOMMU intrs */
197 #define AMDIOMMU_CTRL_vCMD_EN 0x0010000000000000ull /* vCMD buffer proc En */
198 #define AMDIOMMU_CTRL_vIOMMU_EN 0x0020000000000000ull /* vIOMMU En */
199 #define AMDIOMMU_CTRL_GAUP_DIS 0x0040000000000000ull /* Dis Access in guest PT */
200 #define AMDIOMMU_CTRL_GAPPI_EN 0x0080000000000000ull /* Guest APIC phys proc intr En */
201 #define AMDIOMMU_CTRL_TMPM_EN 0x0100000000000000ull /* Tiered Mem Page Migration En */
202 #define AMDIOMMU_CTRL_GGCR3TRP_PHYS 0x0400000000000000ull /* GCR3 is GPA (otherwise SPA) */
203 #define AMDIOMMU_CTRL_IRTCACHE_DIS 0x0800000000000000ull /* IRT Caching Dis */
204 #define AMDIOMMU_CTRL_GSTBUFTRP_MODE 0x1000000000000000ull /* See spec */
205 #define AMDIOMMU_CTRL_SNPAVIC_MASK 0xe000000000000000ull /* MBZ */
210 #define AMDIOMMU_EFR_XT_SUP 0x0000000000000004ull /* x2APIC */
211 #define AMDIOMMU_EFR_HWEV_SUP 0x0000000000000100ull /* HW Event regs */
212 #define AMDIOMMU_EFR_PC_SUP 0x0000000000000200ull /* Perf counters */
213 #define AMDIOMMU_EFR_HATS_MASK 0x0000000000000c00ull /* Host Addr Trans Size */
214 #define AMDIOMMU_EFR_HATS_4LVL 0x0000000000000000ull
215 #define AMDIOMMU_EFR_HATS_5LVL 0x0000000000000400ull
216 #define AMDIOMMU_EFR_HATS_6LVL 0x0000000000000800ull
217 #define AMDIOMMU_EFR_DEVTBLSEG_MASK 0x000000c000000000ull /* DevTbl segmentation */
221 #define AMDIOMMU_CMDPTR_MASK 0x000000000007fff0ull
233 #define AMDIOMMU_HWEVS_HEV 0x00000001 /* HW Ev Valid */
234 #define AMDIOMMU_HWEVS_HEO 0x00000002 /* HW Ev Overfl */
242 #define AMDIOMMU_CMDEVS_EVOVRFLW 0x00000001
243 #define AMDIOMMU_CMDEVS_EVLOGINT 0x00000002
244 #define AMDIOMMU_CMDEVS_COMWAITINT 0x00000004
245 #define AMDIOMMU_CMDEVS_EVLOGRUN 0x00000008
246 #define AMDIOMMU_CMDEVS_CMDBUFRUN 0x00000010
247 #define AMDIOMMU_CMDEVS_PPROVRFLW 0x00000020
248 #define AMDIOMMU_CMDEVS_PPRINT 0x00000040
249 #define AMDIOMMU_CMDEVS_PPRLOGRUN 0x00000080
250 #define AMDIOMMU_CMDEVS_GALOGRUN 0x00000100
251 #define AMDIOMMU_CMDEVS_GALOVRFLW 0x00000200
252 #define AMDIOMMU_CMDEVS_GAINT 0x00000400
253 #define AMDIOMMU_CMDEVS_PPROVRFLWB 0x00000800
254 #define AMDIOMMU_CMDEVS_PPRLOGACTIVE 0x00001000
255 #define AMDIOMMU_CMDEVS_RESV1 0x00002000
256 #define AMDIOMMU_CMDEVS_RESV2 0x00004000
257 #define AMDIOMMU_CMDEVS_EVOVRFLWB 0x00008000
258 #define AMDIOMMU_CMDEVS_EVLOGACTIVE 0x00010000
259 #define AMDIOMMU_CMDEVS_PPROVRFLWEB 0x00020000
260 #define AMDIOMMU_CMDEVS_PPROVRFLWE 0x00040000
266 #define AMDIOMMU_EFR2_TMPMSUP 0x0000000000000004ull /* Tiered Mem Migration */
267 #define AMDIOMMU_EFR2_GCR3TRPM 0x0000000000000008ull /* GPA based GCR3 pointer in DTE */
268 #define AMDIOMMU_EFR2_GAPPID 0x0000000000000010ull /* masking of GAPIC PPI */
269 #define AMDIOMMU_EFR2_SNPAVIC_MASK 0x00000000000000e0ull /* SNP-enabled Adv intr features */
270 #define AMDIOMMU_EFR2_SNPAVIC_NO 0x0000000000000000ull /* No features supported */
271 #define AMDIOMMU_EFR2_SNPAVIC_REMAPV 0x0000000000000020ull /* Intr remapping with GVAPIC */
272 #define AMDIOMMU_EFR2_NUMINTRREMAP_MASK 0x0000000000000300ull /* Number of remapped intr per dev */
273 #define AMDIOMMU_EFR2_NUMINTRREMAP_512 0x0000000000000000ull /* 512 */
274 #define AMDIOMMU_EFR2_NUMINTRREMAP_2048 0x0000000000000100ull /* 2048 */
275 #define AMDIOMMU_EFR2_HTRANGEIGN 0x0000000000000800ull /* HT range is regular GPA */
333 #define AMDIOMMU_DTE_HAD_NAND 0x0 /* No Access, No Dirty */
334 #define AMDIOMMU_DTE_HAD_AND 0x1 /* Access, No Dirty */
335 #define AMDIOMMU_DTE_HAD_RSRV 0x2
336 #define AMDIOMMU_DTE_HAD_AD 0x3 /* Access, Dirty */
338 #define AMDIOMMU_DTE_PGMODE_1T1 0x0 /* SPA = GPA */
339 #define AMDIOMMU_DTE_PGMODE_1LV 0x1 /* 1 Level PT */
340 #define AMDIOMMU_DTE_PGMODE_2LV 0x2 /* 2 Level PT */
341 #define AMDIOMMU_DTE_PGMODE_3LV 0x3 /* 3 Level PT */
342 #define AMDIOMMU_DTE_PGMODE_4LV 0x4 /* 4 Level PT */
343 #define AMDIOMMU_DTE_PGMODE_5LV 0x5 /* 5 Level PT */
344 #define AMDIOMMU_DTE_PGMODE_6LV 0x6 /* 6 Level PT */
345 #define AMDIOMMU_DTE_PGMODE_RSRV 0x7
347 #define AMDIOMMU_DTE_GLX_1LV 0x0 /* 1 Level GCR3 */
348 #define AMDIOMMU_DTE_GLX_2LV 0x1 /* 2 Level GCR3 */
349 #define AMDIOMMU_DTE_GLX_3LV 0x2 /* 3 Level GCR3 */
350 #define AMDIOMMU_DTE_GLX_RSRV 0x3
352 #define AMDIOMMU_DTE_PIOCTL_DIS 0x0
353 #define AMDIOMMU_DTE_PIOCTL_EN 0x1
354 #define AMDIOMMU_DTE_PIOCTL_MAP 0x2
355 #define AMDIOMMU_DTE_PIOCTL_RSRV 0x3
357 #define AMDIOMMU_DTE_SYSMGT_DIS 0x0 /* Target Abort */
358 #define AMDIOMMU_DTE_SYSMGT_FW 0x0 /* Forwarded All */
359 #define AMDIOMMU_DTE_SYSMGT_FWI 0x0 /* Forwarded INT */
360 #define AMDIOMMU_DTE_SYSMGT_T 0x0 /* Translated */
362 #define AMDIOMMU_DTE_GPM_4LV 0x0 /* 4 Level */
363 #define AMDIOMMU_DTE_GPM_5LV 0x1 /* 5 Level */
364 #define AMDIOMMU_DTE_GPM_RSRV1 0x2
365 #define AMDIOMMU_DTE_GPM_RSRV2 0x3
367 #define AMDIOMMU_DTE_INTCTL_DIS 0x0 /* Target Abort */
368 #define AMDIOMMU_DTE_INTCTL_FW 0x1 /* Forward Unmapped */
369 #define AMDIOMMU_DTE_INTCTL_MAP 0x2 /* Forward Remapped */
370 #define AMDIOMMU_DTE_INTCTL_RSRV 0x3
377 #define AMDIOMMU_PTE_PR 0x0001 /* Present, AKA V */
378 #define AMDIOMMU_IGN1 0x0002
379 #define AMDIOMMU_IGN2 0x0004
380 #define AMDIOMMU_IGN3 0x0008
381 #define AMDIOMMU_IGN4 0x0010
382 #define AMDIOMMU_PTE_A 0x0020 /* Accessed */
383 #define AMDIOMMU_PTE_D 0x0040 /* Dirty */
384 #define AMDIOMMU_IGN5 0x0080
385 #define AMDIOMMU_IGN6 0x0100
386 #define AMDIOMMU_PTE_NLVL_MASK 0x0e00 /* Next Level */
388 #define AMDIOMMU_PTE_NLVL_7h 0x0e00 /* Magic Next Level */
389 #define AMDIOMMU_PTE_PA_MASK 0x000ffffffffff000ull
391 #define AMDIOMMU_PTE_PMC_MASK 0x0600000000000000ull /* Page Migr */
392 #define AMDIOMMU_PTE_U 0x0800000000000000ull /* ATS.U */
393 #define AMDIOMMU_PTE_FC 0x1000000000000000ull /* Force Coh */
394 #define AMDIOMMU_PTE_IR 0x2000000000000000ull /* Read Perm */
395 #define AMDIOMMU_PTE_IW 0x4000000000000000ull /* Write Perm */
396 #define AMDIOMMU_PTE_IGN7 0x8000000000000000ull
402 /* vAPIC is not enabled, guestmode = 0 */
404 u_int remapen:1; /* 0 - Target Abort */
417 /* vAPIC is enabled, guestmode = 0 */
419 u_int remapen:1; /* 0 - Target Abort */
437 u_int remapen:1; /* 0 - Target Abort */
455 /* vAPIC is enabled, guestmode = 0, x2APIC */
457 u_int remapen:1; /* 0 - Target Abort */
463 u_int dest0:24; /* Destination APIC 23:0 */
475 u_int remapen:1; /* 0 - Target Abort */
482 u_int dest0:24; /* Destination APIC for dorbell 23:0 */
493 #define AMDIOMMU_IRTE_INTTYPE_FIXED 0
663 #define AMDIOMMU_CMD_COMPLETION_WAIT 0x1
664 #define AMDIOMMU_CMD_INVALIDATE_DEVTAB_ENTRY 0x2
665 #define AMDIOMMU_CMD_INVALIDATE_IOMMU_PAGES 0x3
666 #define AMDIOMMU_CMD_INVALIDATE_IOTLB_PAGES 0x4
667 #define AMDIOMMU_CMD_INVALIDATE_INTERRUPT_TABLE 0x5
668 #define AMDIOMMU_CMD_PREFETCH_IOMMU_PAGES 0x6
669 #define AMDIOMMU_CMD_COMPLETE_PPR_REQUEST 0x7
670 #define AMDIOMMU_CMD_INVALIDATE_IOMMU_ALL 0x8
671 #define AMDIOMMU_CMD_INSERT_GUEST_EVENT 0x9
672 #define AMDIOMMU_CMD_RESET_VMMIO 0xa
753 #define AMDIOMMU_EV_ILL_DEV_TABLE_ENTRY 0x1
754 #define AMDIOMMU_EV_IO_PAGE_FAULT 0x2
755 #define AMDIOMMU_EV_DEV_TAB_HW_ERROR 0x3
756 #define AMDIOMMU_EV_PAGE_TAB_HW_ERROR 0x4
757 #define AMDIOMMU_EV_ILL_CMD_ERROR 0x5
758 #define AMDIOMMU_EV_CMD_HW_ERROR 0x6
759 #define AMDIOMMU_EV_IOTLB_INV_TIMEOUT 0x7
760 #define AMDIOMMU_EV_INVALID_DEV_REQ 0x8
761 #define AMDIOMMU_EV_INVALID_PPR_REQ 0x9
762 #define AMDIOMMU_EV_COUNTER_ZERO 0xa /* Typo in table 42? */