54 #define REG_EQCR_PI_CINH    0x0000
55 #define REG_EQCR_CI_CINH    0x0004
56 #define REG_EQCR_ITR        0x0008
57 #define REG_DQRR_PI_CINH    0x0040
58 #define REG_DQRR_CI_CINH    0x0044
59 #define REG_DQRR_ITR        0x0048
60 #define REG_DQRR_DCAP       0x0050
61 #define REG_DQRR_SDQCR      0x0054
62 #define REG_DQRR_VDQCR      0x0058
63 #define REG_DQRR_PDQCR      0x005c
64 #define REG_MR_PI_CINH      0x0080
65 #define REG_MR_CI_CINH      0x0084
66 #define REG_MR_ITR          0x0088
67 #define REG_CFG             0x0100
68 #define REG_ISR             0x0e00
69 #define REG_IER             0x0e04
70 #define REG_ISDR            0x0e08
71 #define REG_IIR             0x0e0c
72 #define REG_ITPR            0x0e14
75 #define CL_EQCR             0x0000
76 #define CL_DQRR             0x1000
77 #define CL_MR               0x2000
78 #define CL_EQCR_PI_CENA     0x3000
79 #define CL_EQCR_CI_CENA     0x3100
80 #define CL_DQRR_PI_CENA     0x3200
81 #define CL_DQRR_CI_CENA     0x3300
82 #define CL_MR_PI_CENA       0x3400
83 #define CL_MR_CI_CENA       0x3500
84 #define CL_RORI_CENA        0x3600
85 #define CL_CR               0x3800
86 #define CL_RR0              0x3900
87 #define CL_RR1              0x3940
223             QM_EQCR_VERB_VBIT : 0);  in qm_eqcr_init()
229     eqcr->busy = 0;  in qm_eqcr_init()
235     cfg = (qm_in(CFG) & 0x00ffffff) |  in qm_eqcr_init()
236         ((pmode & 0x3) << 24);    /* QCSP_CFG::EPM */  in qm_eqcr_init()
238     return 0;  in qm_eqcr_init()
279     eqcr->busy = 0;  in qm_eqcr_abort()
306     ASSERT_COND(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff)); \
307     ASSERT_COND(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff)); \
308 } while(0)
329     eqcr->busy = 0;  in qmPortalEqcrPciCommit()
357     eqcr->busy = 0;  in qmPortalEqcrPceCommit()
376     eqcr->busy = 0;  in qmPortalEqcrPvbCommit()
472     qm_out(CFG, (qm_in(CFG) & 0xff0fffff) |  in qm_dqrr_set_maxfill()
489     qm_out(DQRR_SDQCR, 0);  in qm_dqrr_init()
490     qm_out(DQRR_VDQCR, 0);  in qm_dqrr_init()
491     qm_out(DQRR_PDQCR, 0);  in qm_dqrr_init()
498             QM_DQRR_VERB_VBIT : 0);  in qm_dqrr_init()
505     dqrr->flags = 0;  in qm_dqrr_init()
514     cfg = (qm_in(CFG) & 0xff000f00) |  in qm_dqrr_init()
518         (stash_ring ? 0x80 : 0) |        /* RE */  in qm_dqrr_init()
519         (0 ? 0x40 : 0) |            /* Ignore RP */  in qm_dqrr_init()
520         (stash_data ? 0x20 : 0) |        /* SE */  in qm_dqrr_init()
521         (0 ? 0x10 : 0);                /* Ignore SP */  in qm_dqrr_init()
620     return 0;  in qmPortalDqrrPvbUpdate()
680     qm_out(DQRR_DCAP, (0 << 8) |    /* S */  in qmPortalDqrrDcaConsume1()
681         ((uint32_t)(park ? 1 : 0) << 6) |    /* PK */  in qmPortalDqrrDcaConsume1()
697     qm_out(DQRR_DCAP, (0 << 8) |        /* DQRR_DCAP::S */  in qmPortalDqrrDcaConsume1ptr()
698         ((uint32_t)(park ? 1 : 0) << 6) |        /* DQRR_DCAP::PK */  in qmPortalDqrrDcaConsume1ptr()
757     qm_out(DQRR_DCAP, (0 << 8) |        /* S */  in qm_dqrr_park()
768     qm_out(DQRR_DCAP, (0 << 8) |        /* S */  in qm_dqrr_park_ci()
816     return (uint8_t)((qm_in(CFG) & 0x00f00000) >> 20);  in qm_dqrr_get_maxfill()
853     mr->vbit = (uint8_t)((qm_in(MR_PI_CINH) & QM_MR_SIZE) ?QM_MR_VERB_VBIT : 0);  in qm_mr_init()
862     cfg = (qm_in(CFG) & 0xfffff0ff) |  in qm_mr_init()
1042             0 : 1);  in qm_mc_init()
1043     mc->vbit = (uint8_t)(mc->rridx ? QM_MCC_VERB_VBIT : 0);  in qm_mc_init()