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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
H A Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
H A Dqcom,sm6150-dpu.yaml52 reg = <0x0ae01000 0x8f000>,
53 <0x0aeb0000 0x2008>;
69 interrupts = <0>;
73 #size-cells = <0>;
75 port@0 {
76 reg = <0>;
H A Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
H A Dqcom,x1e80100-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^phy@[0-9a-f]+$":
74 reg = <0x0ae00000 0x1000>;
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
95 iommus = <&apps_smmu 0x1c00 0x2>;
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sm6350-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
H A Dqcom,sm6150-mdss.yaml47 "^display-controller@[0-9a-f]+$":
54 "^displayport-controller@[0-9a-f]+$":
62 "^dsi@[0-9a-f]+$":
71 "^phy@[0-9a-f]+$":
92 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x800 0x0>;
117 reg = <0x0ae01000 0x8f000>,
118 <0x0aeb0000 0x2008>;
134 interrupts = <0>;
138 #size-cells = <0>;
[all …]
H A Dqcom,sm8350-mdss.yaml53 "^display-controller@[0-9a-f]+$":
61 "^displayport-controller@[0-9a-f]+$":
69 "^dsi@[0-9a-f]+$":
79 "^phy@[0-9a-f]+$":
101 reg = <0x0ae00000 0x1000>;
104 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
105 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
119 iommus = <&apps_smmu 0x820 0x402>;
131 reg = <0x0ae01000 0x8f000>,
132 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,glymur-mdss.yaml42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
56 "^phy@[0-9a-f]+$":
79 reg = <0x0ae00000 0x1000>;
100 iommus = <&apps_smmu 0x1c00 0x2>;
111 reg = <0x0ae01000 0x8f000>,
112 <0x0aeb0000 0x2008>;
133 interrupts = <0>;
137 #size-cells = <0>;
139 port@0 {
[all …]
H A Dqcom,sdm670-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
[all …]
H A Dqcom,sm8650-mdss.yaml42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
89 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
90 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
106 iommus = <&apps_smmu 0x1c00 0x2>;
114 reg = <0x0ae01000 0x8f000>,
115 <0x0aeb0000 0x3000>;
[all …]
H A Dqcom,sc7180-mdss.yaml49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
99 reg = <0x0ae00000 0x1000>;
118 iommus = <&apps_smmu 0x820 0x402>;
126 reg = <0x0ae01000 0x8f000>,
127 <0x0aeb0000 0x2008>;
143 interrupts = <0>;
147 #size-cells = <0>;
[all …]
H A Dqcom,sm8150-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x800 0x420>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
140 interrupts = <0>;
144 #size-cells = <0>;
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x2800 0x402>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
147 interrupts = <0>;
151 #size-cells = <0>;
[all …]
H A Dqcom,qcs8300-mdss.yaml38 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
64 "^phy@[0-9a-f]+$":
92 reg = <0x0ae00000 0x1000>;
116 iommus = <&apps_smmu 0x1000 0x402>;
124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>;
145 interrupts = <0>;
148 #size-cells = <0>;
[all …]
H A Dqcom,sm8750-mdss.yaml42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
88 reg = <0x0ae00000 0x1000>;
108 iommus = <&apps_smmu 0x800 0x2>;
119 reg = <0x0ae01000 0x93000>,
120 <0x0aeb0000 0x3000>;
124 interrupts-extended = <&mdss 0>;
146 #size-cells = <0>;
[all …]
H A Dqcom,sar2130p-mdss.yaml43 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
107 iommus = <&apps_smmu 0x1c00 0x2>;
115 reg = <0x0ae01000 0x8f000>,
116 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
143 #size-cells = <0>;
[all …]
H A Dqcom,eliza-mdss.yaml42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
90 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x800 0x2>;
121 reg = <0x0ae01000 0x93000>,
122 <0x0aeb0000 0x3000>;
126 interrupts-extended = <&mdss 0>;
148 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
83 clocks = <&cpufreq_hw 0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0 0x100>;
[all …]
H A Dmonaco.dtsi35 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0 0x0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
105 reg = <0x0 0x200>;
131 reg = <0x0 0x300>;
[all …]
H A Dglymur.dtsi41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
49 power-domains = <&cpu_pd0>, <&scmi_perf 0>;
64 reg = <0x0 0x100>;
67 power-domains = <&cpu_pd1>, <&scmi_perf 0>;
76 reg = <0x0 0x200>;
79 power-domains = <&cpu_pd2>, <&scmi_perf 0>;
88 reg = <0x0 0x300>;
91 power-domains = <&cpu_pd3>, <&scmi_perf 0>;
[all …]