xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8750 Display MDSS
8
9maintainers:
10  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11
12description:
13  SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8750-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    items:
33      - description: Interconnect path from mdp0 port to the data bus
34      - description: Interconnect path from CPU to the reg bus
35
36  interconnect-names:
37    items:
38      - const: mdp0-mem
39      - const: cpu-cfg
40
41patternProperties:
42  "^display-controller@[0-9a-f]+$":
43    type: object
44    additionalProperties: true
45    properties:
46      compatible:
47        const: qcom,sm8750-dpu
48
49  "^displayport-controller@[0-9a-f]+$":
50    type: object
51    additionalProperties: true
52    properties:
53      compatible:
54        contains:
55          const: qcom,sm8750-dp
56
57  "^dsi@[0-9a-f]+$":
58    type: object
59    additionalProperties: true
60    properties:
61      compatible:
62        contains:
63          const: qcom,sm8750-dsi-ctrl
64
65  "^phy@[0-9a-f]+$":
66    type: object
67    additionalProperties: true
68    properties:
69      compatible:
70        const: qcom,sm8750-dsi-phy-3nm
71
72required:
73  - compatible
74
75unevaluatedProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/qcom,rpmh.h>
80    #include <dt-bindings/interconnect/qcom,icc.h>
81    #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
82    #include <dt-bindings/interrupt-controller/arm-gic.h>
83    #include <dt-bindings/phy/phy-qcom-qmp.h>
84    #include <dt-bindings/power/qcom,rpmhpd.h>
85
86    display-subsystem@ae00000 {
87            compatible = "qcom,sm8750-mdss";
88            reg = <0x0ae00000 0x1000>;
89            reg-names = "mdss";
90
91            interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
92
93            clocks = <&disp_cc_mdss_ahb_clk>,
94                     <&gcc_disp_hf_axi_clk>,
95                     <&disp_cc_mdss_mdp_clk>;
96
97            interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
98                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
99                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
100                             &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
101            interconnect-names = "mdp0-mem",
102                                 "cpu-cfg";
103
104            resets = <&disp_cc_mdss_core_bcr>;
105
106            power-domains = <&mdss_gdsc>;
107
108            iommus = <&apps_smmu 0x800 0x2>;
109
110            interrupt-controller;
111            #interrupt-cells = <1>;
112
113            #address-cells = <1>;
114            #size-cells = <1>;
115            ranges;
116
117            display-controller@ae01000 {
118                compatible = "qcom,sm8750-dpu";
119                reg = <0x0ae01000 0x93000>,
120                      <0x0aeb0000 0x2008>;
121                reg-names = "mdp",
122                            "vbif";
123
124                interrupts-extended = <&mdss 0>;
125
126                clocks = <&gcc_disp_hf_axi_clk>,
127                         <&disp_cc_mdss_ahb_clk>,
128                         <&disp_cc_mdss_mdp_lut_clk>,
129                         <&disp_cc_mdss_mdp_clk>,
130                         <&disp_cc_mdss_vsync_clk>;
131                clock-names = "nrt_bus",
132                              "iface",
133                              "lut",
134                              "core",
135                              "vsync";
136
137                assigned-clocks = <&disp_cc_mdss_vsync_clk>;
138                assigned-clock-rates = <19200000>;
139
140                operating-points-v2 = <&mdp_opp_table>;
141
142                power-domains = <&rpmhpd RPMHPD_MMCX>;
143
144                ports {
145                    #address-cells = <1>;
146                    #size-cells = <0>;
147
148                    port@0 {
149                        reg = <0>;
150
151                        dpu_intf1_out: endpoint {
152                            remote-endpoint = <&mdss_dsi0_in>;
153                        };
154                    };
155
156                    port@1 {
157                        reg = <1>;
158
159                        dpu_intf2_out: endpoint {
160                            remote-endpoint = <&mdss_dsi1_in>;
161                        };
162                    };
163
164                    port@2 {
165                        reg = <2>;
166
167                        dpu_intf0_out: endpoint {
168                            remote-endpoint = <&mdss_dp0_in>;
169                        };
170                    };
171                };
172
173                mdp_opp_table: opp-table {
174                    compatible = "operating-points-v2";
175
176                    opp-207000000 {
177                        opp-hz = /bits/ 64 <207000000>;
178                        required-opps = <&rpmhpd_opp_low_svs>;
179                    };
180
181                    opp-337000000 {
182                        opp-hz = /bits/ 64 <337000000>;
183                        required-opps = <&rpmhpd_opp_svs>;
184                    };
185
186                    opp-417000000 {
187                        opp-hz = /bits/ 64 <417000000>;
188                        required-opps = <&rpmhpd_opp_svs_l1>;
189                    };
190
191                    opp-532000000 {
192                        opp-hz = /bits/ 64 <532000000>;
193                        required-opps = <&rpmhpd_opp_nom>;
194                    };
195
196                    opp-575000000 {
197                        opp-hz = /bits/ 64 <575000000>;
198                        required-opps = <&rpmhpd_opp_nom_l1>;
199                    };
200                };
201            };
202
203            dsi@ae94000 {
204                compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
205                reg = <0x0ae94000 0x400>;
206                reg-names = "dsi_ctrl";
207
208                interrupts-extended = <&mdss 4>;
209
210                clocks = <&disp_cc_mdss_byte0_clk>,
211                         <&disp_cc_mdss_byte0_intf_clk>,
212                         <&disp_cc_mdss_pclk0_clk>,
213                         <&disp_cc_mdss_esc0_clk>,
214                         <&disp_cc_mdss_ahb_clk>,
215                         <&gcc_disp_hf_axi_clk>,
216                         <&mdss_dsi0_phy 1>,
217                         <&mdss_dsi0_phy 0>,
218                         <&disp_cc_esync0_clk>,
219                         <&disp_cc_osc_clk>,
220                         <&disp_cc_mdss_byte0_clk_src>,
221                         <&disp_cc_mdss_pclk0_clk_src>;
222                clock-names = "byte",
223                              "byte_intf",
224                              "pixel",
225                              "core",
226                              "iface",
227                              "bus",
228                              "dsi_pll_pixel",
229                              "dsi_pll_byte",
230                              "esync",
231                              "osc",
232                              "byte_src",
233                              "pixel_src";
234
235                operating-points-v2 = <&mdss_dsi_opp_table>;
236
237                power-domains = <&rpmhpd RPMHPD_MMCX>;
238
239                phys = <&mdss_dsi0_phy>;
240                phy-names = "dsi";
241
242                vdda-supply = <&vreg_l3g_1p2>;
243
244                #address-cells = <1>;
245                #size-cells = <0>;
246
247                ports {
248                    #address-cells = <1>;
249                    #size-cells = <0>;
250
251                    port@0 {
252                        reg = <0>;
253
254                        mdss_dsi0_in: endpoint {
255                            remote-endpoint = <&dpu_intf1_out>;
256                        };
257                    };
258
259                    port@1 {
260                        reg = <1>;
261
262                        mdss_dsi0_out: endpoint {
263                            remote-endpoint = <&panel0_in>;
264                            data-lanes = <0 1 2 3>;
265                        };
266                    };
267                };
268
269                mdss_dsi_opp_table: opp-table {
270                    compatible = "operating-points-v2";
271
272                    opp-187500000 {
273                        opp-hz = /bits/ 64 <187500000>;
274                        required-opps = <&rpmhpd_opp_low_svs>;
275                    };
276
277                    opp-300000000 {
278                        opp-hz = /bits/ 64 <300000000>;
279                        required-opps = <&rpmhpd_opp_svs>;
280                    };
281
282                    opp-358000000 {
283                        opp-hz = /bits/ 64 <358000000>;
284                        required-opps = <&rpmhpd_opp_svs_l1>;
285                    };
286                };
287            };
288
289            mdss_dsi0_phy: phy@ae95000 {
290                compatible = "qcom,sm8750-dsi-phy-3nm";
291                reg = <0x0ae95000 0x200>,
292                      <0x0ae95200 0x280>,
293                      <0x0ae95500 0x400>;
294                reg-names = "dsi_phy",
295                            "dsi_phy_lane",
296                            "dsi_pll";
297
298                clocks = <&disp_cc_mdss_ahb_clk>,
299                         <&rpmhcc RPMH_CXO_CLK>;
300                clock-names = "iface",
301                              "ref";
302
303                vdds-supply = <&vreg_l3i_0p88>;
304
305                #clock-cells = <1>;
306                #phy-cells = <0>;
307            };
308
309            dsi@ae96000 {
310                compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
311                reg = <0x0ae96000 0x400>;
312                reg-names = "dsi_ctrl";
313
314                interrupts-extended = <&mdss 5>;
315
316                clocks = <&disp_cc_mdss_byte1_clk>,
317                         <&disp_cc_mdss_byte1_intf_clk>,
318                         <&disp_cc_mdss_pclk1_clk>,
319                         <&disp_cc_mdss_esc1_clk>,
320                         <&disp_cc_mdss_ahb_clk>,
321                         <&gcc_disp_hf_axi_clk>,
322                         <&mdss_dsi1_phy 1>,
323                         <&mdss_dsi1_phy 0>,
324                         <&disp_cc_esync1_clk>,
325                         <&disp_cc_osc_clk>,
326                         <&disp_cc_mdss_byte1_clk_src>,
327                         <&disp_cc_mdss_pclk1_clk_src>;
328                clock-names = "byte",
329                              "byte_intf",
330                              "pixel",
331                              "core",
332                              "iface",
333                              "bus",
334                              "dsi_pll_pixel",
335                              "dsi_pll_byte",
336                              "esync",
337                              "osc",
338                              "byte_src",
339                              "pixel_src";
340
341                operating-points-v2 = <&mdss_dsi_opp_table>;
342
343                power-domains = <&rpmhpd RPMHPD_MMCX>;
344
345                phys = <&mdss_dsi1_phy>;
346                phy-names = "dsi";
347
348                #address-cells = <1>;
349                #size-cells = <0>;
350
351                ports {
352                    #address-cells = <1>;
353                    #size-cells = <0>;
354
355                    port@0 {
356                        reg = <0>;
357
358                        mdss_dsi1_in: endpoint {
359                            remote-endpoint = <&dpu_intf2_out>;
360                        };
361                    };
362
363                    port@1 {
364                        reg = <1>;
365
366                        mdss_dsi1_out: endpoint {
367                        };
368                    };
369                };
370            };
371
372            mdss_dsi1_phy: phy@ae97000 {
373                compatible = "qcom,sm8750-dsi-phy-3nm";
374                reg = <0x0ae97000 0x200>,
375                      <0x0ae97200 0x280>,
376                      <0x0ae97500 0x400>;
377                reg-names = "dsi_phy",
378                            "dsi_phy_lane",
379                            "dsi_pll";
380
381                clocks = <&disp_cc_mdss_ahb_clk>,
382                         <&rpmhcc RPMH_CXO_CLK>;
383                clock-names = "iface",
384                              "ref";
385
386                #clock-cells = <1>;
387                #phy-cells = <0>;
388            };
389
390            displayport-controller@af54000 {
391                compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
392                reg = <0xaf54000 0x104>,
393                      <0xaf54200 0xc0>,
394                      <0xaf55000 0x770>,
395                      <0xaf56000 0x9c>,
396                      <0xaf57000 0x9c>;
397
398                interrupts-extended = <&mdss 12>;
399
400                clocks = <&disp_cc_mdss_ahb_clk>,
401                         <&disp_cc_mdss_dptx0_aux_clk>,
402                         <&disp_cc_mdss_dptx0_link_clk>,
403                         <&disp_cc_mdss_dptx0_link_intf_clk>,
404                         <&disp_cc_mdss_dptx0_pixel0_clk>;
405                clock-names = "core_iface",
406                              "core_aux",
407                              "ctrl_link",
408                              "ctrl_link_iface",
409                              "stream_pixel";
410
411                assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
412                                  <&disp_cc_mdss_dptx0_pixel0_clk_src>;
413                assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
414                                         <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
415
416                operating-points-v2 = <&dp_opp_table>;
417
418                power-domains = <&rpmhpd RPMHPD_MMCX>;
419
420                phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
421                phy-names = "dp";
422
423                #sound-dai-cells = <0>;
424
425                dp_opp_table: opp-table {
426                    compatible = "operating-points-v2";
427
428                    opp-192000000 {
429                        opp-hz = /bits/ 64 <192000000>;
430                        required-opps = <&rpmhpd_opp_low_svs_d1>;
431                    };
432
433                    opp-270000000 {
434                        opp-hz = /bits/ 64 <270000000>;
435                        required-opps = <&rpmhpd_opp_low_svs>;
436                    };
437
438                    opp-540000000 {
439                        opp-hz = /bits/ 64 <540000000>;
440                        required-opps = <&rpmhpd_opp_svs_l1>;
441                    };
442
443                    opp-810000000 {
444                        opp-hz = /bits/ 64 <810000000>;
445                        required-opps = <&rpmhpd_opp_nom>;
446                    };
447                };
448
449                ports {
450                    #address-cells = <1>;
451                    #size-cells = <0>;
452
453                    port@0 {
454                        reg = <0>;
455
456                        mdss_dp0_in: endpoint {
457                            remote-endpoint = <&dpu_intf0_out>;
458                        };
459                    };
460
461                    port@1 {
462                        reg = <1>;
463
464                        mdss_dp0_out: endpoint {
465                            remote-endpoint = <&usb_dp_qmpphy_dp_in>;
466                        };
467                    };
468                };
469            };
470        };
471