xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml (revision 96c84703f1cf6ea43617f9565166681cd71df104) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6150 Display DPU
8
9maintainers:
10  - Abhinav Kumar <quic_abhinavk@quicinc.com>
11  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12
13$ref: /schemas/display/msm/dpu-common.yaml#
14
15properties:
16  compatible:
17    const: qcom,sm6150-dpu
18
19  reg:
20    items:
21      - description: Address offset and size for mdp register set
22      - description: Address offset and size for vbif register set
23
24  reg-names:
25    items:
26      - const: mdp
27      - const: vbif
28
29  clocks:
30    items:
31      - description: Display ahb clock
32      - description: Display hf axi clock
33      - description: Display core clock
34      - description: Display vsync clock
35
36  clock-names:
37    items:
38      - const: iface
39      - const: bus
40      - const: core
41      - const: vsync
42
43unevaluatedProperties: false
44
45examples:
46  - |
47    #include <dt-bindings/interrupt-controller/arm-gic.h>
48    #include <dt-bindings/power/qcom,rpmhpd.h>
49
50    display-controller@ae01000 {
51        compatible = "qcom,sm6150-dpu";
52        reg = <0x0ae01000 0x8f000>,
53              <0x0aeb0000 0x2008>;
54        reg-names = "mdp", "vbif";
55
56        clocks = <&dispcc_mdss_ahb_clk>,
57                 <&gcc_disp_hf_axi_clk>,
58                 <&dispcc_mdss_mdp_clk>,
59                 <&dispcc_mdss_vsync_clk>;
60        clock-names = "iface", "bus", "core", "vsync";
61
62        assigned-clocks = <&dispcc_mdss_vsync_clk>;
63        assigned-clock-rates = <19200000>;
64
65        operating-points-v2 = <&mdp_opp_table>;
66        power-domains = <&rpmhpd RPMHPD_CX>;
67
68        interrupt-parent = <&mdss>;
69        interrupts = <0>;
70
71        ports {
72            #address-cells = <1>;
73            #size-cells = <0>;
74
75            port@0 {
76                reg = <0>;
77                dpu_intf0_out: endpoint {
78                };
79            };
80
81            port@1 {
82                reg = <1>;
83                dpu_intf1_out: endpoint {
84                  remote-endpoint = <&mdss_dsi0_in>;
85                };
86            };
87        };
88
89        mdp_opp_table: opp-table {
90            compatible = "operating-points-v2";
91
92            opp-19200000 {
93              opp-hz = /bits/ 64 <19200000>;
94              required-opps = <&rpmhpd_opp_low_svs>;
95            };
96
97            opp-25600000 {
98              opp-hz = /bits/ 64 <25600000>;
99              required-opps = <&rpmhpd_opp_svs>;
100            };
101
102            opp-307200000 {
103              opp-hz = /bits/ 64 <307200000>;
104              required-opps = <&rpmhpd_opp_nom>;
105            };
106        };
107    };
108...
109