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/freebsd/sys/arm64/include/
H A Dcmn600_reg.h34 #define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */
36 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32)
68 #define POR_CFGM_NODE_INFO 0x0000 /* ro */
69 #define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL
71 #define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000
73 #define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff
74 #define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0
76 #define NODE_ID_SUB_MASK 0x3
77 #define NODE_ID_SUB_SHIFT 0
78 #define NODE_ID_PORT_MASK 0x4
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/arm/ti/
H A Dti_pruss.h32 #define PRUSS_AM18XX_INTC 0x04000
33 #define PRUSS_AM18XX_REV 0x4e825900
34 #define PRUSS_AM33XX_REV 0x4e82A900
35 #define PRUSS_AM33XX_INTC 0x20000
37 #define PRUSS_INTC_GER (PRUSS_AM33XX_INTC + 0x0010)
38 #define PRUSS_INTC_SISR (PRUSS_AM33XX_INTC + 0x0020)
39 #define PRUSS_INTC_SICR (PRUSS_AM33XX_INTC + 0x0024)
40 #define PRUSS_INTC_EISR (PRUSS_AM33XX_INTC + 0x0028)
41 #define PRUSS_INTC_EICR (PRUSS_AM33XX_INTC + 0x002C)
42 #define PRUSS_INTC_HIEISR (PRUSS_AM33XX_INTC + 0x0034)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
H A Dam3874-iceboard.dts31 reg = <0x80000000 0x40000000>; /* 1 GB */
47 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
65 ethphy0: ethernet-phy@0 {
66 reg = <0x2>;
69 rxdv-skew-ps = <0>;
71 rxd3-skew-ps = <0>;
72 rxd2-skew-ps = <0>;
73 rxd1-skew-ps = <0>;
74 rxd0-skew-ps = <0>;
80 reg = <0x1>;
[all …]
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/dev/syscons/
H A Dscvgarndr.c54 #define SC_RENDER_DEBUG 0
108 RENDERER(mda, 0, txtrndrsw, vga_set);
109 RENDERER(cga, 0, txtrndrsw, vga_set);
110 RENDERER(ega, 0, txtrndrsw, vga_set);
111 RENDERER(vga, 0, txtrndrsw, vga_set);
161 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8200,
162 0x8400, 0x8400, 0x8400, 0x9200, 0xB200, 0xA900, 0xC900, 0x8600, }, {
163 0x0000, 0x4000, 0x6000, 0x7000, 0x7800, 0x7C00, 0x7E00, 0x7C00,
164 0x7800, 0x7800, 0x7800, 0x6C00, 0x4C00, 0x4600, 0x0600, 0x0000, },
169 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8700,
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
[all...]
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpswreg.h32 #define CPSW_SS_OFFSET 0x0000
33 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
39 #define CPSW_PORT_OFFSET 0x0100
40 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
41 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
42 #define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
[all …]
/freebsd/sys/ufs/ufs/
H A Dquota.h58 #define USRQUOTA 0 /* element used for user quotas */
77 #define SUBCMDMASK 0x00ff
81 #define Q_QUOTAON 0x0100 /* enable quotas */
82 #define Q_QUOTAOFF 0x0200 /* disable quotas */
83 #define Q_GETQUOTA32 0x0300 /* get limits and usage (32-bit version) */
84 #define Q_SETQUOTA32 0x0400 /* set limits and usage (32-bit version) */
85 #define Q_SETUSE32 0x0500 /* set usage (32-bit version) */
86 #define Q_SYNC 0x0600 /* sync disk copy of a filesystems quotas */
87 #define Q_GETQUOTA 0x0700 /* get limits and usage (64-bit version) */
88 #define Q_SETQUOTA 0x0800 /* set limits and usage (64-bit version) */
[all …]
/freebsd/sys/dev/sis/
H A Dif_sisreg.h45 #define SIS_CSR 0x00
46 #define SIS_CFG 0x04
47 #define SIS_EECTL 0x08
48 #define SIS_PCICTL 0x0C
49 #define SIS_ISR 0x10
50 #define SIS_IMR 0x14
51 #define SIS_IER 0x18
52 #define SIS_PHYCTL 0x1C
53 #define SIS_TX_LISTPTR 0x20
54 #define SIS_TX_CFG 0x24
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd/sys/dev/irdma/
H A Dirdma_user.h55 #define IRDMA_MAX_MR_SIZE 0x200000000000ULL
57 #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01
58 #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02
59 #define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04
60 #define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05
61 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08
62 #define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a
63 #define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10
64 #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20
65 #define IRDMA_ACCESS_FLAGS_ALL 0x3f
[all …]
/freebsd/stand/i386/libi386/
H A Dtextvidc.c54 #define DEFAULT_BGCOLOR 0
102 if (vidc_started && arg == 0) in vidc_init()
103 return (0); in vidc_init()
113 for (i = 0; i < 10 && vidc_ischar(); i++) in vidc_init()
115 return (0); /* XXX reinit? */ in vidc_init()
122 v86.ctl = 0; in vidc_biosputchar()
123 v86.addr = 0x10; in vidc_biosputchar()
124 v86.eax = 0xe00 | (c & 0xff); in vidc_biosputchar()
125 v86.ebx = 0x7; in vidc_biosputchar()
143 for (i = 0; i < n; i++) in vidc_rawputchar()
[all …]
/freebsd/sys/dev/sound/pci/hda/
H A Dhdac.h40 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
43 #define INTEL_VENDORID 0x8086
44 #define HDA_INTEL_CMLKLP HDA_MODEL_CONSTRUCT(INTEL, 0x02c8)
45 #define HDA_INTEL_CMLKH HDA_MODEL_CONSTRUCT(INTEL, 0x06c8)
46 #define HDA_INTEL_OAK HDA_MODEL_CONSTRUCT(INTEL, 0x080a)
47 #define HDA_INTEL_BAY HDA_MODEL_CONSTRUCT(INTEL, 0x0f04)
48 #define HDA_INTEL_HSW1 HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)
49 #define HDA_INTEL_HSW2 HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)
50 #define HDA_INTEL_HSW3 HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)
51 #define HDA_INTEL_BDW1 HDA_MODEL_CONSTRUCT(INTEL, 0x160c)
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dmsx11 0 string/b MGS MSX Gigamix MGSDRV3 music file,
12 >6 ubeshort 0x0D0A
16 >>8 string >\0 \b, title: %s
19 >6 uleshort 0x80
20 >>0x2E uleshort 0
21 >>>0x30 string >\0 \b, title: %s
24 0 string/b KSCC KSS music file v1.03
25 >0xE byte 0
26 >>0xF byte&0x02 0 \b, soundchips: AY-3-8910, SCC(+)
27 >>0xF byte&0x02 2 \b, soundchip(s): SN76489
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]
/freebsd/sys/dev/dwc/
H A Dif_dwc_rk.c56 #define RK3328_GRF_MAC_CON0 0x0900
57 #define MAC_CON0_GMAC2IO_TX_DL_CFG_MASK 0x7F
58 #define MAC_CON0_GMAC2IO_TX_DL_CFG_SHIFT 0
59 #define MAC_CON0_GMAC2IO_RX_DL_CFG_MASK 0x7F
62 #define RK3328_GRF_MAC_CON1 0x0904
63 #define MAC_CON1_GMAC2IO_GMAC_TXCLK_DLY_ENA (1 << 0)
66 #define MAC_CON1_GMAC2IO_GMII_CLK_SEL_125 (0 << 11)
76 #define MAC_CON1_GMAC2IO_RMII_CLK_SEL_2_5 (0 << 7)
79 #define MAC_CON1_GMAC2IO_MAC_SPEED_10 (0 << 2)
80 #define RK3328_GRF_MAC_CON2 0x0908
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
73 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
75 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
77 (((addr)[0] & (addr)[1] & (addr)[2] & \
78 (addr)[3] & (addr)[4] & (addr)[5]) == 0xf
[all...]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.c84 #define B2055_INITTAB_ENTRY_OK 0x01
85 #define B2055_INITTAB_UPLOAD 0x02
91 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
92 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
93 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
94 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
95 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
96 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
97 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
98 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
/freebsd/sys/dev/usb/serial/
H A Dumcs.h37 #define MCS7840_RDREQ 0x0d
38 #define MCS7840_WRREQ 0x0e
41 #define MCS7840_EEPROM_RW_WVALUE 0x0900
47 #define MCS7840_DEV_REG_SP1 0x00 /* Options for UART 1, R/W */
48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
55 #define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits,
58 #define MCS7840_DEV_REG_SP2 0x08 /* Options for UART 2, R/W */
59 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
[all …]

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