1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0-only 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ 4*f126890aSEmmanuel Vadot * 5*f126890aSEmmanuel Vadot * Based on "omap4.dtsi" 6*f126890aSEmmanuel Vadot */ 7*f126890aSEmmanuel Vadot 8*f126890aSEmmanuel Vadot#include "dra7.dtsi" 9*f126890aSEmmanuel Vadot 10*f126890aSEmmanuel Vadot/ { 11*f126890aSEmmanuel Vadot compatible = "ti,dra722", "ti,dra72", "ti,dra7"; 12*f126890aSEmmanuel Vadot 13*f126890aSEmmanuel Vadot aliases { 14*f126890aSEmmanuel Vadot rproc0 = &ipu1; 15*f126890aSEmmanuel Vadot rproc1 = &ipu2; 16*f126890aSEmmanuel Vadot rproc2 = &dsp1; 17*f126890aSEmmanuel Vadot }; 18*f126890aSEmmanuel Vadot 19*f126890aSEmmanuel Vadot pmu { 20*f126890aSEmmanuel Vadot compatible = "arm,cortex-a15-pmu"; 21*f126890aSEmmanuel Vadot interrupt-parent = <&wakeupgen>; 22*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 23*f126890aSEmmanuel Vadot }; 24*f126890aSEmmanuel Vadot}; 25*f126890aSEmmanuel Vadot 26*f126890aSEmmanuel Vadot&l4_per2 { 27*f126890aSEmmanuel Vadot target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 28*f126890aSEmmanuel Vadot compatible = "ti,sysc-omap4", "ti,sysc"; 29*f126890aSEmmanuel Vadot reg = <0x5b000 0x4>, 30*f126890aSEmmanuel Vadot <0x5b010 0x4>; 31*f126890aSEmmanuel Vadot reg-names = "rev", "sysc"; 32*f126890aSEmmanuel Vadot ti,sysc-midle = <SYSC_IDLE_FORCE>, 33*f126890aSEmmanuel Vadot <SYSC_IDLE_NO>; 34*f126890aSEmmanuel Vadot ti,sysc-sidle = <SYSC_IDLE_FORCE>, 35*f126890aSEmmanuel Vadot <SYSC_IDLE_NO>; 36*f126890aSEmmanuel Vadot clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; 37*f126890aSEmmanuel Vadot clock-names = "fck"; 38*f126890aSEmmanuel Vadot #address-cells = <1>; 39*f126890aSEmmanuel Vadot #size-cells = <1>; 40*f126890aSEmmanuel Vadot ranges = <0x0 0x5b000 0x1000>; 41*f126890aSEmmanuel Vadot 42*f126890aSEmmanuel Vadot cal: cal@0 { 43*f126890aSEmmanuel Vadot compatible = "ti,dra72-cal"; 44*f126890aSEmmanuel Vadot reg = <0x0000 0x400>, 45*f126890aSEmmanuel Vadot <0x0800 0x40>, 46*f126890aSEmmanuel Vadot <0x0900 0x40>; 47*f126890aSEmmanuel Vadot reg-names = "cal_top", 48*f126890aSEmmanuel Vadot "cal_rx_core0", 49*f126890aSEmmanuel Vadot "cal_rx_core1"; 50*f126890aSEmmanuel Vadot interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 51*f126890aSEmmanuel Vadot ti,camerrx-control = <&scm_conf 0xE94>; 52*f126890aSEmmanuel Vadot 53*f126890aSEmmanuel Vadot ports { 54*f126890aSEmmanuel Vadot #address-cells = <1>; 55*f126890aSEmmanuel Vadot #size-cells = <0>; 56*f126890aSEmmanuel Vadot 57*f126890aSEmmanuel Vadot csi2_0: port@0 { 58*f126890aSEmmanuel Vadot reg = <0>; 59*f126890aSEmmanuel Vadot }; 60*f126890aSEmmanuel Vadot csi2_1: port@1 { 61*f126890aSEmmanuel Vadot reg = <1>; 62*f126890aSEmmanuel Vadot }; 63*f126890aSEmmanuel Vadot }; 64*f126890aSEmmanuel Vadot }; 65*f126890aSEmmanuel Vadot }; 66*f126890aSEmmanuel Vadot}; 67*f126890aSEmmanuel Vadot 68*f126890aSEmmanuel Vadot&dss { 69*f126890aSEmmanuel Vadot reg = <0 0x80>, 70*f126890aSEmmanuel Vadot <0x4054 0x4>, 71*f126890aSEmmanuel Vadot <0x4300 0x20>; 72*f126890aSEmmanuel Vadot reg-names = "dss", "pll1_clkctrl", "pll1"; 73*f126890aSEmmanuel Vadot 74*f126890aSEmmanuel Vadot clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, 75*f126890aSEmmanuel Vadot <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; 76*f126890aSEmmanuel Vadot clock-names = "fck", "video1_clk"; 77*f126890aSEmmanuel Vadot}; 78*f126890aSEmmanuel Vadot 79*f126890aSEmmanuel Vadot&mailbox5 { 80*f126890aSEmmanuel Vadot mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { 81*f126890aSEmmanuel Vadot ti,mbox-tx = <6 2 2>; 82*f126890aSEmmanuel Vadot ti,mbox-rx = <4 2 2>; 83*f126890aSEmmanuel Vadot status = "disabled"; 84*f126890aSEmmanuel Vadot }; 85*f126890aSEmmanuel Vadot mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { 86*f126890aSEmmanuel Vadot ti,mbox-tx = <5 2 2>; 87*f126890aSEmmanuel Vadot ti,mbox-rx = <1 2 2>; 88*f126890aSEmmanuel Vadot status = "disabled"; 89*f126890aSEmmanuel Vadot }; 90*f126890aSEmmanuel Vadot}; 91*f126890aSEmmanuel Vadot 92*f126890aSEmmanuel Vadot&mailbox6 { 93*f126890aSEmmanuel Vadot mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { 94*f126890aSEmmanuel Vadot ti,mbox-tx = <6 2 2>; 95*f126890aSEmmanuel Vadot ti,mbox-rx = <4 2 2>; 96*f126890aSEmmanuel Vadot status = "disabled"; 97*f126890aSEmmanuel Vadot }; 98*f126890aSEmmanuel Vadot}; 99*f126890aSEmmanuel Vadot 100*f126890aSEmmanuel Vadot&pcie1_rc { 101*f126890aSEmmanuel Vadot compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; 102*f126890aSEmmanuel Vadot}; 103*f126890aSEmmanuel Vadot 104*f126890aSEmmanuel Vadot&pcie1_ep { 105*f126890aSEmmanuel Vadot compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; 106*f126890aSEmmanuel Vadot}; 107*f126890aSEmmanuel Vadot 108*f126890aSEmmanuel Vadot&pcie2_rc { 109*f126890aSEmmanuel Vadot compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; 110*f126890aSEmmanuel Vadot}; 111