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/freebsd/sys/contrib/device-tree/src/xtensa/
H A Dxtfpga-flash-128m.dtsi8 reg = <0x00000000 0x08000000>;
11 partition@0 {
13 reg = <0x00000000 0x06000000>;
17 reg = <0x06000000 0x00800000>;
21 reg = <0x06800000 0x017e0000>;
25 reg = <0x07fe0000 0x00020000>;
H A Dlx200mx.dts8 memory@0 {
10 reg = <0x00000000 0x06000000>;
H A Dxtfpga.dtsi9 …bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root…
12 memory@0 {
14 reg = <0x00000000 0x06000000>;
19 #size-cells = <0>;
20 cpu@0 {
22 reg = <0>;
30 * two cells: second cell == 0: internal irq number
39 #clock-cells = <0>;
49 ranges = <0x00000000 0xf0000000 0x10000000>;
52 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-db8500.dtsi8 operating-points = <998400 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
H A Dste-db8520.dtsi8 operating-points = <1152000 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm3384_viper.dtsi7 memory@0 {
11 reg = <0x06000000 0x02000000>,
12 <0x0e000000 0x02000000>;
17 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
30 #address-cells = <0>;
40 #clock-cells = <0>;
59 reg = <0x14e00048 0x4 0x14e0004c 0x4>,
60 <0x14e00350 0x4 0x14e00354 0x4>;
[all …]
/freebsd/sys/dev/igc/
H A Digc_i225.h40 #define NVM_INIT_CTRL_2_DEFAULT_I225 0X7243
41 #define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1
42 #define NVM_LED_1_CFG_DEFAULT_I225 0x0184
43 #define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C
45 #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002
46 #define IGC_MRQC_ENABLE_VMDQ 0x00000003
47 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
48 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
49 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
50 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
H A Dpci_init.c26 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); in mt76x2_mac_pbf_init()
27 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); in mt76x2_mac_pbf_init()
34 s8 offset = 0; in mt76x2_fixup_xtal()
38 offset = eep_val & 0x7f; in mt76x2_fixup_xtal()
39 if ((eep_val & 0xff) == 0xff) in mt76x2_fixup_xtal()
40 offset = 0; in mt76x2_fixup_xtal()
41 else if (eep_val & 0x80) in mt76x2_fixup_xtal()
42 offset = 0 - offset; in mt76x2_fixup_xtal()
45 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2_fixup_xtal()
47 eep_val &= 0xff; in mt76x2_fixup_xtal()
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_hashfilter.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00010008/0x00010008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
[all …]
H A Dt5fw_cfg_hashfilter.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
H A Dt5fw_cfg.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
H A Dt6fw_cfg.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00012008/0x00012008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml24 const: 0
95 port@0:
108 - port@0
165 reg = <0x01ee0000 0x10000>;
176 pinctrl-0 = <&hdmi_pins>;
180 #size-cells = <0>;
182 port@0 {
183 reg = <0>;
221 reg = <0x06000000 0x10000>;
234 pinctrl-0 = <&hdmi_pins>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212desc.h32 uint32_t ds_ctl0; /* DMA control 0 */
38 uint32_t status0;/* DMA status 0 */
42 uint32_t status0;/* DMA status 0 */
58 #define AR_FrameLen 0x00000fff /* frame length */
60 #define AR_XmitPower 0x003f0000 /* transmit power control */
62 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
63 #define AR_VEOL 0x00800000 /* virtual end-of-list */
64 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
[all …]
/freebsd/sys/dev/sound/pci/
H A Dallegro_reg.h49 #define PCI_LEGACY_AUDIO_CTRL 0x40
50 #define SOUND_BLASTER_ENABLE 0x00000001
51 #define FM_SYNTHESIS_ENABLE 0x00000002
52 #define GAME_PORT_ENABLE 0x00000004
53 #define MPU401_IO_ENABLE 0x00000008
54 #define MPU401_IRQ_ENABLE 0x00000010
55 #define ALIAS_10BIT_IO 0x00000020
56 #define SB_DMA_MASK 0x000000C0
57 #define SB_DMA_0 0x00000040
58 #define SB_DMA_1 0x00000040
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/freebsd/sys/dev/e1000/
H A De1000_vf.h44 #define E1000_DEV_ID_82576_VF 0x10CA
45 #define E1000_DEV_ID_I350_VF 0x1520
50 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
51 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
54 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
55 (0x0C00C + ((_n) * 0x40)))
57 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
59 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
60 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
61 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
[all …]
/freebsd/sys/dev/pci/controller/
H A Dpci_n1sdp.c62 #define AP_NS_SHARED_MEM_BASE 0x06000000
65 #define PCI_CFG_SPACE_SIZE 0x1000
73 uint32_t valid_bdfs[0];
98 for (i = 0; i < nitems(m); i++) { in n1sdp_init()
104 if (vaddr == 0) { in n1sdp_init()
114 PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh); in n1sdp_init()
115 if (error != 0) in n1sdp_init()
126 for (i = 0; i < table_count; i++) in n1sdp_init()
148 bdf = PCIE_ADDR_OFFSET(bus, slot, func, 0); in n1sdp_check_bdf()
[all...]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0c>;
92 reg = <0x10060000 0x100>;
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]

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