Lines Matching +full:0 +full:x06000000

44 #define E1000_DEV_ID_82576_VF		0x10CA
45 #define E1000_DEV_ID_I350_VF		0x1520
50 #define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
51 #define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
54 #define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
55 				 (0x0C00C + ((_n) * 0x40)))
57 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
59 #define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
60 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
61 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
62 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
63 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
64 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
65 #define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
66 #define E1000_SRRCTL_DROP_EN			0x80000000
68 #define E1000_SRRCTL_BSIZEPKT_MASK	0x0000007F
69 #define E1000_SRRCTL_BSIZEHDR_MASK	0x00003F00
72 #define E1000_EICR		0x01580 /* Ext. Interrupt Cause Read - R/clr */
73 #define E1000_EITR(_n)		(0x01680 + ((_n) << 2))
74 #define E1000_EICS		0x01520 /* Ext. Intr Cause Set -W0 */
75 #define E1000_EIMS		0x01524 /* Ext. Intr Mask Set/Read -RW */
76 #define E1000_EIMC		0x01528 /* Ext. Intr Mask Clear -WO */
77 #define E1000_EIAC		0x0152C /* Ext. Intr Auto Clear -RW */
78 #define E1000_EIAM		0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */
79 #define E1000_IVAR0		0x01700 /* Intr Vector Alloc (array) -RW */
80 #define E1000_IVAR_MISC		0x01740 /* IVAR for "other" causes -RW */
81 #define E1000_IVAR_VALID	0x80
116 #define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
134 #define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
135 #define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
136 #define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
137 #define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
138 #define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
139 #define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
140 #define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
141 #define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
153 #define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
154 #define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
159 	e1000_undefined = 0,
284 	e1000_promisc_disabled = 0,   /* all promisc modes disabled */