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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8939.yaml70 reg = <0x00580000 0x14000>;
/linux/arch/powerpc/boot/dts/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dc293pcie.dts46 reg = <0xf 0xffe1e000 0 0x2000>;
47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x2 0x0 0xf 0xffdf0000 0x00010000>;
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
58 reg = <0xf 0xffe0a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0x80000000
[all …]
H A Dp1010rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
46 reg = <0x00040000 0x00040000>;
52 reg = <0x00080000 0x00700000>;
58 reg = <0x00800000 0x01400000>;
66 reg = <0x01f00000 0x00100000>;
72 ifc_nand: nand@1,0 {
76 reg = <0x1 0x0 0x10000>;
79 cpld@3,0 {
83 reg = <0x3 0x0 0x0000020>;
[all …]
H A Dp1025twr.dtsi43 nor@0,0 {
47 reg = <0x0 0x0 0x4000000>;
51 partition@0 {
54 reg = <0x0 0x00040000>;
61 reg = <0x00040000 0x00040000>;
67 reg = <0x00080000 0x00580000>;
73 reg = <0x00600000 0x038c0000>;
80 reg = <0x03ec0000 0x00040000>;
89 reg = <0x03f00000 0x00100000>;
96 display@2,0 {
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7791-koelsch.dts68 reg = <0 0x40000000 0 0x40000000>;
73 reg = <2 0x00000000 0 0x40000000>;
79 pinctrl-0 = <&keyboard_pins>;
83 gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
111 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
215 states = <3300000 1>, <1800000 0>;
238 states = <3300000 1>, <1800000 0>;
261 states = <3300000 1>, <1800000 0>;
266 #clock-cells = <0>;
300 #clock-cells = <0>;
[all …]
/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
H A Dmsm8939.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
49 reg = <0x100>;
67 reg = <0x101>;
80 reg = <0x102>;
93 reg = <0x103>;
102 CPU4: cpu@0 {
106 reg = <0x0>;
124 reg = <0x1>;
[all …]
H A Dmsm8916.dtsi27 reg = <0 0x80000000 0 0>;
36 reg = <0x0 0x86000000 0x0 0x300000>;
42 reg = <0x0 0x86300000 0x0 0x100000>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
85 * alignment = <0x0 0x400000>;
86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
[all …]
/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_port.c24 #define DFLT_FQ_ID 0x00FFFFFF
27 #define PORT_BMI_FIFO_UNITS 0x100
34 #define PORT_IC_OFFSET_UNITS 0x10
38 #define BMI_PORT_REGS_OFFSET 0
39 #define QMI_PORT_REGS_OFFSET 0x400
40 #define HWP_PORT_REGS_OFFSET 0x800
59 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0
62 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f
64 #define QMI_PORT_CFG_EN 0x80000000
65 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
[all …]
/linux/drivers/net/ethernet/sun/
H A Dniu.h10 #define PIO 0x000000UL
11 #define FZC_PIO 0x080000UL
12 #define FZC_MAC 0x180000UL
13 #define FZC_IPP 0x280000UL
14 #define FFLP 0x300000UL
15 #define FZC_FFLP 0x380000UL
16 #define PIO_VADDR 0x400000UL
17 #define ZCP 0x500000UL
18 #define FZC_ZCP 0x580000UL
19 #define DMC 0x600000UL
[all …]