1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2e689cf4aSJeff Kirsher /* niu.h: Definitions for Neptune ethernet driver.
3e689cf4aSJeff Kirsher *
4e689cf4aSJeff Kirsher * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
5e689cf4aSJeff Kirsher */
6e689cf4aSJeff Kirsher
7e689cf4aSJeff Kirsher #ifndef _NIU_H
8e689cf4aSJeff Kirsher #define _NIU_H
9e689cf4aSJeff Kirsher
10e689cf4aSJeff Kirsher #define PIO 0x000000UL
11e689cf4aSJeff Kirsher #define FZC_PIO 0x080000UL
12e689cf4aSJeff Kirsher #define FZC_MAC 0x180000UL
13e689cf4aSJeff Kirsher #define FZC_IPP 0x280000UL
14e689cf4aSJeff Kirsher #define FFLP 0x300000UL
15e689cf4aSJeff Kirsher #define FZC_FFLP 0x380000UL
16e689cf4aSJeff Kirsher #define PIO_VADDR 0x400000UL
17e689cf4aSJeff Kirsher #define ZCP 0x500000UL
18e689cf4aSJeff Kirsher #define FZC_ZCP 0x580000UL
19e689cf4aSJeff Kirsher #define DMC 0x600000UL
20e689cf4aSJeff Kirsher #define FZC_DMC 0x680000UL
21e689cf4aSJeff Kirsher #define TXC 0x700000UL
22e689cf4aSJeff Kirsher #define FZC_TXC 0x780000UL
23e689cf4aSJeff Kirsher #define PIO_LDSV 0x800000UL
24e689cf4aSJeff Kirsher #define PIO_PIO_LDGIM 0x900000UL
25e689cf4aSJeff Kirsher #define PIO_IMASK0 0xa00000UL
26e689cf4aSJeff Kirsher #define PIO_IMASK1 0xb00000UL
27e689cf4aSJeff Kirsher #define FZC_PROM 0xc80000UL
28e689cf4aSJeff Kirsher #define FZC_PIM 0xd80000UL
29e689cf4aSJeff Kirsher
30e689cf4aSJeff Kirsher #define LDSV0(LDG) (PIO_LDSV + 0x00000UL + (LDG) * 0x2000UL)
31e689cf4aSJeff Kirsher #define LDSV1(LDG) (PIO_LDSV + 0x00008UL + (LDG) * 0x2000UL)
32e689cf4aSJeff Kirsher #define LDSV2(LDG) (PIO_LDSV + 0x00010UL + (LDG) * 0x2000UL)
33e689cf4aSJeff Kirsher
34e689cf4aSJeff Kirsher #define LDG_IMGMT(LDG) (PIO_LDSV + 0x00018UL + (LDG) * 0x2000UL)
35e689cf4aSJeff Kirsher #define LDG_IMGMT_ARM 0x0000000080000000ULL
36e689cf4aSJeff Kirsher #define LDG_IMGMT_TIMER 0x000000000000003fULL
37e689cf4aSJeff Kirsher
38e689cf4aSJeff Kirsher #define LD_IM0(IDX) (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
39e689cf4aSJeff Kirsher #define LD_IM0_MASK 0x0000000000000003ULL
40e689cf4aSJeff Kirsher
41e689cf4aSJeff Kirsher #define LD_IM1(IDX) (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
42e689cf4aSJeff Kirsher #define LD_IM1_MASK 0x0000000000000003ULL
43e689cf4aSJeff Kirsher
44e689cf4aSJeff Kirsher #define LDG_TIMER_RES (FZC_PIO + 0x00008UL)
45e689cf4aSJeff Kirsher #define LDG_TIMER_RES_VAL 0x00000000000fffffULL
46e689cf4aSJeff Kirsher
47e689cf4aSJeff Kirsher #define DIRTY_TID_CTL (FZC_PIO + 0x00010UL)
48e689cf4aSJeff Kirsher #define DIRTY_TID_CTL_NPTHRED 0x00000000003f0000ULL
49e689cf4aSJeff Kirsher #define DIRTY_TID_CTL_RDTHRED 0x00000000000003f0ULL
50e689cf4aSJeff Kirsher #define DIRTY_TID_CTL_DTIDCLR 0x0000000000000002ULL
51e689cf4aSJeff Kirsher #define DIRTY_TID_CTL_DTIDENAB 0x0000000000000001ULL
52e689cf4aSJeff Kirsher
53e689cf4aSJeff Kirsher #define DIRTY_TID_STAT (FZC_PIO + 0x00018UL)
54e689cf4aSJeff Kirsher #define DIRTY_TID_STAT_NPWSTAT 0x0000000000003f00ULL
55e689cf4aSJeff Kirsher #define DIRTY_TID_STAT_RDSTAT 0x000000000000003fULL
56e689cf4aSJeff Kirsher
57e689cf4aSJeff Kirsher #define RST_CTL (FZC_PIO + 0x00038UL)
58e689cf4aSJeff Kirsher #define RST_CTL_MAC_RST3 0x0000000000400000ULL
59e689cf4aSJeff Kirsher #define RST_CTL_MAC_RST2 0x0000000000200000ULL
60e689cf4aSJeff Kirsher #define RST_CTL_MAC_RST1 0x0000000000100000ULL
61e689cf4aSJeff Kirsher #define RST_CTL_MAC_RST0 0x0000000000080000ULL
62e689cf4aSJeff Kirsher #define RST_CTL_ACK_TO_EN 0x0000000000000800ULL
63e689cf4aSJeff Kirsher #define RST_CTL_ACK_TO_VAL 0x00000000000007feULL
64e689cf4aSJeff Kirsher
65e689cf4aSJeff Kirsher #define SMX_CFIG_DAT (FZC_PIO + 0x00040UL)
66e689cf4aSJeff Kirsher #define SMX_CFIG_DAT_RAS_DET 0x0000000080000000ULL
67e689cf4aSJeff Kirsher #define SMX_CFIG_DAT_RAS_INJ 0x0000000040000000ULL
68e689cf4aSJeff Kirsher #define SMX_CFIG_DAT_XACT_TO 0x000000000fffffffULL
69e689cf4aSJeff Kirsher
70e689cf4aSJeff Kirsher #define SMX_INT_STAT (FZC_PIO + 0x00048UL)
71e689cf4aSJeff Kirsher #define SMX_INT_STAT_STAT 0x00000000ffffffffULL
72e689cf4aSJeff Kirsher
73e689cf4aSJeff Kirsher #define SMX_CTL (FZC_PIO + 0x00050UL)
74e689cf4aSJeff Kirsher #define SMX_CTL_CTL 0x00000000ffffffffULL
75e689cf4aSJeff Kirsher
76e689cf4aSJeff Kirsher #define SMX_DBG_VEC (FZC_PIO + 0x00058UL)
77e689cf4aSJeff Kirsher #define SMX_DBG_VEC_VEC 0x00000000ffffffffULL
78e689cf4aSJeff Kirsher
79e689cf4aSJeff Kirsher #define PIO_DBG_SEL (FZC_PIO + 0x00060UL)
80e689cf4aSJeff Kirsher #define PIO_DBG_SEL_SEL 0x000000000000003fULL
81e689cf4aSJeff Kirsher
82e689cf4aSJeff Kirsher #define PIO_TRAIN_VEC (FZC_PIO + 0x00068UL)
83e689cf4aSJeff Kirsher #define PIO_TRAIN_VEC_VEC 0x00000000ffffffffULL
84e689cf4aSJeff Kirsher
85e689cf4aSJeff Kirsher #define PIO_ARB_CTL (FZC_PIO + 0x00070UL)
86e689cf4aSJeff Kirsher #define PIO_ARB_CTL_CTL 0x00000000ffffffffULL
87e689cf4aSJeff Kirsher
88e689cf4aSJeff Kirsher #define PIO_ARB_DBG_VEC (FZC_PIO + 0x00078UL)
89e689cf4aSJeff Kirsher #define PIO_ARB_DBG_VEC_VEC 0x00000000ffffffffULL
90e689cf4aSJeff Kirsher
91e689cf4aSJeff Kirsher #define SYS_ERR_MASK (FZC_PIO + 0x00090UL)
92e689cf4aSJeff Kirsher #define SYS_ERR_MASK_META2 0x0000000000000400ULL
93e689cf4aSJeff Kirsher #define SYS_ERR_MASK_META1 0x0000000000000200ULL
94e689cf4aSJeff Kirsher #define SYS_ERR_MASK_PEU 0x0000000000000100ULL
95e689cf4aSJeff Kirsher #define SYS_ERR_MASK_TXC 0x0000000000000080ULL
96e689cf4aSJeff Kirsher #define SYS_ERR_MASK_RDMC 0x0000000000000040ULL
97e689cf4aSJeff Kirsher #define SYS_ERR_MASK_TDMC 0x0000000000000020ULL
98e689cf4aSJeff Kirsher #define SYS_ERR_MASK_ZCP 0x0000000000000010ULL
99e689cf4aSJeff Kirsher #define SYS_ERR_MASK_FFLP 0x0000000000000008ULL
100e689cf4aSJeff Kirsher #define SYS_ERR_MASK_IPP 0x0000000000000004ULL
101e689cf4aSJeff Kirsher #define SYS_ERR_MASK_MAC 0x0000000000000002ULL
102e689cf4aSJeff Kirsher #define SYS_ERR_MASK_SMX 0x0000000000000001ULL
103e689cf4aSJeff Kirsher
104e689cf4aSJeff Kirsher #define SYS_ERR_STAT (FZC_PIO + 0x00098UL)
105e689cf4aSJeff Kirsher #define SYS_ERR_STAT_META2 0x0000000000000400ULL
106e689cf4aSJeff Kirsher #define SYS_ERR_STAT_META1 0x0000000000000200ULL
107e689cf4aSJeff Kirsher #define SYS_ERR_STAT_PEU 0x0000000000000100ULL
108e689cf4aSJeff Kirsher #define SYS_ERR_STAT_TXC 0x0000000000000080ULL
109e689cf4aSJeff Kirsher #define SYS_ERR_STAT_RDMC 0x0000000000000040ULL
110e689cf4aSJeff Kirsher #define SYS_ERR_STAT_TDMC 0x0000000000000020ULL
111e689cf4aSJeff Kirsher #define SYS_ERR_STAT_ZCP 0x0000000000000010ULL
112e689cf4aSJeff Kirsher #define SYS_ERR_STAT_FFLP 0x0000000000000008ULL
113e689cf4aSJeff Kirsher #define SYS_ERR_STAT_IPP 0x0000000000000004ULL
114e689cf4aSJeff Kirsher #define SYS_ERR_STAT_MAC 0x0000000000000002ULL
115e689cf4aSJeff Kirsher #define SYS_ERR_STAT_SMX 0x0000000000000001ULL
116e689cf4aSJeff Kirsher
117e689cf4aSJeff Kirsher #define SID(LDG) (FZC_PIO + 0x10200UL + (LDG) * 8UL)
118e689cf4aSJeff Kirsher #define SID_FUNC 0x0000000000000060ULL
119e689cf4aSJeff Kirsher #define SID_FUNC_SHIFT 5
120e689cf4aSJeff Kirsher #define SID_VECTOR 0x000000000000001fULL
121e689cf4aSJeff Kirsher #define SID_VECTOR_SHIFT 0
122e689cf4aSJeff Kirsher
123e689cf4aSJeff Kirsher #define LDG_NUM(LDN) (FZC_PIO + 0x20000UL + (LDN) * 8UL)
124e689cf4aSJeff Kirsher
125e689cf4aSJeff Kirsher #define XMAC_PORT0_OFF (FZC_MAC + 0x000000)
126e689cf4aSJeff Kirsher #define XMAC_PORT1_OFF (FZC_MAC + 0x006000)
127e689cf4aSJeff Kirsher #define BMAC_PORT2_OFF (FZC_MAC + 0x00c000)
128e689cf4aSJeff Kirsher #define BMAC_PORT3_OFF (FZC_MAC + 0x010000)
129e689cf4aSJeff Kirsher
130e689cf4aSJeff Kirsher /* XMAC registers, offset from np->mac_regs */
131e689cf4aSJeff Kirsher
132e689cf4aSJeff Kirsher #define XTXMAC_SW_RST 0x00000UL
133e689cf4aSJeff Kirsher #define XTXMAC_SW_RST_REG_RS 0x0000000000000002ULL
134e689cf4aSJeff Kirsher #define XTXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
135e689cf4aSJeff Kirsher
136e689cf4aSJeff Kirsher #define XRXMAC_SW_RST 0x00008UL
137e689cf4aSJeff Kirsher #define XRXMAC_SW_RST_REG_RS 0x0000000000000002ULL
138e689cf4aSJeff Kirsher #define XRXMAC_SW_RST_SOFT_RST 0x0000000000000001ULL
139e689cf4aSJeff Kirsher
140e689cf4aSJeff Kirsher #define XTXMAC_STATUS 0x00020UL
141e689cf4aSJeff Kirsher #define XTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
142e689cf4aSJeff Kirsher #define XTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
143e689cf4aSJeff Kirsher #define XTXMAC_STATUS_TXFIFO_XFR_ERR 0x0000000000000010ULL
144e689cf4aSJeff Kirsher #define XTXMAC_STATUS_TXMAC_OFLOW 0x0000000000000008ULL
145e689cf4aSJeff Kirsher #define XTXMAC_STATUS_MAX_PSIZE_ERR 0x0000000000000004ULL
146e689cf4aSJeff Kirsher #define XTXMAC_STATUS_TXMAC_UFLOW 0x0000000000000002ULL
147e689cf4aSJeff Kirsher #define XTXMAC_STATUS_FRAME_XMITED 0x0000000000000001ULL
148e689cf4aSJeff Kirsher
149e689cf4aSJeff Kirsher #define XRXMAC_STATUS 0x00028UL
150e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST7_CNT_EXP 0x0000000000100000ULL
151e689cf4aSJeff Kirsher #define XRXMAC_STATUS_LCL_FLT_STATUS 0x0000000000080000ULL
152e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RFLT_DET 0x0000000000040000ULL
153e689cf4aSJeff Kirsher #define XRXMAC_STATUS_LFLT_CNT_EXP 0x0000000000020000ULL
154e689cf4aSJeff Kirsher #define XRXMAC_STATUS_PHY_MDINT 0x0000000000010000ULL
155e689cf4aSJeff Kirsher #define XRXMAC_STATUS_ALIGNERR_CNT_EXP 0x0000000000010000ULL
156e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXFRAG_CNT_EXP 0x0000000000008000ULL
157e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXMULTF_CNT_EXP 0x0000000000004000ULL
158e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXBCAST_CNT_EXP 0x0000000000002000ULL
159e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST6_CNT_EXP 0x0000000000001000ULL
160e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST5_CNT_EXP 0x0000000000000800ULL
161e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST4_CNT_EXP 0x0000000000000400ULL
162e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST3_CNT_EXP 0x0000000000000200ULL
163e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST2_CNT_EXP 0x0000000000000100ULL
164e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXHIST1_CNT_EXP 0x0000000000000080ULL
165e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXOCTET_CNT_EXP 0x0000000000000040ULL
166e689cf4aSJeff Kirsher #define XRXMAC_STATUS_CVIOLERR_CNT_EXP 0x0000000000000020ULL
167e689cf4aSJeff Kirsher #define XRXMAC_STATUS_LENERR_CNT_EXP 0x0000000000000010ULL
168e689cf4aSJeff Kirsher #define XRXMAC_STATUS_CRCERR_CNT_EXP 0x0000000000000008ULL
169e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXUFLOW 0x0000000000000004ULL
170e689cf4aSJeff Kirsher #define XRXMAC_STATUS_RXOFLOW 0x0000000000000002ULL
171e689cf4aSJeff Kirsher #define XRXMAC_STATUS_FRAME_RCVD 0x0000000000000001ULL
172e689cf4aSJeff Kirsher
173e689cf4aSJeff Kirsher #define XMAC_FC_STAT 0x00030UL
174e689cf4aSJeff Kirsher #define XMAC_FC_STAT_RX_RCV_PAUSE_TIME 0x00000000ffff0000ULL
175e689cf4aSJeff Kirsher #define XMAC_FC_STAT_TX_MAC_NPAUSE 0x0000000000000004ULL
176e689cf4aSJeff Kirsher #define XMAC_FC_STAT_TX_MAC_PAUSE 0x0000000000000002ULL
177e689cf4aSJeff Kirsher #define XMAC_FC_STAT_RX_MAC_RPAUSE 0x0000000000000001ULL
178e689cf4aSJeff Kirsher
179e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK 0x00040UL
180e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_FRAME_CNT_EXP 0x0000000000000800ULL
181e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_BYTE_CNT_EXP 0x0000000000000400ULL
182e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_TXFIFO_XFR_ERR 0x0000000000000010ULL
183e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_TXMAC_OFLOW 0x0000000000000008ULL
184e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_MAX_PSIZE_ERR 0x0000000000000004ULL
185e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_TXMAC_UFLOW 0x0000000000000002ULL
186e689cf4aSJeff Kirsher #define XTXMAC_STAT_MSK_FRAME_XMITED 0x0000000000000001ULL
187e689cf4aSJeff Kirsher
188e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK 0x00048UL
189e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_LCL_FLT_STAT_MSK 0x0000000000080000ULL
190e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RFLT_DET 0x0000000000040000ULL
191e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_LFLT_CNT_EXP 0x0000000000020000ULL
192e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_PHY_MDINT 0x0000000000010000ULL
193e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXFRAG_CNT_EXP 0x0000000000008000ULL
194e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXMULTF_CNT_EXP 0x0000000000004000ULL
195e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXBCAST_CNT_EXP 0x0000000000002000ULL
196e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST6_CNT_EXP 0x0000000000001000ULL
197e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST5_CNT_EXP 0x0000000000000800ULL
198e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST4_CNT_EXP 0x0000000000000400ULL
199e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST3_CNT_EXP 0x0000000000000200ULL
200e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST2_CNT_EXP 0x0000000000000100ULL
201e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXHIST1_CNT_EXP 0x0000000000000080ULL
202e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXOCTET_CNT_EXP 0x0000000000000040ULL
203e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_CVIOLERR_CNT_EXP 0x0000000000000020ULL
204e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_LENERR_CNT_EXP 0x0000000000000010ULL
205e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_CRCERR_CNT_EXP 0x0000000000000008ULL
206e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXUFLOW_CNT_EXP 0x0000000000000004ULL
207e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_RXOFLOW_CNT_EXP 0x0000000000000002ULL
208e689cf4aSJeff Kirsher #define XRXMAC_STAT_MSK_FRAME_RCVD 0x0000000000000001ULL
209e689cf4aSJeff Kirsher
210e689cf4aSJeff Kirsher #define XMAC_FC_MSK 0x00050UL
211e689cf4aSJeff Kirsher #define XMAC_FC_MSK_TX_MAC_NPAUSE 0x0000000000000004ULL
212e689cf4aSJeff Kirsher #define XMAC_FC_MSK_TX_MAC_PAUSE 0x0000000000000002ULL
213e689cf4aSJeff Kirsher #define XMAC_FC_MSK_RX_MAC_RPAUSE 0x0000000000000001ULL
214e689cf4aSJeff Kirsher
215e689cf4aSJeff Kirsher #define XMAC_CONFIG 0x00060UL
216e689cf4aSJeff Kirsher #define XMAC_CONFIG_SEL_CLK_25MHZ 0x0000000080000000ULL
217e689cf4aSJeff Kirsher #define XMAC_CONFIG_1G_PCS_BYPASS 0x0000000040000000ULL
218e689cf4aSJeff Kirsher #define XMAC_CONFIG_10G_XPCS_BYPASS 0x0000000020000000ULL
219e689cf4aSJeff Kirsher #define XMAC_CONFIG_MODE_MASK 0x0000000018000000ULL
220e689cf4aSJeff Kirsher #define XMAC_CONFIG_MODE_XGMII 0x0000000000000000ULL
221e689cf4aSJeff Kirsher #define XMAC_CONFIG_MODE_GMII 0x0000000008000000ULL
222e689cf4aSJeff Kirsher #define XMAC_CONFIG_MODE_MII 0x0000000010000000ULL
223e689cf4aSJeff Kirsher #define XMAC_CONFIG_LFS_DISABLE 0x0000000004000000ULL
224e689cf4aSJeff Kirsher #define XMAC_CONFIG_LOOPBACK 0x0000000002000000ULL
225e689cf4aSJeff Kirsher #define XMAC_CONFIG_TX_OUTPUT_EN 0x0000000001000000ULL
226e689cf4aSJeff Kirsher #define XMAC_CONFIG_SEL_POR_CLK_SRC 0x0000000000800000ULL
227e689cf4aSJeff Kirsher #define XMAC_CONFIG_LED_POLARITY 0x0000000000400000ULL
228e689cf4aSJeff Kirsher #define XMAC_CONFIG_FORCE_LED_ON 0x0000000000200000ULL
229e689cf4aSJeff Kirsher #define XMAC_CONFIG_PASS_FLOW_CTRL 0x0000000000100000ULL
230e689cf4aSJeff Kirsher #define XMAC_CONFIG_RCV_PAUSE_ENABLE 0x0000000000080000ULL
231e689cf4aSJeff Kirsher #define XMAC_CONFIG_MAC2IPP_PKT_CNT_EN 0x0000000000040000ULL
232e689cf4aSJeff Kirsher #define XMAC_CONFIG_STRIP_CRC 0x0000000000020000ULL
233e689cf4aSJeff Kirsher #define XMAC_CONFIG_ADDR_FILTER_EN 0x0000000000010000ULL
234e689cf4aSJeff Kirsher #define XMAC_CONFIG_HASH_FILTER_EN 0x0000000000008000ULL
235e689cf4aSJeff Kirsher #define XMAC_CONFIG_RX_CODEV_CHK_DIS 0x0000000000004000ULL
236e689cf4aSJeff Kirsher #define XMAC_CONFIG_RESERVED_MULTICAST 0x0000000000002000ULL
237e689cf4aSJeff Kirsher #define XMAC_CONFIG_RX_CRC_CHK_DIS 0x0000000000001000ULL
238e689cf4aSJeff Kirsher #define XMAC_CONFIG_ERR_CHK_DIS 0x0000000000000800ULL
239e689cf4aSJeff Kirsher #define XMAC_CONFIG_PROMISC_GROUP 0x0000000000000400ULL
240e689cf4aSJeff Kirsher #define XMAC_CONFIG_PROMISCUOUS 0x0000000000000200ULL
241e689cf4aSJeff Kirsher #define XMAC_CONFIG_RX_MAC_ENABLE 0x0000000000000100ULL
242e689cf4aSJeff Kirsher #define XMAC_CONFIG_WARNING_MSG_EN 0x0000000000000080ULL
243e689cf4aSJeff Kirsher #define XMAC_CONFIG_ALWAYS_NO_CRC 0x0000000000000008ULL
244e689cf4aSJeff Kirsher #define XMAC_CONFIG_VAR_MIN_IPG_EN 0x0000000000000004ULL
245e689cf4aSJeff Kirsher #define XMAC_CONFIG_STRETCH_MODE 0x0000000000000002ULL
246e689cf4aSJeff Kirsher #define XMAC_CONFIG_TX_ENABLE 0x0000000000000001ULL
247e689cf4aSJeff Kirsher
248e689cf4aSJeff Kirsher #define XMAC_IPG 0x00080UL
249e689cf4aSJeff Kirsher #define XMAC_IPG_STRETCH_CONST 0x0000000000e00000ULL
250e689cf4aSJeff Kirsher #define XMAC_IPG_STRETCH_CONST_SHIFT 21
251e689cf4aSJeff Kirsher #define XMAC_IPG_STRETCH_RATIO 0x00000000001f0000ULL
252e689cf4aSJeff Kirsher #define XMAC_IPG_STRETCH_RATIO_SHIFT 16
253e689cf4aSJeff Kirsher #define XMAC_IPG_IPG_MII_GMII 0x000000000000ff00ULL
254e689cf4aSJeff Kirsher #define XMAC_IPG_IPG_MII_GMII_SHIFT 8
255e689cf4aSJeff Kirsher #define XMAC_IPG_IPG_XGMII 0x0000000000000007ULL
256e689cf4aSJeff Kirsher #define XMAC_IPG_IPG_XGMII_SHIFT 0
257e689cf4aSJeff Kirsher
258e689cf4aSJeff Kirsher #define IPG_12_15_XGMII 3
259e689cf4aSJeff Kirsher #define IPG_16_19_XGMII 4
260e689cf4aSJeff Kirsher #define IPG_20_23_XGMII 5
261e689cf4aSJeff Kirsher #define IPG_12_MII_GMII 10
262e689cf4aSJeff Kirsher #define IPG_13_MII_GMII 11
263e689cf4aSJeff Kirsher #define IPG_14_MII_GMII 12
264e689cf4aSJeff Kirsher #define IPG_15_MII_GMII 13
265e689cf4aSJeff Kirsher #define IPG_16_MII_GMII 14
266e689cf4aSJeff Kirsher
267e689cf4aSJeff Kirsher #define XMAC_MIN 0x00088UL
268e689cf4aSJeff Kirsher #define XMAC_MIN_RX_MIN_PKT_SIZE 0x000000003ff00000ULL
269e689cf4aSJeff Kirsher #define XMAC_MIN_RX_MIN_PKT_SIZE_SHFT 20
270e689cf4aSJeff Kirsher #define XMAC_MIN_SLOT_TIME 0x000000000003fc00ULL
271e689cf4aSJeff Kirsher #define XMAC_MIN_SLOT_TIME_SHFT 10
272e689cf4aSJeff Kirsher #define XMAC_MIN_TX_MIN_PKT_SIZE 0x00000000000003ffULL
273e689cf4aSJeff Kirsher #define XMAC_MIN_TX_MIN_PKT_SIZE_SHFT 0
274e689cf4aSJeff Kirsher
275e689cf4aSJeff Kirsher #define XMAC_MAX 0x00090UL
276e689cf4aSJeff Kirsher #define XMAC_MAX_FRAME_SIZE 0x0000000000003fffULL
277e689cf4aSJeff Kirsher #define XMAC_MAX_FRAME_SIZE_SHFT 0
278e689cf4aSJeff Kirsher
279e689cf4aSJeff Kirsher #define XMAC_ADDR0 0x000a0UL
280e689cf4aSJeff Kirsher #define XMAC_ADDR0_ADDR0 0x000000000000ffffULL
281e689cf4aSJeff Kirsher
282e689cf4aSJeff Kirsher #define XMAC_ADDR1 0x000a8UL
283e689cf4aSJeff Kirsher #define XMAC_ADDR1_ADDR1 0x000000000000ffffULL
284e689cf4aSJeff Kirsher
285e689cf4aSJeff Kirsher #define XMAC_ADDR2 0x000b0UL
286e689cf4aSJeff Kirsher #define XMAC_ADDR2_ADDR2 0x000000000000ffffULL
287e689cf4aSJeff Kirsher
288e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN 0x00208UL
289e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
290e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
291e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
292e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
293e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
294e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
295e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
296e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
297e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
298e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
299e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
300e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
301e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
302e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
303e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
304e689cf4aSJeff Kirsher #define XMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
305e689cf4aSJeff Kirsher
306e689cf4aSJeff Kirsher #define XMAC_NUM_ALT_ADDR 16
307e689cf4aSJeff Kirsher
308e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR0(NUM) (0x00218UL + (NUM)*0x18UL)
309e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
310e689cf4aSJeff Kirsher
311e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR1(NUM) (0x00220UL + (NUM)*0x18UL)
312e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
313e689cf4aSJeff Kirsher
314e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR2(NUM) (0x00228UL + (NUM)*0x18UL)
315e689cf4aSJeff Kirsher #define XMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
316e689cf4aSJeff Kirsher
317e689cf4aSJeff Kirsher #define XMAC_ADD_FILT0 0x00818UL
318e689cf4aSJeff Kirsher #define XMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
319e689cf4aSJeff Kirsher
320e689cf4aSJeff Kirsher #define XMAC_ADD_FILT1 0x00820UL
321e689cf4aSJeff Kirsher #define XMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
322e689cf4aSJeff Kirsher
323e689cf4aSJeff Kirsher #define XMAC_ADD_FILT2 0x00828UL
324e689cf4aSJeff Kirsher #define XMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
325e689cf4aSJeff Kirsher
326e689cf4aSJeff Kirsher #define XMAC_ADD_FILT12_MASK 0x00830UL
327e689cf4aSJeff Kirsher #define XMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
328e689cf4aSJeff Kirsher
329e689cf4aSJeff Kirsher #define XMAC_ADD_FILT00_MASK 0x00838UL
330e689cf4aSJeff Kirsher #define XMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
331e689cf4aSJeff Kirsher
332e689cf4aSJeff Kirsher #define XMAC_HASH_TBL(NUM) (0x00840UL + (NUM) * 0x8UL)
333e689cf4aSJeff Kirsher #define XMAC_HASH_TBL_VAL 0x000000000000ffffULL
334e689cf4aSJeff Kirsher
335e689cf4aSJeff Kirsher #define XMAC_NUM_HOST_INFO 20
336e689cf4aSJeff Kirsher
337e689cf4aSJeff Kirsher #define XMAC_HOST_INFO(NUM) (0x00900UL + (NUM) * 0x8UL)
338e689cf4aSJeff Kirsher
339e689cf4aSJeff Kirsher #define XMAC_PA_DATA0 0x00b80UL
340e689cf4aSJeff Kirsher #define XMAC_PA_DATA0_VAL 0x00000000ffffffffULL
341e689cf4aSJeff Kirsher
342e689cf4aSJeff Kirsher #define XMAC_PA_DATA1 0x00b88UL
343e689cf4aSJeff Kirsher #define XMAC_PA_DATA1_VAL 0x00000000ffffffffULL
344e689cf4aSJeff Kirsher
345e689cf4aSJeff Kirsher #define XMAC_DEBUG_SEL 0x00b90UL
346e689cf4aSJeff Kirsher #define XMAC_DEBUG_SEL_XMAC 0x0000000000000078ULL
347e689cf4aSJeff Kirsher #define XMAC_DEBUG_SEL_MAC 0x0000000000000007ULL
348e689cf4aSJeff Kirsher
349e689cf4aSJeff Kirsher #define XMAC_TRAIN_VEC 0x00b98UL
350e689cf4aSJeff Kirsher #define XMAC_TRAIN_VEC_VAL 0x00000000ffffffffULL
351e689cf4aSJeff Kirsher
352e689cf4aSJeff Kirsher #define RXMAC_BT_CNT 0x00100UL
353e689cf4aSJeff Kirsher #define RXMAC_BT_CNT_COUNT 0x00000000ffffffffULL
354e689cf4aSJeff Kirsher
355e689cf4aSJeff Kirsher #define RXMAC_BC_FRM_CNT 0x00108UL
356e689cf4aSJeff Kirsher #define RXMAC_BC_FRM_CNT_COUNT 0x00000000001fffffULL
357e689cf4aSJeff Kirsher
358e689cf4aSJeff Kirsher #define RXMAC_MC_FRM_CNT 0x00110UL
359e689cf4aSJeff Kirsher #define RXMAC_MC_FRM_CNT_COUNT 0x00000000001fffffULL
360e689cf4aSJeff Kirsher
361e689cf4aSJeff Kirsher #define RXMAC_FRAG_CNT 0x00118UL
362e689cf4aSJeff Kirsher #define RXMAC_FRAG_CNT_COUNT 0x00000000001fffffULL
363e689cf4aSJeff Kirsher
364e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT1 0x00120UL
365e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT1_COUNT 0x00000000001fffffULL
366e689cf4aSJeff Kirsher
367e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT2 0x00128UL
368e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT2_COUNT 0x00000000001fffffULL
369e689cf4aSJeff Kirsher
370e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT3 0x00130UL
371e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT3_COUNT 0x00000000000fffffULL
372e689cf4aSJeff Kirsher
373e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT4 0x00138UL
374e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT4_COUNT 0x000000000007ffffULL
375e689cf4aSJeff Kirsher
376e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT5 0x00140UL
377e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT5_COUNT 0x000000000003ffffULL
378e689cf4aSJeff Kirsher
379e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT6 0x00148UL
380e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT6_COUNT 0x000000000000ffffULL
381e689cf4aSJeff Kirsher
382e689cf4aSJeff Kirsher #define RXMAC_MPSZER_CNT 0x00150UL
383e689cf4aSJeff Kirsher #define RXMAC_MPSZER_CNT_COUNT 0x00000000000000ffULL
384e689cf4aSJeff Kirsher
385e689cf4aSJeff Kirsher #define RXMAC_CRC_ER_CNT 0x00158UL
386e689cf4aSJeff Kirsher #define RXMAC_CRC_ER_CNT_COUNT 0x00000000000000ffULL
387e689cf4aSJeff Kirsher
388e689cf4aSJeff Kirsher #define RXMAC_CD_VIO_CNT 0x00160UL
389e689cf4aSJeff Kirsher #define RXMAC_CD_VIO_CNT_COUNT 0x00000000000000ffULL
390e689cf4aSJeff Kirsher
391e689cf4aSJeff Kirsher #define RXMAC_ALIGN_ERR_CNT 0x00168UL
392e689cf4aSJeff Kirsher #define RXMAC_ALIGN_ERR_CNT_COUNT 0x00000000000000ffULL
393e689cf4aSJeff Kirsher
394e689cf4aSJeff Kirsher #define TXMAC_FRM_CNT 0x00170UL
395e689cf4aSJeff Kirsher #define TXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
396e689cf4aSJeff Kirsher
397e689cf4aSJeff Kirsher #define TXMAC_BYTE_CNT 0x00178UL
398e689cf4aSJeff Kirsher #define TXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
399e689cf4aSJeff Kirsher
400e689cf4aSJeff Kirsher #define LINK_FAULT_CNT 0x00180UL
401e689cf4aSJeff Kirsher #define LINK_FAULT_CNT_COUNT 0x00000000000000ffULL
402e689cf4aSJeff Kirsher
403e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT7 0x00188UL
404e689cf4aSJeff Kirsher #define RXMAC_HIST_CNT7_COUNT 0x0000000007ffffffULL
405e689cf4aSJeff Kirsher
406e689cf4aSJeff Kirsher #define XMAC_SM_REG 0x001a8UL
407e689cf4aSJeff Kirsher #define XMAC_SM_REG_STATE 0x00000000ffffffffULL
408e689cf4aSJeff Kirsher
409e689cf4aSJeff Kirsher #define XMAC_INTER1 0x001b0UL
410e689cf4aSJeff Kirsher #define XMAC_INTERN1_SIGNALS1 0x00000000ffffffffULL
411e689cf4aSJeff Kirsher
412e689cf4aSJeff Kirsher #define XMAC_INTER2 0x001b8UL
413e689cf4aSJeff Kirsher #define XMAC_INTERN2_SIGNALS2 0x00000000ffffffffULL
414e689cf4aSJeff Kirsher
415e689cf4aSJeff Kirsher /* BMAC registers, offset from np->mac_regs */
416e689cf4aSJeff Kirsher
417e689cf4aSJeff Kirsher #define BTXMAC_SW_RST 0x00000UL
418e689cf4aSJeff Kirsher #define BTXMAC_SW_RST_RESET 0x0000000000000001ULL
419e689cf4aSJeff Kirsher
420e689cf4aSJeff Kirsher #define BRXMAC_SW_RST 0x00008UL
421e689cf4aSJeff Kirsher #define BRXMAC_SW_RST_RESET 0x0000000000000001ULL
422e689cf4aSJeff Kirsher
423e689cf4aSJeff Kirsher #define BMAC_SEND_PAUSE 0x00010UL
424e689cf4aSJeff Kirsher #define BMAC_SEND_PAUSE_SEND 0x0000000000010000ULL
425e689cf4aSJeff Kirsher #define BMAC_SEND_PAUSE_TIME 0x000000000000ffffULL
426e689cf4aSJeff Kirsher
427e689cf4aSJeff Kirsher #define BTXMAC_STATUS 0x00020UL
428e689cf4aSJeff Kirsher #define BTXMAC_STATUS_XMIT 0x0000000000000001ULL
429e689cf4aSJeff Kirsher #define BTXMAC_STATUS_UNDERRUN 0x0000000000000002ULL
430e689cf4aSJeff Kirsher #define BTXMAC_STATUS_MAX_PKT_ERR 0x0000000000000004ULL
431e689cf4aSJeff Kirsher #define BTXMAC_STATUS_BYTE_CNT_EXP 0x0000000000000400ULL
432e689cf4aSJeff Kirsher #define BTXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000800ULL
433e689cf4aSJeff Kirsher
434e689cf4aSJeff Kirsher #define BRXMAC_STATUS 0x00028UL
435e689cf4aSJeff Kirsher #define BRXMAC_STATUS_RX_PKT 0x0000000000000001ULL
436e689cf4aSJeff Kirsher #define BRXMAC_STATUS_OVERFLOW 0x0000000000000002ULL
437e689cf4aSJeff Kirsher #define BRXMAC_STATUS_FRAME_CNT_EXP 0x0000000000000004ULL
438e689cf4aSJeff Kirsher #define BRXMAC_STATUS_ALIGN_ERR_EXP 0x0000000000000008ULL
439e689cf4aSJeff Kirsher #define BRXMAC_STATUS_CRC_ERR_EXP 0x0000000000000010ULL
440e689cf4aSJeff Kirsher #define BRXMAC_STATUS_LEN_ERR_EXP 0x0000000000000020ULL
441e689cf4aSJeff Kirsher
442e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS 0x00030UL
443e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_PAUSE_RECV 0x0000000000000001ULL
444e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_PAUSE 0x0000000000000002ULL
445e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_NOPAUSE 0x0000000000000004ULL
446e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_TIME 0x00000000ffff0000ULL
447e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_TIME_SHIFT 16
448e689cf4aSJeff Kirsher
449e689cf4aSJeff Kirsher #define BTXMAC_STATUS_MASK 0x00040UL
450e689cf4aSJeff Kirsher #define BRXMAC_STATUS_MASK 0x00048UL
451e689cf4aSJeff Kirsher #define BMAC_CTRL_STATUS_MASK 0x00050UL
452e689cf4aSJeff Kirsher
453e689cf4aSJeff Kirsher #define BTXMAC_CONFIG 0x00060UL
454e689cf4aSJeff Kirsher #define BTXMAC_CONFIG_ENABLE 0x0000000000000001ULL
455e689cf4aSJeff Kirsher #define BTXMAC_CONFIG_FCS_DISABLE 0x0000000000000002ULL
456e689cf4aSJeff Kirsher
457e689cf4aSJeff Kirsher #define BRXMAC_CONFIG 0x00068UL
458e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_DISCARD_DIS 0x0000000000000080ULL
459e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_ADDR_FILT_EN 0x0000000000000040ULL
460e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_HASH_FILT_EN 0x0000000000000020ULL
461e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_PROMISC_GRP 0x0000000000000010ULL
462e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_PROMISC 0x0000000000000008ULL
463e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_STRIP_FCS 0x0000000000000004ULL
464e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_STRIP_PAD 0x0000000000000002ULL
465e689cf4aSJeff Kirsher #define BRXMAC_CONFIG_ENABLE 0x0000000000000001ULL
466e689cf4aSJeff Kirsher
467e689cf4aSJeff Kirsher #define BMAC_CTRL_CONFIG 0x00070UL
468e689cf4aSJeff Kirsher #define BMAC_CTRL_CONFIG_TX_PAUSE_EN 0x0000000000000001ULL
469e689cf4aSJeff Kirsher #define BMAC_CTRL_CONFIG_RX_PAUSE_EN 0x0000000000000002ULL
470e689cf4aSJeff Kirsher #define BMAC_CTRL_CONFIG_PASS_CTRL 0x0000000000000004ULL
471e689cf4aSJeff Kirsher
472e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG 0x00078UL
473e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_TX_OUTPUT_EN 0x0000000000000001ULL
474e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_MII_LOOPBACK 0x0000000000000002ULL
475e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_GMII_MODE 0x0000000000000008ULL
476e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_LINK_LED 0x0000000000000020ULL
477e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_LED_POLARITY 0x0000000000000040ULL
478e689cf4aSJeff Kirsher #define BMAC_XIF_CONFIG_25MHZ_CLOCK 0x0000000000000080ULL
479e689cf4aSJeff Kirsher
480e689cf4aSJeff Kirsher #define BMAC_MIN_FRAME 0x000a0UL
481e689cf4aSJeff Kirsher #define BMAC_MIN_FRAME_VAL 0x00000000000003ffULL
482e689cf4aSJeff Kirsher
483e689cf4aSJeff Kirsher #define BMAC_MAX_FRAME 0x000a8UL
484e689cf4aSJeff Kirsher #define BMAC_MAX_FRAME_MAX_BURST 0x000000003fff0000ULL
485e689cf4aSJeff Kirsher #define BMAC_MAX_FRAME_MAX_BURST_SHIFT 16
486e689cf4aSJeff Kirsher #define BMAC_MAX_FRAME_MAX_FRAME 0x0000000000003fffULL
487e689cf4aSJeff Kirsher #define BMAC_MAX_FRAME_MAX_FRAME_SHIFT 0
488e689cf4aSJeff Kirsher
489e689cf4aSJeff Kirsher #define BMAC_PREAMBLE_SIZE 0x000b0UL
490e689cf4aSJeff Kirsher #define BMAC_PREAMBLE_SIZE_VAL 0x00000000000003ffULL
491e689cf4aSJeff Kirsher
492e689cf4aSJeff Kirsher #define BMAC_CTRL_TYPE 0x000c8UL
493e689cf4aSJeff Kirsher
494e689cf4aSJeff Kirsher #define BMAC_ADDR0 0x00100UL
495e689cf4aSJeff Kirsher #define BMAC_ADDR0_ADDR0 0x000000000000ffffULL
496e689cf4aSJeff Kirsher
497e689cf4aSJeff Kirsher #define BMAC_ADDR1 0x00108UL
498e689cf4aSJeff Kirsher #define BMAC_ADDR1_ADDR1 0x000000000000ffffULL
499e689cf4aSJeff Kirsher
500e689cf4aSJeff Kirsher #define BMAC_ADDR2 0x00110UL
501e689cf4aSJeff Kirsher #define BMAC_ADDR2_ADDR2 0x000000000000ffffULL
502e689cf4aSJeff Kirsher
503e689cf4aSJeff Kirsher #define BMAC_NUM_ALT_ADDR 6
504e689cf4aSJeff Kirsher
505e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR0(NUM) (0x00118UL + (NUM)*0x18UL)
506e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
507e689cf4aSJeff Kirsher
508e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR1(NUM) (0x00120UL + (NUM)*0x18UL)
509e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR1_ADDR1 0x000000000000ffffULL
510e689cf4aSJeff Kirsher
511e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR2(NUM) (0x00128UL + (NUM)*0x18UL)
512e689cf4aSJeff Kirsher #define BMAC_ALT_ADDR2_ADDR2 0x000000000000ffffULL
513e689cf4aSJeff Kirsher
514e689cf4aSJeff Kirsher #define BMAC_FC_ADDR0 0x00268UL
515e689cf4aSJeff Kirsher #define BMAC_FC_ADDR0_ADDR0 0x000000000000ffffULL
516e689cf4aSJeff Kirsher
517e689cf4aSJeff Kirsher #define BMAC_FC_ADDR1 0x00270UL
518e689cf4aSJeff Kirsher #define BMAC_FC_ADDR1_ADDR1 0x000000000000ffffULL
519e689cf4aSJeff Kirsher
520e689cf4aSJeff Kirsher #define BMAC_FC_ADDR2 0x00278UL
521e689cf4aSJeff Kirsher #define BMAC_FC_ADDR2_ADDR2 0x000000000000ffffULL
522e689cf4aSJeff Kirsher
523e689cf4aSJeff Kirsher #define BMAC_ADD_FILT0 0x00298UL
524e689cf4aSJeff Kirsher #define BMAC_ADD_FILT0_FILT0 0x000000000000ffffULL
525e689cf4aSJeff Kirsher
526e689cf4aSJeff Kirsher #define BMAC_ADD_FILT1 0x002a0UL
527e689cf4aSJeff Kirsher #define BMAC_ADD_FILT1_FILT1 0x000000000000ffffULL
528e689cf4aSJeff Kirsher
529e689cf4aSJeff Kirsher #define BMAC_ADD_FILT2 0x002a8UL
530e689cf4aSJeff Kirsher #define BMAC_ADD_FILT2_FILT2 0x000000000000ffffULL
531e689cf4aSJeff Kirsher
532e689cf4aSJeff Kirsher #define BMAC_ADD_FILT12_MASK 0x002b0UL
533e689cf4aSJeff Kirsher #define BMAC_ADD_FILT12_MASK_VAL 0x00000000000000ffULL
534e689cf4aSJeff Kirsher
535e689cf4aSJeff Kirsher #define BMAC_ADD_FILT00_MASK 0x002b8UL
536e689cf4aSJeff Kirsher #define BMAC_ADD_FILT00_MASK_VAL 0x000000000000ffffULL
537e689cf4aSJeff Kirsher
538e689cf4aSJeff Kirsher #define BMAC_HASH_TBL(NUM) (0x002c0UL + (NUM) * 0x8UL)
539e689cf4aSJeff Kirsher #define BMAC_HASH_TBL_VAL 0x000000000000ffffULL
540e689cf4aSJeff Kirsher
541e689cf4aSJeff Kirsher #define BRXMAC_FRAME_CNT 0x00370
542e689cf4aSJeff Kirsher #define BRXMAC_FRAME_CNT_COUNT 0x000000000000ffffULL
543e689cf4aSJeff Kirsher
544e689cf4aSJeff Kirsher #define BRXMAC_MAX_LEN_ERR_CNT 0x00378
545e689cf4aSJeff Kirsher
546e689cf4aSJeff Kirsher #define BRXMAC_ALIGN_ERR_CNT 0x00380
547e689cf4aSJeff Kirsher #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
548e689cf4aSJeff Kirsher
549e689cf4aSJeff Kirsher #define BRXMAC_CRC_ERR_CNT 0x00388
550e689cf4aSJeff Kirsher #define BRXMAC_ALIGN_ERR_CNT_COUNT 0x000000000000ffffULL
551e689cf4aSJeff Kirsher
552e689cf4aSJeff Kirsher #define BRXMAC_CODE_VIOL_ERR_CNT 0x00390
553e689cf4aSJeff Kirsher #define BRXMAC_CODE_VIOL_ERR_CNT_COUNT 0x000000000000ffffULL
554e689cf4aSJeff Kirsher
555e689cf4aSJeff Kirsher #define BMAC_STATE_MACHINE 0x003a0
556e689cf4aSJeff Kirsher
557e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN 0x003f8UL
558e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN15 0x0000000000008000ULL
559e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN14 0x0000000000004000ULL
560e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN13 0x0000000000002000ULL
561e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN12 0x0000000000001000ULL
562e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN11 0x0000000000000800ULL
563e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN10 0x0000000000000400ULL
564e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN9 0x0000000000000200ULL
565e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN8 0x0000000000000100ULL
566e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN7 0x0000000000000080ULL
567e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN6 0x0000000000000040ULL
568e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN5 0x0000000000000020ULL
569e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN4 0x0000000000000010ULL
570e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN3 0x0000000000000008ULL
571e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN2 0x0000000000000004ULL
572e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN1 0x0000000000000002ULL
573e689cf4aSJeff Kirsher #define BMAC_ADDR_CMPEN_EN0 0x0000000000000001ULL
574e689cf4aSJeff Kirsher
575e689cf4aSJeff Kirsher #define BMAC_NUM_HOST_INFO 9
576e689cf4aSJeff Kirsher
577e689cf4aSJeff Kirsher #define BMAC_HOST_INFO(NUM) (0x00400UL + (NUM) * 0x8UL)
578e689cf4aSJeff Kirsher
579e689cf4aSJeff Kirsher #define BTXMAC_BYTE_CNT 0x00448UL
580e689cf4aSJeff Kirsher #define BTXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
581e689cf4aSJeff Kirsher
582e689cf4aSJeff Kirsher #define BTXMAC_FRM_CNT 0x00450UL
583e689cf4aSJeff Kirsher #define BTXMAC_FRM_CNT_COUNT 0x00000000ffffffffULL
584e689cf4aSJeff Kirsher
585e689cf4aSJeff Kirsher #define BRXMAC_BYTE_CNT 0x00458UL
586e689cf4aSJeff Kirsher #define BRXMAC_BYTE_CNT_COUNT 0x00000000ffffffffULL
587e689cf4aSJeff Kirsher
588e689cf4aSJeff Kirsher #define HOST_INFO_MPR 0x0000000000000100ULL
589e689cf4aSJeff Kirsher #define HOST_INFO_MACRDCTBLN 0x0000000000000007ULL
590e689cf4aSJeff Kirsher
591e689cf4aSJeff Kirsher /* XPCS registers, offset from np->regs + np->xpcs_off */
592e689cf4aSJeff Kirsher
593e689cf4aSJeff Kirsher #define XPCS_CONTROL1 (FZC_MAC + 0x00000UL)
594e689cf4aSJeff Kirsher #define XPCS_CONTROL1_RESET 0x0000000000008000ULL
595e689cf4aSJeff Kirsher #define XPCS_CONTROL1_LOOPBACK 0x0000000000004000ULL
596e689cf4aSJeff Kirsher #define XPCS_CONTROL1_SPEED_SELECT3 0x0000000000002000ULL
597e689cf4aSJeff Kirsher #define XPCS_CONTROL1_CSR_LOW_PWR 0x0000000000000800ULL
598e689cf4aSJeff Kirsher #define XPCS_CONTROL1_CSR_SPEED1 0x0000000000000040ULL
599e689cf4aSJeff Kirsher #define XPCS_CONTROL1_CSR_SPEED0 0x000000000000003cULL
600e689cf4aSJeff Kirsher
601e689cf4aSJeff Kirsher #define XPCS_STATUS1 (FZC_MAC + 0x00008UL)
602e689cf4aSJeff Kirsher #define XPCS_STATUS1_CSR_FAULT 0x0000000000000080ULL
603e689cf4aSJeff Kirsher #define XPCS_STATUS1_CSR_RXLNK_STAT 0x0000000000000004ULL
604e689cf4aSJeff Kirsher #define XPCS_STATUS1_CSR_LPWR_ABLE 0x0000000000000002ULL
605e689cf4aSJeff Kirsher
606e689cf4aSJeff Kirsher #define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL)
607e689cf4aSJeff Kirsher #define XPCS_DEVICE_IDENTIFIER_VAL 0x00000000ffffffffULL
608e689cf4aSJeff Kirsher
609e689cf4aSJeff Kirsher #define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL)
610e689cf4aSJeff Kirsher #define XPCS_SPEED_ABILITY_10GIG 0x0000000000000001ULL
611e689cf4aSJeff Kirsher
612e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL)
613e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_CSR_VEND2 0x0000000080000000ULL
614e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_CSR_VEND1 0x0000000040000000ULL
615e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_DTE_XS 0x0000000000000020ULL
616e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_PHY_XS 0x0000000000000010ULL
617e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_PCS 0x0000000000000008ULL
618e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_WIS 0x0000000000000004ULL
619e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_PMD_PMA 0x0000000000000002ULL
620e689cf4aSJeff Kirsher #define XPCS_DEV_IN_PKG_CLS22 0x0000000000000001ULL
621e689cf4aSJeff Kirsher
622e689cf4aSJeff Kirsher #define XPCS_CONTROL2 (FZC_MAC + 0x00028UL)
623e689cf4aSJeff Kirsher #define XPCS_CONTROL2_CSR_PSC_SEL 0x0000000000000003ULL
624e689cf4aSJeff Kirsher
625e689cf4aSJeff Kirsher #define XPCS_STATUS2 (FZC_MAC + 0x00030UL)
626e689cf4aSJeff Kirsher #define XPCS_STATUS2_CSR_DEV_PRES 0x000000000000c000ULL
627e689cf4aSJeff Kirsher #define XPCS_STATUS2_CSR_TX_FAULT 0x0000000000000800ULL
628e689cf4aSJeff Kirsher #define XPCS_STATUS2_CSR_RCV_FAULT 0x0000000000000400ULL
629e689cf4aSJeff Kirsher #define XPCS_STATUS2_TEN_GBASE_W 0x0000000000000004ULL
630e689cf4aSJeff Kirsher #define XPCS_STATUS2_TEN_GBASE_X 0x0000000000000002ULL
631e689cf4aSJeff Kirsher #define XPCS_STATUS2_TEN_GBASE_R 0x0000000000000001ULL
632e689cf4aSJeff Kirsher
633e689cf4aSJeff Kirsher #define XPCS_PKG_ID (FZC_MAC + 0x00038UL)
634e689cf4aSJeff Kirsher #define XPCS_PKG_ID_VAL 0x00000000ffffffffULL
635e689cf4aSJeff Kirsher
636e689cf4aSJeff Kirsher #define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
637e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_LANE_ALIGN 0x0000000000001000ULL
638e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_PATTEST_CAP 0x0000000000000800ULL
639e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_LANE3_SYNC 0x0000000000000008ULL
640e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_LANE2_SYNC 0x0000000000000004ULL
641e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_LANE1_SYNC 0x0000000000000002ULL
642e689cf4aSJeff Kirsher #define XPCS_STATUS_CSR_LANE0_SYNC 0x0000000000000001ULL
643e689cf4aSJeff Kirsher
644e689cf4aSJeff Kirsher #define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL)
645e689cf4aSJeff Kirsher #define XPCS_TEST_CONTROL_TXTST_EN 0x0000000000000004ULL
646e689cf4aSJeff Kirsher #define XPCS_TEST_CONTROL_TPAT_SEL 0x0000000000000003ULL
647e689cf4aSJeff Kirsher
648e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL)
649e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1_DBG_IOTST 0x0000000000000080ULL
650e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1_DBG_SEL 0x0000000000000078ULL
651e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1_BYPASS_DET 0x0000000000000004ULL
652e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1_TXBUF_EN 0x0000000000000002ULL
653e689cf4aSJeff Kirsher #define XPCS_CFG_VENDOR1_XPCS_EN 0x0000000000000001ULL
654e689cf4aSJeff Kirsher
655e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL)
656e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_SSM_LANE3 0x0000000001e00000ULL
657e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_SSM_LANE2 0x00000000001e0000ULL
658e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_SSM_LANE1 0x000000000001e000ULL
659e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_SSM_LANE0 0x0000000000001e00ULL
660e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_EBUF_SM 0x00000000000001feULL
661e689cf4aSJeff Kirsher #define XPCS_DIAG_VENDOR2_RCV_SM 0x0000000000000001ULL
662e689cf4aSJeff Kirsher
663e689cf4aSJeff Kirsher #define XPCS_MASK1 (FZC_MAC + 0x00060UL)
664e689cf4aSJeff Kirsher #define XPCS_MASK1_FAULT_MASK 0x0000000000000080ULL
665e689cf4aSJeff Kirsher #define XPCS_MASK1_RXALIGN_STAT_MSK 0x0000000000000004ULL
666e689cf4aSJeff Kirsher
667e689cf4aSJeff Kirsher #define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL)
668e689cf4aSJeff Kirsher #define XPCS_PKT_COUNT_TX 0x00000000ffff0000ULL
669e689cf4aSJeff Kirsher #define XPCS_PKT_COUNT_RX 0x000000000000ffffULL
670e689cf4aSJeff Kirsher
671e689cf4aSJeff Kirsher #define XPCS_TX_SM (FZC_MAC + 0x00070UL)
672e689cf4aSJeff Kirsher #define XPCS_TX_SM_VAL 0x000000000000000fULL
673e689cf4aSJeff Kirsher
674e689cf4aSJeff Kirsher #define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL)
675e689cf4aSJeff Kirsher #define XPCS_DESKEW_ERR_CNT_VAL 0x00000000000000ffULL
676e689cf4aSJeff Kirsher
677e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL)
678e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT01_LANE1 0x00000000ffff0000ULL
679e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT01_LANE0 0x000000000000ffffULL
680e689cf4aSJeff Kirsher
681e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL)
682e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT23_LANE3 0x00000000ffff0000ULL
683e689cf4aSJeff Kirsher #define XPCS_SYMERR_CNT23_LANE2 0x000000000000ffffULL
684e689cf4aSJeff Kirsher
685e689cf4aSJeff Kirsher #define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL)
686e689cf4aSJeff Kirsher #define XPCS_TRAINING_VECTOR_VAL 0x00000000ffffffffULL
687e689cf4aSJeff Kirsher
688e689cf4aSJeff Kirsher /* PCS registers, offset from np->regs + np->pcs_off */
689e689cf4aSJeff Kirsher
690e689cf4aSJeff Kirsher #define PCS_MII_CTL (FZC_MAC + 0x00000UL)
691e689cf4aSJeff Kirsher #define PCS_MII_CTL_RST 0x0000000000008000ULL
692e689cf4aSJeff Kirsher #define PCS_MII_CTL_10_100_SPEED 0x0000000000002000ULL
693e689cf4aSJeff Kirsher #define PCS_MII_AUTONEG_EN 0x0000000000001000ULL
694e689cf4aSJeff Kirsher #define PCS_MII_PWR_DOWN 0x0000000000000800ULL
695e689cf4aSJeff Kirsher #define PCS_MII_ISOLATE 0x0000000000000400ULL
696e689cf4aSJeff Kirsher #define PCS_MII_AUTONEG_RESTART 0x0000000000000200ULL
697e689cf4aSJeff Kirsher #define PCS_MII_DUPLEX 0x0000000000000100ULL
698e689cf4aSJeff Kirsher #define PCS_MII_COLL_TEST 0x0000000000000080ULL
699e689cf4aSJeff Kirsher #define PCS_MII_1000MB_SPEED 0x0000000000000040ULL
700e689cf4aSJeff Kirsher
701e689cf4aSJeff Kirsher #define PCS_MII_STAT (FZC_MAC + 0x00008UL)
702e689cf4aSJeff Kirsher #define PCS_MII_STAT_EXT_STATUS 0x0000000000000100ULL
703e689cf4aSJeff Kirsher #define PCS_MII_STAT_AUTONEG_DONE 0x0000000000000020ULL
704e689cf4aSJeff Kirsher #define PCS_MII_STAT_REMOTE_FAULT 0x0000000000000010ULL
705e689cf4aSJeff Kirsher #define PCS_MII_STAT_AUTONEG_ABLE 0x0000000000000008ULL
706e689cf4aSJeff Kirsher #define PCS_MII_STAT_LINK_STATUS 0x0000000000000004ULL
707e689cf4aSJeff Kirsher #define PCS_MII_STAT_JABBER_DET 0x0000000000000002ULL
708e689cf4aSJeff Kirsher #define PCS_MII_STAT_EXT_CAP 0x0000000000000001ULL
709e689cf4aSJeff Kirsher
710e689cf4aSJeff Kirsher #define PCS_MII_ADV (FZC_MAC + 0x00010UL)
711e689cf4aSJeff Kirsher #define PCS_MII_ADV_NEXT_PAGE 0x0000000000008000ULL
712e689cf4aSJeff Kirsher #define PCS_MII_ADV_ACK 0x0000000000004000ULL
713e689cf4aSJeff Kirsher #define PCS_MII_ADV_REMOTE_FAULT 0x0000000000003000ULL
714e689cf4aSJeff Kirsher #define PCS_MII_ADV_ASM_DIR 0x0000000000000100ULL
715e689cf4aSJeff Kirsher #define PCS_MII_ADV_PAUSE 0x0000000000000080ULL
716e689cf4aSJeff Kirsher #define PCS_MII_ADV_HALF_DUPLEX 0x0000000000000040ULL
717e689cf4aSJeff Kirsher #define PCS_MII_ADV_FULL_DUPLEX 0x0000000000000020ULL
718e689cf4aSJeff Kirsher
719e689cf4aSJeff Kirsher #define PCS_MII_PARTNER (FZC_MAC + 0x00018UL)
720e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_NEXT_PAGE 0x0000000000008000ULL
721e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_ACK 0x0000000000004000ULL
722e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_REMOTE_FAULT 0x0000000000002000ULL
723e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_PAUSE 0x0000000000000180ULL
724e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_HALF_DUPLEX 0x0000000000000040ULL
725e689cf4aSJeff Kirsher #define PCS_MII_PARTNER_FULL_DUPLEX 0x0000000000000020ULL
726e689cf4aSJeff Kirsher
727e689cf4aSJeff Kirsher #define PCS_CONF (FZC_MAC + 0x00020UL)
728e689cf4aSJeff Kirsher #define PCS_CONF_MASK 0x0000000000000040ULL
729e689cf4aSJeff Kirsher #define PCS_CONF_10MS_TMR_OVERRIDE 0x0000000000000020ULL
730e689cf4aSJeff Kirsher #define PCS_CONF_JITTER_STUDY 0x0000000000000018ULL
731e689cf4aSJeff Kirsher #define PCS_CONF_SIGDET_ACTIVE_LOW 0x0000000000000004ULL
732e689cf4aSJeff Kirsher #define PCS_CONF_SIGDET_OVERRIDE 0x0000000000000002ULL
733e689cf4aSJeff Kirsher #define PCS_CONF_ENABLE 0x0000000000000001ULL
734e689cf4aSJeff Kirsher
735e689cf4aSJeff Kirsher #define PCS_STATE (FZC_MAC + 0x00028UL)
736e689cf4aSJeff Kirsher #define PCS_STATE_D_PARTNER_FAIL 0x0000000020000000ULL
737e689cf4aSJeff Kirsher #define PCS_STATE_D_WAIT_C_CODES_ACK 0x0000000010000000ULL
738e689cf4aSJeff Kirsher #define PCS_STATE_D_SYNC_LOSS 0x0000000008000000ULL
739e689cf4aSJeff Kirsher #define PCS_STATE_D_NO_GOOD_C_CODES 0x0000000004000000ULL
740e689cf4aSJeff Kirsher #define PCS_STATE_D_SERDES 0x0000000002000000ULL
741e689cf4aSJeff Kirsher #define PCS_STATE_D_BREAKLINK_C_CODES 0x0000000001000000ULL
742e689cf4aSJeff Kirsher #define PCS_STATE_L_SIGDET 0x0000000000400000ULL
743e689cf4aSJeff Kirsher #define PCS_STATE_L_SYNC_LOSS 0x0000000000200000ULL
744e689cf4aSJeff Kirsher #define PCS_STATE_L_C_CODES 0x0000000000100000ULL
745e689cf4aSJeff Kirsher #define PCS_STATE_LINK_CFG_STATE 0x000000000001e000ULL
746e689cf4aSJeff Kirsher #define PCS_STATE_SEQ_DET_STATE 0x0000000000001800ULL
747e689cf4aSJeff Kirsher #define PCS_STATE_WORD_SYNC_STATE 0x0000000000000700ULL
748e689cf4aSJeff Kirsher #define PCS_STATE_NO_IDLE 0x000000000000000fULL
749e689cf4aSJeff Kirsher
750e689cf4aSJeff Kirsher #define PCS_INTERRUPT (FZC_MAC + 0x00030UL)
751e689cf4aSJeff Kirsher #define PCS_INTERRUPT_LSTATUS 0x0000000000000004ULL
752e689cf4aSJeff Kirsher
753e689cf4aSJeff Kirsher #define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL)
754e689cf4aSJeff Kirsher #define PCS_DPATH_MODE_PCS 0x0000000000000000ULL
755e689cf4aSJeff Kirsher #define PCS_DPATH_MODE_MII 0x0000000000000002ULL
756e689cf4aSJeff Kirsher #define PCS_DPATH_MODE_LINKUP_F_ENAB 0x0000000000000001ULL
757e689cf4aSJeff Kirsher
758e689cf4aSJeff Kirsher #define PCS_PKT_CNT (FZC_MAC + 0x000c0UL)
759e689cf4aSJeff Kirsher #define PCS_PKT_CNT_RX 0x0000000007ff0000ULL
760e689cf4aSJeff Kirsher #define PCS_PKT_CNT_TX 0x00000000000007ffULL
761e689cf4aSJeff Kirsher
762e689cf4aSJeff Kirsher #define MIF_BB_MDC (FZC_MAC + 0x16000UL)
763e689cf4aSJeff Kirsher #define MIF_BB_MDC_CLK 0x0000000000000001ULL
764e689cf4aSJeff Kirsher
765e689cf4aSJeff Kirsher #define MIF_BB_MDO (FZC_MAC + 0x16008UL)
766e689cf4aSJeff Kirsher #define MIF_BB_MDO_DAT 0x0000000000000001ULL
767e689cf4aSJeff Kirsher
768e689cf4aSJeff Kirsher #define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL)
769e689cf4aSJeff Kirsher #define MIF_BB_MDO_EN_VAL 0x0000000000000001ULL
770e689cf4aSJeff Kirsher
771e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL)
772e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_ST 0x00000000c0000000ULL
773e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_ST_SHIFT 30
774e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_OP_ADDR 0x0000000000000000ULL
775e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_OP_WRITE 0x0000000010000000ULL
776e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_OP_READ_INC 0x0000000020000000ULL
777e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_OP_READ 0x0000000030000000ULL
778e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_OP_SHIFT 28
779e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_PORT 0x000000000f800000ULL
780e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_PORT_SHIFT 23
781e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_REG 0x00000000007c0000ULL
782e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_REG_SHIFT 18
783e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_TA 0x0000000000030000ULL
784e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_TA_SHIFT 16
785e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_DATA 0x000000000000ffffULL
786e689cf4aSJeff Kirsher #define MIF_FRAME_OUTPUT_DATA_SHIFT 0
787e689cf4aSJeff Kirsher
788e689cf4aSJeff Kirsher #define MDIO_ADDR_OP(port, dev, reg) \
789e689cf4aSJeff Kirsher ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
790e689cf4aSJeff Kirsher MIF_FRAME_OUTPUT_OP_ADDR | \
791e689cf4aSJeff Kirsher (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
792e689cf4aSJeff Kirsher (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
793e689cf4aSJeff Kirsher (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
794e689cf4aSJeff Kirsher (reg << MIF_FRAME_OUTPUT_DATA_SHIFT))
795e689cf4aSJeff Kirsher
796e689cf4aSJeff Kirsher #define MDIO_READ_OP(port, dev) \
797e689cf4aSJeff Kirsher ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
798e689cf4aSJeff Kirsher MIF_FRAME_OUTPUT_OP_READ | \
799e689cf4aSJeff Kirsher (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
800e689cf4aSJeff Kirsher (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
801e689cf4aSJeff Kirsher (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
802e689cf4aSJeff Kirsher
803e689cf4aSJeff Kirsher #define MDIO_WRITE_OP(port, dev, data) \
804e689cf4aSJeff Kirsher ((0 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
805e689cf4aSJeff Kirsher MIF_FRAME_OUTPUT_OP_WRITE | \
806e689cf4aSJeff Kirsher (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
807e689cf4aSJeff Kirsher (dev << MIF_FRAME_OUTPUT_REG_SHIFT) | \
808e689cf4aSJeff Kirsher (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
809e689cf4aSJeff Kirsher (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
810e689cf4aSJeff Kirsher
811e689cf4aSJeff Kirsher #define MII_READ_OP(port, reg) \
812e689cf4aSJeff Kirsher ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
813e689cf4aSJeff Kirsher (2 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
814e689cf4aSJeff Kirsher (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
815e689cf4aSJeff Kirsher (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
816e689cf4aSJeff Kirsher (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT))
817e689cf4aSJeff Kirsher
818e689cf4aSJeff Kirsher #define MII_WRITE_OP(port, reg, data) \
819e689cf4aSJeff Kirsher ((1 << MIF_FRAME_OUTPUT_ST_SHIFT) | \
820e689cf4aSJeff Kirsher (1 << MIF_FRAME_OUTPUT_OP_SHIFT) | \
821e689cf4aSJeff Kirsher (port << MIF_FRAME_OUTPUT_PORT_SHIFT) | \
822e689cf4aSJeff Kirsher (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \
823e689cf4aSJeff Kirsher (0x2 << MIF_FRAME_OUTPUT_TA_SHIFT) | \
824e689cf4aSJeff Kirsher (data << MIF_FRAME_OUTPUT_DATA_SHIFT))
825e689cf4aSJeff Kirsher
826e689cf4aSJeff Kirsher #define MIF_CONFIG (FZC_MAC + 0x16020UL)
827e689cf4aSJeff Kirsher #define MIF_CONFIG_ATCA_GE 0x0000000000010000ULL
828e689cf4aSJeff Kirsher #define MIF_CONFIG_INDIRECT_MODE 0x0000000000008000ULL
829e689cf4aSJeff Kirsher #define MIF_CONFIG_POLL_PRT_PHYADDR 0x0000000000003c00ULL
830e689cf4aSJeff Kirsher #define MIF_CONFIG_POLL_DEV_REG_ADDR 0x00000000000003e0ULL
831e689cf4aSJeff Kirsher #define MIF_CONFIG_BB_MODE 0x0000000000000010ULL
832e689cf4aSJeff Kirsher #define MIF_CONFIG_POLL_EN 0x0000000000000008ULL
833e689cf4aSJeff Kirsher #define MIF_CONFIG_BB_SER_SEL 0x0000000000000006ULL
834e689cf4aSJeff Kirsher #define MIF_CONFIG_MANUAL_MODE 0x0000000000000001ULL
835e689cf4aSJeff Kirsher
836e689cf4aSJeff Kirsher #define MIF_POLL_STATUS (FZC_MAC + 0x16028UL)
837e689cf4aSJeff Kirsher #define MIF_POLL_STATUS_DATA 0x00000000ffff0000ULL
838e689cf4aSJeff Kirsher #define MIF_POLL_STATUS_STAT 0x000000000000ffffULL
839e689cf4aSJeff Kirsher
840e689cf4aSJeff Kirsher #define MIF_POLL_MASK (FZC_MAC + 0x16030UL)
841e689cf4aSJeff Kirsher #define MIF_POLL_MASK_VAL 0x000000000000ffffULL
842e689cf4aSJeff Kirsher
843e689cf4aSJeff Kirsher #define MIF_SM (FZC_MAC + 0x16038UL)
844e689cf4aSJeff Kirsher #define MIF_SM_PORT_ADDR 0x00000000001f0000ULL
845e689cf4aSJeff Kirsher #define MIF_SM_MDI_1 0x0000000000004000ULL
846e689cf4aSJeff Kirsher #define MIF_SM_MDI_0 0x0000000000002400ULL
847e689cf4aSJeff Kirsher #define MIF_SM_MDCLK 0x0000000000001000ULL
848e689cf4aSJeff Kirsher #define MIF_SM_MDO_EN 0x0000000000000800ULL
849e689cf4aSJeff Kirsher #define MIF_SM_MDO 0x0000000000000400ULL
850e689cf4aSJeff Kirsher #define MIF_SM_MDI 0x0000000000000200ULL
851e689cf4aSJeff Kirsher #define MIF_SM_CTL 0x00000000000001c0ULL
852e689cf4aSJeff Kirsher #define MIF_SM_EX 0x000000000000003fULL
853e689cf4aSJeff Kirsher
854e689cf4aSJeff Kirsher #define MIF_STATUS (FZC_MAC + 0x16040UL)
855e689cf4aSJeff Kirsher #define MIF_STATUS_MDINT1 0x0000000000000020ULL
856e689cf4aSJeff Kirsher #define MIF_STATUS_MDINT0 0x0000000000000010ULL
857e689cf4aSJeff Kirsher
858e689cf4aSJeff Kirsher #define MIF_MASK (FZC_MAC + 0x16048UL)
859e689cf4aSJeff Kirsher #define MIF_MASK_MDINT1 0x0000000000000020ULL
860e689cf4aSJeff Kirsher #define MIF_MASK_MDINT0 0x0000000000000010ULL
861e689cf4aSJeff Kirsher #define MIF_MASK_PEU_ERR 0x0000000000000008ULL
862e689cf4aSJeff Kirsher #define MIF_MASK_YC 0x0000000000000004ULL
863e689cf4aSJeff Kirsher #define MIF_MASK_XGE_ERR0 0x0000000000000002ULL
864e689cf4aSJeff Kirsher #define MIF_MASK_MIF_INIT_DONE 0x0000000000000001ULL
865e689cf4aSJeff Kirsher
866e689cf4aSJeff Kirsher #define ENET_SERDES_RESET (FZC_MAC + 0x14000UL)
867e689cf4aSJeff Kirsher #define ENET_SERDES_RESET_1 0x0000000000000002ULL
868e689cf4aSJeff Kirsher #define ENET_SERDES_RESET_0 0x0000000000000001ULL
869e689cf4aSJeff Kirsher
870e689cf4aSJeff Kirsher #define ENET_SERDES_CFG (FZC_MAC + 0x14008UL)
871e689cf4aSJeff Kirsher #define ENET_SERDES_BE_LOOPBACK 0x0000000000000002ULL
872e689cf4aSJeff Kirsher #define ENET_SERDES_CFG_FORCE_RDY 0x0000000000000001ULL
873e689cf4aSJeff Kirsher
874e689cf4aSJeff Kirsher #define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL)
875e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_FBDIV0 0x0000000000000001ULL
876e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_FBDIV1 0x0000000000000002ULL
877e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_FBDIV2 0x0000000000000004ULL
878e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_HRATE0 0x0000000000000008ULL
879e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_HRATE1 0x0000000000000010ULL
880e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_HRATE2 0x0000000000000020ULL
881e689cf4aSJeff Kirsher #define ENET_SERDES_PLL_HRATE3 0x0000000000000040ULL
882e689cf4aSJeff Kirsher
883e689cf4aSJeff Kirsher #define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL)
884e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_SDET_0 0x0000000000000001ULL
885e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_SDET_1 0x0000000000000002ULL
886e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_SDET_2 0x0000000000000004ULL
887e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_SDET_3 0x0000000000000008ULL
888e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_0 0x0000000000000070ULL
889e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_0_SHIFT 4
890e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_1 0x0000000000000380ULL
891e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_1_SHIFT 7
892e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_2 0x0000000000001c00ULL
893e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_2_SHIFT 10
894e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_3 0x000000000000e000ULL
895e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_EMPH_3_SHIFT 13
896e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_0 0x0000000000070000ULL
897e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_0_SHIFT 16
898e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_1 0x0000000000380000ULL
899e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_1_SHIFT 19
900e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_2 0x0000000001c00000ULL
901e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_2_SHIFT 22
902e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_3 0x000000000e000000ULL
903e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_LADJ_3_SHIFT 25
904e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_RXITERM_0 0x0000000010000000ULL
905e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_RXITERM_1 0x0000000020000000ULL
906e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_RXITERM_2 0x0000000040000000ULL
907e689cf4aSJeff Kirsher #define ENET_SERDES_CTRL_RXITERM_3 0x0000000080000000ULL
908e689cf4aSJeff Kirsher
909e689cf4aSJeff Kirsher #define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL)
910e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_0 0x0000000000000003ULL
911e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_0_SHIFT 0
912e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_1 0x000000000000000cULL
913e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_1_SHIFT 2
914e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_2 0x0000000000000030ULL
915e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_2_SHIFT 4
916e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_3 0x00000000000000c0ULL
917e689cf4aSJeff Kirsher #define ENET_SERDES_TEST_MD_3_SHIFT 6
918e689cf4aSJeff Kirsher
919e689cf4aSJeff Kirsher #define ENET_TEST_MD_NO_LOOPBACK 0x0
920e689cf4aSJeff Kirsher #define ENET_TEST_MD_EWRAP 0x1
921e689cf4aSJeff Kirsher #define ENET_TEST_MD_PAD_LOOPBACK 0x2
922e689cf4aSJeff Kirsher #define ENET_TEST_MD_REV_LOOPBACK 0x3
923e689cf4aSJeff Kirsher
924e689cf4aSJeff Kirsher #define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL)
925e689cf4aSJeff Kirsher #define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL)
926e689cf4aSJeff Kirsher #define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL)
927e689cf4aSJeff Kirsher
928e689cf4aSJeff Kirsher #define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL)
929e689cf4aSJeff Kirsher
930e689cf4aSJeff Kirsher #define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL)
931e689cf4aSJeff Kirsher #define ESR_INT_SIGNALS_ALL 0x00000000ffffffffULL
932e689cf4aSJeff Kirsher #define ESR_INT_SIGNALS_P0_BITS 0x0000000033e0000fULL
933e689cf4aSJeff Kirsher #define ESR_INT_SIGNALS_P1_BITS 0x000000000c1f00f0ULL
934e689cf4aSJeff Kirsher #define ESR_INT_SRDY0_P0 0x0000000020000000ULL
935e689cf4aSJeff Kirsher #define ESR_INT_DET0_P0 0x0000000010000000ULL
936e689cf4aSJeff Kirsher #define ESR_INT_SRDY0_P1 0x0000000008000000ULL
937e689cf4aSJeff Kirsher #define ESR_INT_DET0_P1 0x0000000004000000ULL
938e689cf4aSJeff Kirsher #define ESR_INT_XSRDY_P0 0x0000000002000000ULL
939e689cf4aSJeff Kirsher #define ESR_INT_XDP_P0_CH3 0x0000000001000000ULL
940e689cf4aSJeff Kirsher #define ESR_INT_XDP_P0_CH2 0x0000000000800000ULL
941e689cf4aSJeff Kirsher #define ESR_INT_XDP_P0_CH1 0x0000000000400000ULL
942e689cf4aSJeff Kirsher #define ESR_INT_XDP_P0_CH0 0x0000000000200000ULL
943e689cf4aSJeff Kirsher #define ESR_INT_XSRDY_P1 0x0000000000100000ULL
944e689cf4aSJeff Kirsher #define ESR_INT_XDP_P1_CH3 0x0000000000080000ULL
945e689cf4aSJeff Kirsher #define ESR_INT_XDP_P1_CH2 0x0000000000040000ULL
946e689cf4aSJeff Kirsher #define ESR_INT_XDP_P1_CH1 0x0000000000020000ULL
947e689cf4aSJeff Kirsher #define ESR_INT_XDP_P1_CH0 0x0000000000010000ULL
948e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P1_CH3 0x0000000000000080ULL
949e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P1_CH2 0x0000000000000040ULL
950e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P1_CH1 0x0000000000000020ULL
951e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P1_CH0 0x0000000000000010ULL
952e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P0_CH3 0x0000000000000008ULL
953e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P0_CH2 0x0000000000000004ULL
954e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P0_CH1 0x0000000000000002ULL
955e689cf4aSJeff Kirsher #define ESR_INT_SLOSS_P0_CH0 0x0000000000000001ULL
956e689cf4aSJeff Kirsher
957e689cf4aSJeff Kirsher #define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL)
958e689cf4aSJeff Kirsher #define ESR_DEBUG_SEL_VAL 0x000000000000003fULL
959e689cf4aSJeff Kirsher
960e689cf4aSJeff Kirsher /* SerDes registers behind MIF */
961e689cf4aSJeff Kirsher #define NIU_ESR_DEV_ADDR 0x1e
962e689cf4aSJeff Kirsher #define ESR_BASE 0x0000
963e689cf4aSJeff Kirsher
964e689cf4aSJeff Kirsher #define ESR_RXTX_COMM_CTRL_L (ESR_BASE + 0x0000)
965e689cf4aSJeff Kirsher #define ESR_RXTX_COMM_CTRL_H (ESR_BASE + 0x0001)
966e689cf4aSJeff Kirsher
967e689cf4aSJeff Kirsher #define ESR_RXTX_RESET_CTRL_L (ESR_BASE + 0x0002)
968e689cf4aSJeff Kirsher #define ESR_RXTX_RESET_CTRL_H (ESR_BASE + 0x0003)
969e689cf4aSJeff Kirsher
970e689cf4aSJeff Kirsher #define ESR_RX_POWER_CTRL_L (ESR_BASE + 0x0004)
971e689cf4aSJeff Kirsher #define ESR_RX_POWER_CTRL_H (ESR_BASE + 0x0005)
972e689cf4aSJeff Kirsher
973e689cf4aSJeff Kirsher #define ESR_TX_POWER_CTRL_L (ESR_BASE + 0x0006)
974e689cf4aSJeff Kirsher #define ESR_TX_POWER_CTRL_H (ESR_BASE + 0x0007)
975e689cf4aSJeff Kirsher
976e689cf4aSJeff Kirsher #define ESR_MISC_POWER_CTRL_L (ESR_BASE + 0x0008)
977e689cf4aSJeff Kirsher #define ESR_MISC_POWER_CTRL_H (ESR_BASE + 0x0009)
978e689cf4aSJeff Kirsher
979e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_L(CHAN) (ESR_BASE + 0x0080 + (CHAN) * 0x10)
980e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_H(CHAN) (ESR_BASE + 0x0081 + (CHAN) * 0x10)
981e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_BIASCNTL 0x80000000
982e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RESV1 0x7c000000
983e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_TDENFIFO 0x02000000
984e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_TDWS20 0x01000000
985e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_VMUXLO 0x00c00000
986e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_VMUXLO_SHIFT 22
987e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_VPULSELO 0x00300000
988e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_VPULSELO_SHIFT 20
989e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RESV2 0x000f0000
990e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RESV3 0x0000c000
991e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RXPRESWIN 0x00003000
992e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RXPRESWIN_SHIFT 12
993e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RESV4 0x00000800
994e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RISEFALL 0x00000700
995e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RISEFALL_SHIFT 8
996e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_RESV5 0x000000fe
997e689cf4aSJeff Kirsher #define ESR_RXTX_CTRL_ENSTRETCH 0x00000001
998e689cf4aSJeff Kirsher
999e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING_L(CHAN) (ESR_BASE + 0x0082 + (CHAN) * 0x10)
1000e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING_H(CHAN) (ESR_BASE + 0x0083 + (CHAN) * 0x10)
1001e689cf4aSJeff Kirsher
1002e689cf4aSJeff Kirsher #define ESR_RX_SYNCCHAR_L(CHAN) (ESR_BASE + 0x0084 + (CHAN) * 0x10)
1003e689cf4aSJeff Kirsher #define ESR_RX_SYNCCHAR_H(CHAN) (ESR_BASE + 0x0085 + (CHAN) * 0x10)
1004e689cf4aSJeff Kirsher
1005e689cf4aSJeff Kirsher #define ESR_RXTX_TEST_L(CHAN) (ESR_BASE + 0x0086 + (CHAN) * 0x10)
1006e689cf4aSJeff Kirsher #define ESR_RXTX_TEST_H(CHAN) (ESR_BASE + 0x0087 + (CHAN) * 0x10)
1007e689cf4aSJeff Kirsher
1008e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_L(CHAN) (ESR_BASE + 0x0088 + (CHAN) * 0x10)
1009e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_H(CHAN) (ESR_BASE + 0x0089 + (CHAN) * 0x10)
1010e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_RESV1 0xf8000000
1011e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_BLTIME 0x07000000
1012e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_BLTIME_SHIFT 24
1013e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_RESV2 0x00ff0000
1014e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_RXLOS_TEST 0x00008000
1015e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_RESV3 0x00004000
1016e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_RXLOSENAB 0x00002000
1017e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_FASTRESYNC 0x00001000
1018e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_SRATE 0x00000f00
1019e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_SRATE_SHIFT 8
1020e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_THCNT 0x000000ff
1021e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL0_THCNT_SHIFT 0
1022e689cf4aSJeff Kirsher
1023e689cf4aSJeff Kirsher #define BLTIME_64_CYCLES 0
1024e689cf4aSJeff Kirsher #define BLTIME_128_CYCLES 1
1025e689cf4aSJeff Kirsher #define BLTIME_256_CYCLES 2
1026e689cf4aSJeff Kirsher #define BLTIME_300_CYCLES 3
1027e689cf4aSJeff Kirsher #define BLTIME_384_CYCLES 4
1028e689cf4aSJeff Kirsher #define BLTIME_512_CYCLES 5
1029e689cf4aSJeff Kirsher #define BLTIME_1024_CYCLES 6
1030e689cf4aSJeff Kirsher #define BLTIME_2048_CYCLES 7
1031e689cf4aSJeff Kirsher
1032e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL1_L(CHAN) (ESR_BASE + 0x008a + (CHAN) * 0x10)
1033e689cf4aSJeff Kirsher #define ESR_GLUE_CTRL1_H(CHAN) (ESR_BASE + 0x008b + (CHAN) * 0x10)
1034e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING1_L(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1035e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING1_H(CHAN) (ESR_BASE + 0x00c2 + (CHAN) * 0x10)
1036e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING2_L(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1037e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING2_H(CHAN) (ESR_BASE + 0x0102 + (CHAN) * 0x10)
1038e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING3_L(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1039e689cf4aSJeff Kirsher #define ESR_RXTX_TUNING3_H(CHAN) (ESR_BASE + 0x0142 + (CHAN) * 0x10)
1040e689cf4aSJeff Kirsher
1041e689cf4aSJeff Kirsher #define NIU_ESR2_DEV_ADDR 0x1e
1042e689cf4aSJeff Kirsher #define ESR2_BASE 0x8000
1043e689cf4aSJeff Kirsher
1044e689cf4aSJeff Kirsher #define ESR2_TI_PLL_CFG_L (ESR2_BASE + 0x000)
1045e689cf4aSJeff Kirsher #define ESR2_TI_PLL_CFG_H (ESR2_BASE + 0x001)
1046e689cf4aSJeff Kirsher #define PLL_CFG_STD 0x00000c00
1047e689cf4aSJeff Kirsher #define PLL_CFG_STD_SHIFT 10
1048e689cf4aSJeff Kirsher #define PLL_CFG_LD 0x00000300
1049e689cf4aSJeff Kirsher #define PLL_CFG_LD_SHIFT 8
1050e689cf4aSJeff Kirsher #define PLL_CFG_MPY 0x0000001e
1051e689cf4aSJeff Kirsher #define PLL_CFG_MPY_SHIFT 1
1052e689cf4aSJeff Kirsher #define PLL_CFG_MPY_4X 0x0
1053e689cf4aSJeff Kirsher #define PLL_CFG_MPY_5X 0x00000002
1054e689cf4aSJeff Kirsher #define PLL_CFG_MPY_6X 0x00000004
1055e689cf4aSJeff Kirsher #define PLL_CFG_MPY_8X 0x00000008
1056e689cf4aSJeff Kirsher #define PLL_CFG_MPY_10X 0x0000000a
1057e689cf4aSJeff Kirsher #define PLL_CFG_MPY_12X 0x0000000c
1058e689cf4aSJeff Kirsher #define PLL_CFG_MPY_12P5X 0x0000000e
1059e689cf4aSJeff Kirsher #define PLL_CFG_ENPLL 0x00000001
1060e689cf4aSJeff Kirsher
1061e689cf4aSJeff Kirsher #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002)
1062e689cf4aSJeff Kirsher #define ESR2_TI_PLL_STS_H (ESR2_BASE + 0x003)
1063e689cf4aSJeff Kirsher #define PLL_STS_LOCK 0x00000001
1064e689cf4aSJeff Kirsher
1065e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TEST_CFG_L (ESR2_BASE + 0x004)
1066e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TEST_CFG_H (ESR2_BASE + 0x005)
1067e689cf4aSJeff Kirsher #define PLL_TEST_INVPATT 0x00004000
1068e689cf4aSJeff Kirsher #define PLL_TEST_RATE 0x00003000
1069e689cf4aSJeff Kirsher #define PLL_TEST_RATE_SHIFT 12
1070e689cf4aSJeff Kirsher #define PLL_TEST_CFG_ENBSAC 0x00000400
1071e689cf4aSJeff Kirsher #define PLL_TEST_CFG_ENBSRX 0x00000200
1072e689cf4aSJeff Kirsher #define PLL_TEST_CFG_ENBSTX 0x00000100
1073e689cf4aSJeff Kirsher #define PLL_TEST_CFG_LOOPBACK_PAD 0x00000040
1074e689cf4aSJeff Kirsher #define PLL_TEST_CFG_LOOPBACK_CML_DIS 0x00000080
1075e689cf4aSJeff Kirsher #define PLL_TEST_CFG_LOOPBACK_CML_EN 0x000000c0
1076e689cf4aSJeff Kirsher #define PLL_TEST_CFG_CLKBYP 0x00000030
1077e689cf4aSJeff Kirsher #define PLL_TEST_CFG_CLKBYP_SHIFT 4
1078e689cf4aSJeff Kirsher #define PLL_TEST_CFG_EN_RXPATT 0x00000008
1079e689cf4aSJeff Kirsher #define PLL_TEST_CFG_EN_TXPATT 0x00000004
1080e689cf4aSJeff Kirsher #define PLL_TEST_CFG_TPATT 0x00000003
1081e689cf4aSJeff Kirsher #define PLL_TEST_CFG_TPATT_SHIFT 0
1082e689cf4aSJeff Kirsher
1083e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TX_CFG_L(CHAN) (ESR2_BASE + 0x100 + (CHAN) * 4)
1084e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TX_CFG_H(CHAN) (ESR2_BASE + 0x101 + (CHAN) * 4)
1085e689cf4aSJeff Kirsher #define PLL_TX_CFG_RDTCT 0x00600000
1086e689cf4aSJeff Kirsher #define PLL_TX_CFG_RDTCT_SHIFT 21
1087e689cf4aSJeff Kirsher #define PLL_TX_CFG_ENIDL 0x00100000
1088e689cf4aSJeff Kirsher #define PLL_TX_CFG_BSTX 0x00020000
1089e689cf4aSJeff Kirsher #define PLL_TX_CFG_ENFTP 0x00010000
1090e689cf4aSJeff Kirsher #define PLL_TX_CFG_DE 0x0000f000
1091e689cf4aSJeff Kirsher #define PLL_TX_CFG_DE_SHIFT 12
1092e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_125MV 0x00000000
1093e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_250MV 0x00000200
1094e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_500MV 0x00000400
1095e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_625MV 0x00000600
1096e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_750MV 0x00000800
1097e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_1000MV 0x00000a00
1098e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_1250MV 0x00000c00
1099e689cf4aSJeff Kirsher #define PLL_TX_CFG_SWING_1375MV 0x00000e00
1100e689cf4aSJeff Kirsher #define PLL_TX_CFG_CM 0x00000100
1101e689cf4aSJeff Kirsher #define PLL_TX_CFG_INVPAIR 0x00000080
1102e689cf4aSJeff Kirsher #define PLL_TX_CFG_RATE 0x00000060
1103e689cf4aSJeff Kirsher #define PLL_TX_CFG_RATE_SHIFT 5
1104e689cf4aSJeff Kirsher #define PLL_TX_CFG_RATE_FULL 0x0
1105e689cf4aSJeff Kirsher #define PLL_TX_CFG_RATE_HALF 0x20
1106e689cf4aSJeff Kirsher #define PLL_TX_CFG_RATE_QUAD 0x40
1107e689cf4aSJeff Kirsher #define PLL_TX_CFG_BUSWIDTH 0x0000001c
1108e689cf4aSJeff Kirsher #define PLL_TX_CFG_BUSWIDTH_SHIFT 2
1109e689cf4aSJeff Kirsher #define PLL_TX_CFG_ENTEST 0x00000002
1110e689cf4aSJeff Kirsher #define PLL_TX_CFG_ENTX 0x00000001
1111e689cf4aSJeff Kirsher
1112e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TX_STS_L(CHAN) (ESR2_BASE + 0x102 + (CHAN) * 4)
1113e689cf4aSJeff Kirsher #define ESR2_TI_PLL_TX_STS_H(CHAN) (ESR2_BASE + 0x103 + (CHAN) * 4)
1114e689cf4aSJeff Kirsher #define PLL_TX_STS_RDTCTIP 0x00000002
1115e689cf4aSJeff Kirsher #define PLL_TX_STS_TESTFAIL 0x00000001
1116e689cf4aSJeff Kirsher
1117e689cf4aSJeff Kirsher #define ESR2_TI_PLL_RX_CFG_L(CHAN) (ESR2_BASE + 0x120 + (CHAN) * 4)
1118e689cf4aSJeff Kirsher #define ESR2_TI_PLL_RX_CFG_H(CHAN) (ESR2_BASE + 0x121 + (CHAN) * 4)
1119e689cf4aSJeff Kirsher #define PLL_RX_CFG_BSINRXN 0x02000000
1120e689cf4aSJeff Kirsher #define PLL_RX_CFG_BSINRXP 0x01000000
1121e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_MAX_LF 0x00000000
1122e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_ADAPTIVE 0x00080000
1123e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_1084MHZ 0x00400000
1124e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_805MHZ 0x00480000
1125e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_573MHZ 0x00500000
1126e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_402MHZ 0x00580000
1127e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_304MHZ 0x00600000
1128e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_216MHZ 0x00680000
1129e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_156MHZ 0x00700000
1130e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_LP_135MHZ 0x00780000
1131e689cf4aSJeff Kirsher #define PLL_RX_CFG_EQ_SHIFT 19
1132e689cf4aSJeff Kirsher #define PLL_RX_CFG_CDR 0x00070000
1133e689cf4aSJeff Kirsher #define PLL_RX_CFG_CDR_SHIFT 16
1134e689cf4aSJeff Kirsher #define PLL_RX_CFG_LOS_DIS 0x00000000
1135e689cf4aSJeff Kirsher #define PLL_RX_CFG_LOS_HTHRESH 0x00004000
1136e689cf4aSJeff Kirsher #define PLL_RX_CFG_LOS_LTHRESH 0x00008000
1137e689cf4aSJeff Kirsher #define PLL_RX_CFG_ALIGN_DIS 0x00000000
1138e689cf4aSJeff Kirsher #define PLL_RX_CFG_ALIGN_ENA 0x00001000
1139e689cf4aSJeff Kirsher #define PLL_RX_CFG_ALIGN_JOG 0x00002000
1140e689cf4aSJeff Kirsher #define PLL_RX_CFG_TERM_VDDT 0x00000000
1141e689cf4aSJeff Kirsher #define PLL_RX_CFG_TERM_0P8VDDT 0x00000100
1142e689cf4aSJeff Kirsher #define PLL_RX_CFG_TERM_FLOAT 0x00000300
1143e689cf4aSJeff Kirsher #define PLL_RX_CFG_INVPAIR 0x00000080
1144e689cf4aSJeff Kirsher #define PLL_RX_CFG_RATE 0x00000060
1145e689cf4aSJeff Kirsher #define PLL_RX_CFG_RATE_SHIFT 5
1146e689cf4aSJeff Kirsher #define PLL_RX_CFG_RATE_FULL 0x0
1147e689cf4aSJeff Kirsher #define PLL_RX_CFG_RATE_HALF 0x20
1148e689cf4aSJeff Kirsher #define PLL_RX_CFG_RATE_QUAD 0x40
1149e689cf4aSJeff Kirsher #define PLL_RX_CFG_BUSWIDTH 0x0000001c
1150e689cf4aSJeff Kirsher #define PLL_RX_CFG_BUSWIDTH_SHIFT 2
1151e689cf4aSJeff Kirsher #define PLL_RX_CFG_ENTEST 0x00000002
1152e689cf4aSJeff Kirsher #define PLL_RX_CFG_ENRX 0x00000001
1153e689cf4aSJeff Kirsher
1154e689cf4aSJeff Kirsher #define ESR2_TI_PLL_RX_STS_L(CHAN) (ESR2_BASE + 0x122 + (CHAN) * 4)
1155e689cf4aSJeff Kirsher #define ESR2_TI_PLL_RX_STS_H(CHAN) (ESR2_BASE + 0x123 + (CHAN) * 4)
1156e689cf4aSJeff Kirsher #define PLL_RX_STS_CRCIDTCT 0x00000200
1157e689cf4aSJeff Kirsher #define PLL_RX_STS_CWDTCT 0x00000100
1158e689cf4aSJeff Kirsher #define PLL_RX_STS_BSRXN 0x00000020
1159e689cf4aSJeff Kirsher #define PLL_RX_STS_BSRXP 0x00000010
1160e689cf4aSJeff Kirsher #define PLL_RX_STS_LOSDTCT 0x00000008
1161e689cf4aSJeff Kirsher #define PLL_RX_STS_ODDCG 0x00000004
1162e689cf4aSJeff Kirsher #define PLL_RX_STS_SYNC 0x00000002
1163e689cf4aSJeff Kirsher #define PLL_RX_STS_TESTFAIL 0x00000001
1164e689cf4aSJeff Kirsher
1165e689cf4aSJeff Kirsher #define ENET_VLAN_TBL(IDX) (FZC_FFLP + 0x00000UL + (IDX) * 8UL)
1166e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_PARITY1 0x0000000000020000ULL
1167e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_PARITY0 0x0000000000010000ULL
1168e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_VPR 0x0000000000000008ULL
1169e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_VLANRDCTBLN 0x0000000000000007ULL
1170e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_SHIFT(PORT) ((PORT) * 4)
1171e689cf4aSJeff Kirsher
1172e689cf4aSJeff Kirsher #define ENET_VLAN_TBL_NUM_ENTRIES 4096
1173e689cf4aSJeff Kirsher
1174e689cf4aSJeff Kirsher #define FFLP_VLAN_PAR_ERR (FZC_FFLP + 0x0800UL)
1175e689cf4aSJeff Kirsher #define FFLP_VLAN_PAR_ERR_ERR 0x0000000080000000ULL
1176e689cf4aSJeff Kirsher #define FFLP_VLAN_PAR_ERR_M_ERR 0x0000000040000000ULL
1177e689cf4aSJeff Kirsher #define FFLP_VLAN_PAR_ERR_ADDR 0x000000003ffc0000ULL
1178e689cf4aSJeff Kirsher #define FFLP_VLAN_PAR_ERR_DATA 0x000000000003ffffULL
1179e689cf4aSJeff Kirsher
1180e689cf4aSJeff Kirsher #define L2_CLS(IDX) (FZC_FFLP + 0x20000UL + (IDX) * 8UL)
1181e689cf4aSJeff Kirsher #define L2_CLS_VLD 0x0000000000010000ULL
1182e689cf4aSJeff Kirsher #define L2_CLS_ETYPE 0x000000000000ffffULL
1183e689cf4aSJeff Kirsher #define L2_CLS_ETYPE_SHIFT 0
1184e689cf4aSJeff Kirsher
1185e689cf4aSJeff Kirsher #define L3_CLS(IDX) (FZC_FFLP + 0x20010UL + (IDX) * 8UL)
1186e689cf4aSJeff Kirsher #define L3_CLS_VALID 0x0000000002000000ULL
1187e689cf4aSJeff Kirsher #define L3_CLS_IPVER 0x0000000001000000ULL
1188e689cf4aSJeff Kirsher #define L3_CLS_PID 0x0000000000ff0000ULL
1189e689cf4aSJeff Kirsher #define L3_CLS_PID_SHIFT 16
1190e689cf4aSJeff Kirsher #define L3_CLS_TOSMASK 0x000000000000ff00ULL
1191e689cf4aSJeff Kirsher #define L3_CLS_TOSMASK_SHIFT 8
1192e689cf4aSJeff Kirsher #define L3_CLS_TOS 0x00000000000000ffULL
1193e689cf4aSJeff Kirsher #define L3_CLS_TOS_SHIFT 0
1194e689cf4aSJeff Kirsher
1195e689cf4aSJeff Kirsher #define TCAM_KEY(IDX) (FZC_FFLP + 0x20030UL + (IDX) * 8UL)
1196e689cf4aSJeff Kirsher #define TCAM_KEY_DISC 0x0000000000000008ULL
1197e689cf4aSJeff Kirsher #define TCAM_KEY_TSEL 0x0000000000000004ULL
1198e689cf4aSJeff Kirsher #define TCAM_KEY_IPADDR 0x0000000000000001ULL
1199e689cf4aSJeff Kirsher
1200e689cf4aSJeff Kirsher #define TCAM_KEY_0 (FZC_FFLP + 0x20090UL)
1201e689cf4aSJeff Kirsher #define TCAM_KEY_0_KEY 0x00000000000000ffULL /* bits 192-199 */
1202e689cf4aSJeff Kirsher
1203e689cf4aSJeff Kirsher #define TCAM_KEY_1 (FZC_FFLP + 0x20098UL)
1204e689cf4aSJeff Kirsher #define TCAM_KEY_1_KEY 0xffffffffffffffffULL /* bits 128-191 */
1205e689cf4aSJeff Kirsher
1206e689cf4aSJeff Kirsher #define TCAM_KEY_2 (FZC_FFLP + 0x200a0UL)
1207e689cf4aSJeff Kirsher #define TCAM_KEY_2_KEY 0xffffffffffffffffULL /* bits 64-127 */
1208e689cf4aSJeff Kirsher
1209e689cf4aSJeff Kirsher #define TCAM_KEY_3 (FZC_FFLP + 0x200a8UL)
1210e689cf4aSJeff Kirsher #define TCAM_KEY_3_KEY 0xffffffffffffffffULL /* bits 0-63 */
1211e689cf4aSJeff Kirsher
1212e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_0 (FZC_FFLP + 0x200b0UL)
1213e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_0_KEY_SEL 0x00000000000000ffULL /* bits 192-199 */
1214e689cf4aSJeff Kirsher
1215e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_1 (FZC_FFLP + 0x200b8UL)
1216e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_1_KEY_SEL 0xffffffffffffffffULL /* bits 128-191 */
1217e689cf4aSJeff Kirsher
1218e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_2 (FZC_FFLP + 0x200c0UL)
1219e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_2_KEY_SEL 0xffffffffffffffffULL /* bits 64-127 */
1220e689cf4aSJeff Kirsher
1221e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_3 (FZC_FFLP + 0x200c8UL)
1222e689cf4aSJeff Kirsher #define TCAM_KEY_MASK_3_KEY_SEL 0xffffffffffffffffULL /* bits 0-63 */
1223e689cf4aSJeff Kirsher
1224e689cf4aSJeff Kirsher #define TCAM_CTL (FZC_FFLP + 0x200d0UL)
1225e689cf4aSJeff Kirsher #define TCAM_CTL_RWC 0x00000000001c0000ULL
1226e689cf4aSJeff Kirsher #define TCAM_CTL_RWC_TCAM_WRITE 0x0000000000000000ULL
1227e689cf4aSJeff Kirsher #define TCAM_CTL_RWC_TCAM_READ 0x0000000000040000ULL
1228e689cf4aSJeff Kirsher #define TCAM_CTL_RWC_TCAM_COMPARE 0x0000000000080000ULL
1229e689cf4aSJeff Kirsher #define TCAM_CTL_RWC_RAM_WRITE 0x0000000000100000ULL
1230e689cf4aSJeff Kirsher #define TCAM_CTL_RWC_RAM_READ 0x0000000000140000ULL
1231e689cf4aSJeff Kirsher #define TCAM_CTL_STAT 0x0000000000020000ULL
1232e689cf4aSJeff Kirsher #define TCAM_CTL_MATCH 0x0000000000010000ULL
1233e689cf4aSJeff Kirsher #define TCAM_CTL_LOC 0x00000000000003ffULL
1234e689cf4aSJeff Kirsher
1235e689cf4aSJeff Kirsher #define TCAM_ERR (FZC_FFLP + 0x200d8UL)
1236e689cf4aSJeff Kirsher #define TCAM_ERR_ERR 0x0000000080000000ULL
1237e689cf4aSJeff Kirsher #define TCAM_ERR_P_ECC 0x0000000040000000ULL
1238e689cf4aSJeff Kirsher #define TCAM_ERR_MULT 0x0000000020000000ULL
1239e689cf4aSJeff Kirsher #define TCAM_ERR_ADDR 0x0000000000ff0000ULL
1240e689cf4aSJeff Kirsher #define TCAM_ERR_SYNDROME 0x000000000000ffffULL
1241e689cf4aSJeff Kirsher
1242e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG1 (FZC_FFLP + 0x200e0UL)
1243e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG1_ERR 0x0000000000000008ULL
1244e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG1_MULT_LK 0x0000000000000004ULL
1245e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG1_CU 0x0000000000000002ULL
1246e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG1_MULT_BIT 0x0000000000000001ULL
1247e689cf4aSJeff Kirsher
1248e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG2 (FZC_FFLP + 0x200e8UL)
1249e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG2_H1 0x000000007ffff800ULL
1250e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG2_SUBAREA 0x0000000000000700ULL
1251e689cf4aSJeff Kirsher #define HASH_LOOKUP_ERR_LOG2_SYNDROME 0x00000000000000ffULL
1252e689cf4aSJeff Kirsher
1253e689cf4aSJeff Kirsher #define FFLP_CFG_1 (FZC_FFLP + 0x20100UL)
1254e689cf4aSJeff Kirsher #define FFLP_CFG_1_TCAM_DIS 0x0000000004000000ULL
1255e689cf4aSJeff Kirsher #define FFLP_CFG_1_PIO_DBG_SEL 0x0000000003800000ULL
1256e689cf4aSJeff Kirsher #define FFLP_CFG_1_PIO_FIO_RST 0x0000000000400000ULL
1257e689cf4aSJeff Kirsher #define FFLP_CFG_1_PIO_FIO_LAT 0x0000000000300000ULL
1258e689cf4aSJeff Kirsher #define FFLP_CFG_1_CAMLAT 0x00000000000f0000ULL
1259e689cf4aSJeff Kirsher #define FFLP_CFG_1_CAMLAT_SHIFT 16
1260e689cf4aSJeff Kirsher #define FFLP_CFG_1_CAMRATIO 0x000000000000f000ULL
1261e689cf4aSJeff Kirsher #define FFLP_CFG_1_CAMRATIO_SHIFT 12
1262e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMRATIO 0x0000000000000f00ULL
1263e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMRATIO_SHIFT 8
1264e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMOUTDR_MASK 0x00000000000000f0ULL
1265e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMOUTDR_NORMAL 0x0000000000000000ULL
1266e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMOUTDR_STRONG 0x0000000000000050ULL
1267e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMOUTDR_WEAK 0x00000000000000a0ULL
1268e689cf4aSJeff Kirsher #define FFLP_CFG_1_FCRAMQS 0x0000000000000008ULL
1269e689cf4aSJeff Kirsher #define FFLP_CFG_1_ERRORDIS 0x0000000000000004ULL
1270e689cf4aSJeff Kirsher #define FFLP_CFG_1_FFLPINITDONE 0x0000000000000002ULL
1271e689cf4aSJeff Kirsher #define FFLP_CFG_1_LLCSNAP 0x0000000000000001ULL
1272e689cf4aSJeff Kirsher
1273e689cf4aSJeff Kirsher #define DEFAULT_FCRAMRATIO 10
1274e689cf4aSJeff Kirsher
1275e689cf4aSJeff Kirsher #define DEFAULT_TCAM_LATENCY 4
1276e689cf4aSJeff Kirsher #define DEFAULT_TCAM_ACCESS_RATIO 10
1277e689cf4aSJeff Kirsher
1278e689cf4aSJeff Kirsher #define TCP_CFLAG_MSK (FZC_FFLP + 0x20108UL)
1279e689cf4aSJeff Kirsher #define TCP_CFLAG_MSK_MASK 0x0000000000000fffULL
1280e689cf4aSJeff Kirsher
1281e689cf4aSJeff Kirsher #define FCRAM_REF_TMR (FZC_FFLP + 0x20110UL)
1282e689cf4aSJeff Kirsher #define FCRAM_REF_TMR_MAX 0x00000000ffff0000ULL
1283e689cf4aSJeff Kirsher #define FCRAM_REF_TMR_MAX_SHIFT 16
1284e689cf4aSJeff Kirsher #define FCRAM_REF_TMR_MIN 0x000000000000ffffULL
1285e689cf4aSJeff Kirsher #define FCRAM_REF_TMR_MIN_SHIFT 0
1286e689cf4aSJeff Kirsher
1287e689cf4aSJeff Kirsher #define DEFAULT_FCRAM_REFRESH_MAX 512
1288e689cf4aSJeff Kirsher #define DEFAULT_FCRAM_REFRESH_MIN 512
1289e689cf4aSJeff Kirsher
1290e689cf4aSJeff Kirsher #define FCRAM_FIO_ADDR (FZC_FFLP + 0x20118UL)
1291e689cf4aSJeff Kirsher #define FCRAM_FIO_ADDR_ADDR 0x00000000000000ffULL
1292e689cf4aSJeff Kirsher
1293e689cf4aSJeff Kirsher #define FCRAM_FIO_DAT (FZC_FFLP + 0x20120UL)
1294e689cf4aSJeff Kirsher #define FCRAM_FIO_DAT_DATA 0x000000000000ffffULL
1295e689cf4aSJeff Kirsher
1296e689cf4aSJeff Kirsher #define FCRAM_ERR_TST0 (FZC_FFLP + 0x20128UL)
1297e689cf4aSJeff Kirsher #define FCRAM_ERR_TST0_SYND 0x00000000000000ffULL
1298e689cf4aSJeff Kirsher
1299e689cf4aSJeff Kirsher #define FCRAM_ERR_TST1 (FZC_FFLP + 0x20130UL)
1300e689cf4aSJeff Kirsher #define FCRAM_ERR_TST1_DAT 0x00000000ffffffffULL
1301e689cf4aSJeff Kirsher
1302e689cf4aSJeff Kirsher #define FCRAM_ERR_TST2 (FZC_FFLP + 0x20138UL)
1303e689cf4aSJeff Kirsher #define FCRAM_ERR_TST2_DAT 0x00000000ffffffffULL
1304e689cf4aSJeff Kirsher
1305e689cf4aSJeff Kirsher #define FFLP_ERR_MASK (FZC_FFLP + 0x20140UL)
1306e689cf4aSJeff Kirsher #define FFLP_ERR_MASK_HSH_TBL_DAT 0x00000000000007f8ULL
1307e689cf4aSJeff Kirsher #define FFLP_ERR_MASK_HSH_TBL_LKUP 0x0000000000000004ULL
1308e689cf4aSJeff Kirsher #define FFLP_ERR_MASK_TCAM 0x0000000000000002ULL
1309e689cf4aSJeff Kirsher #define FFLP_ERR_MASK_VLAN 0x0000000000000001ULL
1310e689cf4aSJeff Kirsher
1311e689cf4aSJeff Kirsher #define FFLP_DBG_TRAIN_VCT (FZC_FFLP + 0x20148UL)
1312e689cf4aSJeff Kirsher #define FFLP_DBG_TRAIN_VCT_VECTOR 0x00000000ffffffffULL
1313e689cf4aSJeff Kirsher
1314e689cf4aSJeff Kirsher #define FCRAM_PHY_RD_LAT (FZC_FFLP + 0x20150UL)
1315e689cf4aSJeff Kirsher #define FCRAM_PHY_RD_LAT_LAT 0x00000000000000ffULL
1316e689cf4aSJeff Kirsher
1317e689cf4aSJeff Kirsher /* Ethernet TCAM format */
1318e689cf4aSJeff Kirsher #define TCAM_ETHKEY0_RESV1 0xffffffffffffff00ULL
1319e689cf4aSJeff Kirsher #define TCAM_ETHKEY0_CLASS_CODE 0x00000000000000f8ULL
1320e689cf4aSJeff Kirsher #define TCAM_ETHKEY0_CLASS_CODE_SHIFT 3
1321e689cf4aSJeff Kirsher #define TCAM_ETHKEY0_RESV2 0x0000000000000007ULL
1322e689cf4aSJeff Kirsher #define TCAM_ETHKEY1_FRAME_BYTE0_7(NUM) (0xff << ((7 - NUM) * 8))
1323e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE8 0xff00000000000000ULL
1324e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE8_SHIFT 56
1325e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE9 0x00ff000000000000ULL
1326e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE9_SHIFT 48
1327e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE10 0x0000ff0000000000ULL
1328e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_BYTE10_SHIFT 40
1329e689cf4aSJeff Kirsher #define TCAM_ETHKEY2_FRAME_RESV 0x000000ffffffffffULL
1330e689cf4aSJeff Kirsher #define TCAM_ETHKEY3_FRAME_RESV 0xffffffffffffffffULL
1331e689cf4aSJeff Kirsher
1332e689cf4aSJeff Kirsher /* IPV4 TCAM format */
1333e689cf4aSJeff Kirsher #define TCAM_V4KEY0_RESV1 0xffffffffffffff00ULL
1334e689cf4aSJeff Kirsher #define TCAM_V4KEY0_CLASS_CODE 0x00000000000000f8ULL
1335e689cf4aSJeff Kirsher #define TCAM_V4KEY0_CLASS_CODE_SHIFT 3
1336e689cf4aSJeff Kirsher #define TCAM_V4KEY0_RESV2 0x0000000000000007ULL
1337e689cf4aSJeff Kirsher #define TCAM_V4KEY1_L2RDCNUM 0xf800000000000000ULL
1338e689cf4aSJeff Kirsher #define TCAM_V4KEY1_L2RDCNUM_SHIFT 59
1339e689cf4aSJeff Kirsher #define TCAM_V4KEY1_NOPORT 0x0400000000000000ULL
1340e689cf4aSJeff Kirsher #define TCAM_V4KEY1_RESV 0x03ffffffffffffffULL
1341e689cf4aSJeff Kirsher #define TCAM_V4KEY2_RESV 0xffff000000000000ULL
1342e689cf4aSJeff Kirsher #define TCAM_V4KEY2_TOS 0x0000ff0000000000ULL
1343e689cf4aSJeff Kirsher #define TCAM_V4KEY2_TOS_SHIFT 40
1344e689cf4aSJeff Kirsher #define TCAM_V4KEY2_PROTO 0x000000ff00000000ULL
1345e689cf4aSJeff Kirsher #define TCAM_V4KEY2_PROTO_SHIFT 32
1346e689cf4aSJeff Kirsher #define TCAM_V4KEY2_PORT_SPI 0x00000000ffffffffULL
1347e689cf4aSJeff Kirsher #define TCAM_V4KEY2_PORT_SPI_SHIFT 0
1348e689cf4aSJeff Kirsher #define TCAM_V4KEY3_SADDR 0xffffffff00000000ULL
1349e689cf4aSJeff Kirsher #define TCAM_V4KEY3_SADDR_SHIFT 32
1350e689cf4aSJeff Kirsher #define TCAM_V4KEY3_DADDR 0x00000000ffffffffULL
1351e689cf4aSJeff Kirsher #define TCAM_V4KEY3_DADDR_SHIFT 0
1352e689cf4aSJeff Kirsher
1353e689cf4aSJeff Kirsher /* IPV6 TCAM format */
1354e689cf4aSJeff Kirsher #define TCAM_V6KEY0_RESV1 0xffffffffffffff00ULL
1355e689cf4aSJeff Kirsher #define TCAM_V6KEY0_CLASS_CODE 0x00000000000000f8ULL
1356e689cf4aSJeff Kirsher #define TCAM_V6KEY0_CLASS_CODE_SHIFT 3
1357e689cf4aSJeff Kirsher #define TCAM_V6KEY0_RESV2 0x0000000000000007ULL
1358e689cf4aSJeff Kirsher #define TCAM_V6KEY1_L2RDCNUM 0xf800000000000000ULL
1359e689cf4aSJeff Kirsher #define TCAM_V6KEY1_L2RDCNUM_SHIFT 59
1360e689cf4aSJeff Kirsher #define TCAM_V6KEY1_NOPORT 0x0400000000000000ULL
1361e689cf4aSJeff Kirsher #define TCAM_V6KEY1_RESV 0x03ff000000000000ULL
1362e689cf4aSJeff Kirsher #define TCAM_V6KEY1_TOS 0x0000ff0000000000ULL
1363e689cf4aSJeff Kirsher #define TCAM_V6KEY1_TOS_SHIFT 40
1364e689cf4aSJeff Kirsher #define TCAM_V6KEY1_NEXT_HDR 0x000000ff00000000ULL
1365e689cf4aSJeff Kirsher #define TCAM_V6KEY1_NEXT_HDR_SHIFT 32
1366e689cf4aSJeff Kirsher #define TCAM_V6KEY1_PORT_SPI 0x00000000ffffffffULL
1367e689cf4aSJeff Kirsher #define TCAM_V6KEY1_PORT_SPI_SHIFT 0
1368e689cf4aSJeff Kirsher #define TCAM_V6KEY2_ADDR_HIGH 0xffffffffffffffffULL
1369e689cf4aSJeff Kirsher #define TCAM_V6KEY3_ADDR_LOW 0xffffffffffffffffULL
1370e689cf4aSJeff Kirsher
1371e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_SYNDROME 0x000003fffc000000ULL
1372e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_SYNDROME_SHIFT 26
1373e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_ZFID 0x0000000003ffc000ULL
1374e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_ZFID_SHIFT 14
1375e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_V4_ECC_OK 0x0000000000002000ULL
1376e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_DISC 0x0000000000001000ULL
1377e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_TRES_MASK 0x0000000000000c00ULL
1378e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_TRES_USE_L2RDC 0x0000000000000000ULL
1379e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_TRES_USE_OFFSET 0x0000000000000400ULL
1380e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_TRES_OVR_RDC 0x0000000000000800ULL
1381e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_TRES_OVR_RDC_OFF 0x0000000000000c00ULL
1382e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_RDCTBL 0x0000000000000380ULL
1383e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_RDCTBL_SHIFT 7
1384e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_OFFSET 0x000000000000007cULL
1385e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_OFFSET_SHIFT 2
1386e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_ZFVLD 0x0000000000000002ULL
1387e689cf4aSJeff Kirsher #define TCAM_ASSOCDATA_AGE 0x0000000000000001ULL
1388e689cf4aSJeff Kirsher
1389e689cf4aSJeff Kirsher #define FLOW_KEY(IDX) (FZC_FFLP + 0x40000UL + (IDX) * 8UL)
1390e689cf4aSJeff Kirsher #define FLOW_KEY_PORT 0x0000000000000200ULL
1391e689cf4aSJeff Kirsher #define FLOW_KEY_L2DA 0x0000000000000100ULL
1392e689cf4aSJeff Kirsher #define FLOW_KEY_VLAN 0x0000000000000080ULL
1393e689cf4aSJeff Kirsher #define FLOW_KEY_IPSA 0x0000000000000040ULL
1394e689cf4aSJeff Kirsher #define FLOW_KEY_IPDA 0x0000000000000020ULL
1395e689cf4aSJeff Kirsher #define FLOW_KEY_PROTO 0x0000000000000010ULL
1396e689cf4aSJeff Kirsher #define FLOW_KEY_L4_0 0x000000000000000cULL
1397e689cf4aSJeff Kirsher #define FLOW_KEY_L4_0_SHIFT 2
1398e689cf4aSJeff Kirsher #define FLOW_KEY_L4_1 0x0000000000000003ULL
1399e689cf4aSJeff Kirsher #define FLOW_KEY_L4_1_SHIFT 0
1400e689cf4aSJeff Kirsher
1401e689cf4aSJeff Kirsher #define FLOW_KEY_L4_NONE 0x0
1402e689cf4aSJeff Kirsher #define FLOW_KEY_L4_RESV 0x1
1403e689cf4aSJeff Kirsher #define FLOW_KEY_L4_BYTE12 0x2
1404e689cf4aSJeff Kirsher #define FLOW_KEY_L4_BYTE56 0x3
1405e689cf4aSJeff Kirsher
1406e689cf4aSJeff Kirsher #define H1POLY (FZC_FFLP + 0x40060UL)
1407e689cf4aSJeff Kirsher #define H1POLY_INITVAL 0x00000000ffffffffULL
1408e689cf4aSJeff Kirsher
1409e689cf4aSJeff Kirsher #define H2POLY (FZC_FFLP + 0x40068UL)
1410e689cf4aSJeff Kirsher #define H2POLY_INITVAL 0x000000000000ffffULL
1411e689cf4aSJeff Kirsher
1412e689cf4aSJeff Kirsher #define FLW_PRT_SEL(IDX) (FZC_FFLP + 0x40070UL + (IDX) * 8UL)
1413e689cf4aSJeff Kirsher #define FLW_PRT_SEL_EXT 0x0000000000010000ULL
1414e689cf4aSJeff Kirsher #define FLW_PRT_SEL_MASK 0x0000000000001f00ULL
1415e689cf4aSJeff Kirsher #define FLW_PRT_SEL_MASK_SHIFT 8
1416e689cf4aSJeff Kirsher #define FLW_PRT_SEL_BASE 0x000000000000001fULL
1417e689cf4aSJeff Kirsher #define FLW_PRT_SEL_BASE_SHIFT 0
1418e689cf4aSJeff Kirsher
1419e689cf4aSJeff Kirsher #define HASH_TBL_ADDR(IDX) (FFLP + 0x00000UL + (IDX) * 8192UL)
1420e689cf4aSJeff Kirsher #define HASH_TBL_ADDR_AUTOINC 0x0000000000800000ULL
1421e689cf4aSJeff Kirsher #define HASH_TBL_ADDR_ADDR 0x00000000007fffffULL
1422e689cf4aSJeff Kirsher
1423e689cf4aSJeff Kirsher #define HASH_TBL_DATA(IDX) (FFLP + 0x00008UL + (IDX) * 8192UL)
1424e689cf4aSJeff Kirsher #define HASH_TBL_DATA_DATA 0xffffffffffffffffULL
1425e689cf4aSJeff Kirsher
1426e689cf4aSJeff Kirsher /* FCRAM hash table entries are up to 8 64-bit words in size.
1427e689cf4aSJeff Kirsher * The layout of each entry is determined by the settings in the
1428e689cf4aSJeff Kirsher * first word, which is the header.
1429e689cf4aSJeff Kirsher *
1430e689cf4aSJeff Kirsher * The indexing is controllable per partition (there is one partition
1431e689cf4aSJeff Kirsher * per RDC group, thus a total of eight) using the BASE and MASK fields
1432e689cf4aSJeff Kirsher * of FLW_PRT_SEL above.
1433e689cf4aSJeff Kirsher */
1434e689cf4aSJeff Kirsher #define FCRAM_SIZE 0x800000
1435e689cf4aSJeff Kirsher #define FCRAM_NUM_PARTITIONS 8
1436e689cf4aSJeff Kirsher
1437e689cf4aSJeff Kirsher /* Generic HASH entry header, used for all non-optimized formats. */
1438e689cf4aSJeff Kirsher #define HASH_HEADER_FMT 0x8000000000000000ULL
1439e689cf4aSJeff Kirsher #define HASH_HEADER_EXT 0x4000000000000000ULL
1440e689cf4aSJeff Kirsher #define HASH_HEADER_VALID 0x2000000000000000ULL
1441e689cf4aSJeff Kirsher #define HASH_HEADER_RESVD 0x1000000000000000ULL
1442e689cf4aSJeff Kirsher #define HASH_HEADER_L2_DADDR 0x0ffffffffffff000ULL
1443e689cf4aSJeff Kirsher #define HASH_HEADER_L2_DADDR_SHIFT 12
1444e689cf4aSJeff Kirsher #define HASH_HEADER_VLAN 0x0000000000000fffULL
1445e689cf4aSJeff Kirsher #define HASH_HEADER_VLAN_SHIFT 0
1446e689cf4aSJeff Kirsher
1447e689cf4aSJeff Kirsher /* Optimized format, just a header with a special layout defined below.
1448e689cf4aSJeff Kirsher * Set FMT and EXT both to zero to indicate this layout is being used.
1449e689cf4aSJeff Kirsher */
1450e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_FMT 0x8000000000000000ULL
1451e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_EXT 0x4000000000000000ULL
1452e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_VALID 0x2000000000000000ULL
1453e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_RDCOFF 0x1f00000000000000ULL
1454e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_RDCOFF_SHIFT 56
1455e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_HASH2 0x00ffff0000000000ULL
1456e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_HASH2_SHIFT 40
1457e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_RESVD 0x000000ff00000000ULL
1458e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_USERINFO 0x00000000ffffffffULL
1459e689cf4aSJeff Kirsher #define HASH_OPT_HEADER_USERINFO_SHIFT 0
1460e689cf4aSJeff Kirsher
1461e689cf4aSJeff Kirsher /* Port and protocol word used for ipv4 and ipv6 layouts. */
1462e689cf4aSJeff Kirsher #define HASH_PORT_DPORT 0xffff000000000000ULL
1463e689cf4aSJeff Kirsher #define HASH_PORT_DPORT_SHIFT 48
1464e689cf4aSJeff Kirsher #define HASH_PORT_SPORT 0x0000ffff00000000ULL
1465e689cf4aSJeff Kirsher #define HASH_PORT_SPORT_SHIFT 32
1466e689cf4aSJeff Kirsher #define HASH_PORT_PROTO 0x00000000ff000000ULL
1467e689cf4aSJeff Kirsher #define HASH_PORT_PROTO_SHIFT 24
1468e689cf4aSJeff Kirsher #define HASH_PORT_PORT_OFF 0x0000000000c00000ULL
1469e689cf4aSJeff Kirsher #define HASH_PORT_PORT_OFF_SHIFT 22
1470e689cf4aSJeff Kirsher #define HASH_PORT_PORT_RESV 0x00000000003fffffULL
1471e689cf4aSJeff Kirsher
1472e689cf4aSJeff Kirsher /* Action word used for ipv4 and ipv6 layouts. */
1473e689cf4aSJeff Kirsher #define HASH_ACTION_RESV1 0xe000000000000000ULL
1474e689cf4aSJeff Kirsher #define HASH_ACTION_RDCOFF 0x1f00000000000000ULL
1475e689cf4aSJeff Kirsher #define HASH_ACTION_RDCOFF_SHIFT 56
1476e689cf4aSJeff Kirsher #define HASH_ACTION_ZFVALID 0x0080000000000000ULL
1477e689cf4aSJeff Kirsher #define HASH_ACTION_RESV2 0x0070000000000000ULL
1478e689cf4aSJeff Kirsher #define HASH_ACTION_ZFID 0x000fff0000000000ULL
1479e689cf4aSJeff Kirsher #define HASH_ACTION_ZFID_SHIFT 40
1480e689cf4aSJeff Kirsher #define HASH_ACTION_RESV3 0x000000ff00000000ULL
1481e689cf4aSJeff Kirsher #define HASH_ACTION_USERINFO 0x00000000ffffffffULL
1482e689cf4aSJeff Kirsher #define HASH_ACTION_USERINFO_SHIFT 0
1483e689cf4aSJeff Kirsher
1484e689cf4aSJeff Kirsher /* IPV4 address word. Addresses are in network endian. */
1485e689cf4aSJeff Kirsher #define HASH_IP4ADDR_SADDR 0xffffffff00000000ULL
1486e689cf4aSJeff Kirsher #define HASH_IP4ADDR_SADDR_SHIFT 32
1487e689cf4aSJeff Kirsher #define HASH_IP4ADDR_DADDR 0x00000000ffffffffULL
1488e689cf4aSJeff Kirsher #define HASH_IP4ADDR_DADDR_SHIFT 0
1489e689cf4aSJeff Kirsher
1490e689cf4aSJeff Kirsher /* IPV6 address layout is 4 words, first two are saddr, next two
1491e689cf4aSJeff Kirsher * are daddr. Addresses are in network endian.
1492e689cf4aSJeff Kirsher */
1493e689cf4aSJeff Kirsher
1494e689cf4aSJeff Kirsher struct fcram_hash_opt {
1495e689cf4aSJeff Kirsher u64 header;
1496e689cf4aSJeff Kirsher };
1497e689cf4aSJeff Kirsher
1498e689cf4aSJeff Kirsher /* EXT=1, FMT=0 */
1499e689cf4aSJeff Kirsher struct fcram_hash_ipv4 {
1500e689cf4aSJeff Kirsher u64 header;
1501e689cf4aSJeff Kirsher u64 addrs;
1502e689cf4aSJeff Kirsher u64 ports;
1503e689cf4aSJeff Kirsher u64 action;
1504e689cf4aSJeff Kirsher };
1505e689cf4aSJeff Kirsher
1506e689cf4aSJeff Kirsher /* EXT=1, FMT=1 */
1507e689cf4aSJeff Kirsher struct fcram_hash_ipv6 {
1508e689cf4aSJeff Kirsher u64 header;
1509e689cf4aSJeff Kirsher u64 addrs[4];
1510e689cf4aSJeff Kirsher u64 ports;
1511e689cf4aSJeff Kirsher u64 action;
1512e689cf4aSJeff Kirsher };
1513e689cf4aSJeff Kirsher
1514e689cf4aSJeff Kirsher #define HASH_TBL_DATA_LOG(IDX) (FFLP + 0x00010UL + (IDX) * 8192UL)
1515e689cf4aSJeff Kirsher #define HASH_TBL_DATA_LOG_ERR 0x0000000080000000ULL
1516e689cf4aSJeff Kirsher #define HASH_TBL_DATA_LOG_ADDR 0x000000007fffff00ULL
1517e689cf4aSJeff Kirsher #define HASH_TBL_DATA_LOG_SYNDROME 0x00000000000000ffULL
1518e689cf4aSJeff Kirsher
1519e689cf4aSJeff Kirsher #define RX_DMA_CK_DIV (FZC_DMC + 0x00000UL)
1520e689cf4aSJeff Kirsher #define RX_DMA_CK_DIV_CNT 0x000000000000ffffULL
1521e689cf4aSJeff Kirsher
1522e689cf4aSJeff Kirsher #define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
1523e689cf4aSJeff Kirsher #define DEF_RDC_VAL 0x000000000000001fULL
1524e689cf4aSJeff Kirsher
1525e689cf4aSJeff Kirsher #define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
1526e689cf4aSJeff Kirsher #define PT_DRR_WT_VAL 0x000000000000ffffULL
1527e689cf4aSJeff Kirsher
1528e689cf4aSJeff Kirsher #define PT_DRR_WEIGHT_DEFAULT_10G 0x0400
1529e689cf4aSJeff Kirsher #define PT_DRR_WEIGHT_DEFAULT_1G 0x0066
1530e689cf4aSJeff Kirsher
1531e689cf4aSJeff Kirsher #define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
1532e689cf4aSJeff Kirsher #define PT_USE_CNT 0x00000000000fffffULL
1533e689cf4aSJeff Kirsher
1534e689cf4aSJeff Kirsher #define RED_RAN_INIT (FZC_DMC + 0x00068UL)
1535e689cf4aSJeff Kirsher #define RED_RAN_INIT_OPMODE 0x0000000000010000ULL
1536e689cf4aSJeff Kirsher #define RED_RAN_INIT_VAL 0x000000000000ffffULL
1537e689cf4aSJeff Kirsher
1538e689cf4aSJeff Kirsher #define RX_ADDR_MD (FZC_DMC + 0x00070UL)
1539e689cf4aSJeff Kirsher #define RX_ADDR_MD_DBG_PT_MUX_SEL 0x000000000000000cULL
1540e689cf4aSJeff Kirsher #define RX_ADDR_MD_RAM_ACC 0x0000000000000002ULL
1541e689cf4aSJeff Kirsher #define RX_ADDR_MD_MODE32 0x0000000000000001ULL
1542e689cf4aSJeff Kirsher
1543e689cf4aSJeff Kirsher #define RDMC_PRE_PAR_ERR (FZC_DMC + 0x00078UL)
1544e689cf4aSJeff Kirsher #define RDMC_PRE_PAR_ERR_ERR 0x0000000000008000ULL
1545e689cf4aSJeff Kirsher #define RDMC_PRE_PAR_ERR_MERR 0x0000000000004000ULL
1546e689cf4aSJeff Kirsher #define RDMC_PRE_PAR_ERR_ADDR 0x00000000000000ffULL
1547e689cf4aSJeff Kirsher
1548e689cf4aSJeff Kirsher #define RDMC_SHA_PAR_ERR (FZC_DMC + 0x00080UL)
1549e689cf4aSJeff Kirsher #define RDMC_SHA_PAR_ERR_ERR 0x0000000000008000ULL
1550e689cf4aSJeff Kirsher #define RDMC_SHA_PAR_ERR_MERR 0x0000000000004000ULL
1551e689cf4aSJeff Kirsher #define RDMC_SHA_PAR_ERR_ADDR 0x00000000000000ffULL
1552e689cf4aSJeff Kirsher
1553e689cf4aSJeff Kirsher #define RDMC_MEM_ADDR (FZC_DMC + 0x00088UL)
1554e689cf4aSJeff Kirsher #define RDMC_MEM_ADDR_PRE_SHAD 0x0000000000000100ULL
1555e689cf4aSJeff Kirsher #define RDMC_MEM_ADDR_ADDR 0x00000000000000ffULL
1556e689cf4aSJeff Kirsher
1557e689cf4aSJeff Kirsher #define RDMC_MEM_DAT0 (FZC_DMC + 0x00090UL)
1558e689cf4aSJeff Kirsher #define RDMC_MEM_DAT0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1559e689cf4aSJeff Kirsher
1560e689cf4aSJeff Kirsher #define RDMC_MEM_DAT1 (FZC_DMC + 0x00098UL)
1561e689cf4aSJeff Kirsher #define RDMC_MEM_DAT1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1562e689cf4aSJeff Kirsher
1563e689cf4aSJeff Kirsher #define RDMC_MEM_DAT2 (FZC_DMC + 0x000a0UL)
1564e689cf4aSJeff Kirsher #define RDMC_MEM_DAT2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1565e689cf4aSJeff Kirsher
1566e689cf4aSJeff Kirsher #define RDMC_MEM_DAT3 (FZC_DMC + 0x000a8UL)
1567e689cf4aSJeff Kirsher #define RDMC_MEM_DAT3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1568e689cf4aSJeff Kirsher
1569e689cf4aSJeff Kirsher #define RDMC_MEM_DAT4 (FZC_DMC + 0x000b0UL)
1570e689cf4aSJeff Kirsher #define RDMC_MEM_DAT4_DATA 0x00000000000fffffULL /* bits 147:128 */
1571e689cf4aSJeff Kirsher
1572e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT (FZC_DMC + 0x000b8UL)
1573e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_ID_MISMATCH 0x0000000000000100ULL
1574e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR 0x00000000000000f0ULL
1575e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR 0x000000000000000fULL
1576e689cf4aSJeff Kirsher
1577e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_MASK (FZC_DMC + 0x000c0UL)
1578e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_MASK_ID_MISMATCH 0x0000000000000100ULL
1579e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR 0x00000000000000f0ULL
1580e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR 0x000000000000000fULL
1581e689cf4aSJeff Kirsher
1582e689cf4aSJeff Kirsher #define RDMC_TRAINING_VECTOR (FZC_DMC + 0x000c8UL)
1583e689cf4aSJeff Kirsher #define RDMC_TRAINING_VECTOR_TRAINING_VECTOR 0x00000000ffffffffULL
1584e689cf4aSJeff Kirsher
1585e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_DBG (FZC_DMC + 0x000d0UL)
1586e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH 0x0000000000000100ULL
1587e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR 0x00000000000000f0ULL
1588e689cf4aSJeff Kirsher #define RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR 0x000000000000000fULL
1589e689cf4aSJeff Kirsher
1590e689cf4aSJeff Kirsher #define RDC_TBL(TBL,SLOT) (FZC_ZCP + 0x10000UL + \
1591e689cf4aSJeff Kirsher (TBL) * (8UL * 16UL) + \
1592e689cf4aSJeff Kirsher (SLOT) * 8UL)
1593e689cf4aSJeff Kirsher #define RDC_TBL_RDC 0x000000000000000fULL
1594e689cf4aSJeff Kirsher
1595e689cf4aSJeff Kirsher #define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
1596e689cf4aSJeff Kirsher #define RX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
1597e689cf4aSJeff Kirsher #define RX_LOG_PAGE_VLD_FUNC_SHIFT 2
1598e689cf4aSJeff Kirsher #define RX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
1599e689cf4aSJeff Kirsher #define RX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
1600e689cf4aSJeff Kirsher
1601e689cf4aSJeff Kirsher #define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
1602e689cf4aSJeff Kirsher #define RX_LOG_MASK1_MASK 0x00000000ffffffffULL
1603e689cf4aSJeff Kirsher
1604e689cf4aSJeff Kirsher #define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
1605e689cf4aSJeff Kirsher #define RX_LOG_VAL1_VALUE 0x00000000ffffffffULL
1606e689cf4aSJeff Kirsher
1607e689cf4aSJeff Kirsher #define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
1608e689cf4aSJeff Kirsher #define RX_LOG_MASK2_MASK 0x00000000ffffffffULL
1609e689cf4aSJeff Kirsher
1610e689cf4aSJeff Kirsher #define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
1611e689cf4aSJeff Kirsher #define RX_LOG_VAL2_VALUE 0x00000000ffffffffULL
1612e689cf4aSJeff Kirsher
1613e689cf4aSJeff Kirsher #define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
1614e689cf4aSJeff Kirsher #define RX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
1615e689cf4aSJeff Kirsher
1616e689cf4aSJeff Kirsher #define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
1617e689cf4aSJeff Kirsher #define RX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
1618e689cf4aSJeff Kirsher
1619e689cf4aSJeff Kirsher #define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
1620e689cf4aSJeff Kirsher #define RX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
1621e689cf4aSJeff Kirsher
1622e689cf4aSJeff Kirsher #define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
1623e689cf4aSJeff Kirsher #define TX_LOG_PAGE_VLD_FUNC 0x000000000000000cULL
1624e689cf4aSJeff Kirsher #define TX_LOG_PAGE_VLD_FUNC_SHIFT 2
1625e689cf4aSJeff Kirsher #define TX_LOG_PAGE_VLD_PAGE1 0x0000000000000002ULL
1626e689cf4aSJeff Kirsher #define TX_LOG_PAGE_VLD_PAGE0 0x0000000000000001ULL
1627e689cf4aSJeff Kirsher
1628e689cf4aSJeff Kirsher #define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
1629e689cf4aSJeff Kirsher #define TX_LOG_MASK1_MASK 0x00000000ffffffffULL
1630e689cf4aSJeff Kirsher
1631e689cf4aSJeff Kirsher #define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
1632e689cf4aSJeff Kirsher #define TX_LOG_VAL1_VALUE 0x00000000ffffffffULL
1633e689cf4aSJeff Kirsher
1634e689cf4aSJeff Kirsher #define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
1635e689cf4aSJeff Kirsher #define TX_LOG_MASK2_MASK 0x00000000ffffffffULL
1636e689cf4aSJeff Kirsher
1637e689cf4aSJeff Kirsher #define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
1638e689cf4aSJeff Kirsher #define TX_LOG_VAL2_VALUE 0x00000000ffffffffULL
1639e689cf4aSJeff Kirsher
1640e689cf4aSJeff Kirsher #define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
1641e689cf4aSJeff Kirsher #define TX_LOG_PAGE_RELO1_RELO 0x00000000ffffffffULL
1642e689cf4aSJeff Kirsher
1643e689cf4aSJeff Kirsher #define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
1644e689cf4aSJeff Kirsher #define TX_LOG_PAGE_RELO2_RELO 0x00000000ffffffffULL
1645e689cf4aSJeff Kirsher
1646e689cf4aSJeff Kirsher #define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
1647e689cf4aSJeff Kirsher #define TX_LOG_PAGE_HDL_HANDLE 0x00000000000fffffULL
1648e689cf4aSJeff Kirsher
1649e689cf4aSJeff Kirsher #define TX_ADDR_MD (FZC_DMC + 0x45000UL)
1650e689cf4aSJeff Kirsher #define TX_ADDR_MD_MODE32 0x0000000000000001ULL
1651e689cf4aSJeff Kirsher
1652e689cf4aSJeff Kirsher #define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
1653e689cf4aSJeff Kirsher #define RDC_RED_PARA_THRE_SYN 0x00000000fff00000ULL
1654e689cf4aSJeff Kirsher #define RDC_RED_PARA_THRE_SYN_SHIFT 20
1655e689cf4aSJeff Kirsher #define RDC_RED_PARA_WIN_SYN 0x00000000000f0000ULL
1656e689cf4aSJeff Kirsher #define RDC_RED_PARA_WIN_SYN_SHIFT 16
1657e689cf4aSJeff Kirsher #define RDC_RED_PARA_THRE 0x000000000000fff0ULL
1658e689cf4aSJeff Kirsher #define RDC_RED_PARA_THRE_SHIFT 4
1659e689cf4aSJeff Kirsher #define RDC_RED_PARA_WIN 0x000000000000000fULL
1660e689cf4aSJeff Kirsher #define RDC_RED_PARA_WIN_SHIFT 0
1661e689cf4aSJeff Kirsher
1662e689cf4aSJeff Kirsher #define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)
1663e689cf4aSJeff Kirsher #define RED_DIS_CNT_OFLOW 0x0000000000010000ULL
1664e689cf4aSJeff Kirsher #define RED_DIS_CNT_COUNT 0x000000000000ffffULL
1665e689cf4aSJeff Kirsher
1666e689cf4aSJeff Kirsher #define IPP_CFIG (FZC_IPP + 0x00000UL)
1667e689cf4aSJeff Kirsher #define IPP_CFIG_SOFT_RST 0x0000000080000000ULL
1668e689cf4aSJeff Kirsher #define IPP_CFIG_IP_MAX_PKT 0x0000000001ffff00ULL
1669e689cf4aSJeff Kirsher #define IPP_CFIG_IP_MAX_PKT_SHIFT 8
1670e689cf4aSJeff Kirsher #define IPP_CFIG_FFLP_CS_PIO_W 0x0000000000000080ULL
1671e689cf4aSJeff Kirsher #define IPP_CFIG_PFIFO_PIO_W 0x0000000000000040ULL
1672e689cf4aSJeff Kirsher #define IPP_CFIG_DFIFO_PIO_W 0x0000000000000020ULL
1673e689cf4aSJeff Kirsher #define IPP_CFIG_CKSUM_EN 0x0000000000000010ULL
1674e689cf4aSJeff Kirsher #define IPP_CFIG_DROP_BAD_CRC 0x0000000000000008ULL
1675e689cf4aSJeff Kirsher #define IPP_CFIG_DFIFO_ECC_EN 0x0000000000000004ULL
1676e689cf4aSJeff Kirsher #define IPP_CFIG_DEBUG_BUS_OUT_EN 0x0000000000000002ULL
1677e689cf4aSJeff Kirsher #define IPP_CFIG_IPP_ENABLE 0x0000000000000001ULL
1678e689cf4aSJeff Kirsher
1679e689cf4aSJeff Kirsher #define IPP_PKT_DIS (FZC_IPP + 0x00020UL)
1680e689cf4aSJeff Kirsher #define IPP_PKT_DIS_COUNT 0x0000000000003fffULL
1681e689cf4aSJeff Kirsher
1682e689cf4aSJeff Kirsher #define IPP_BAD_CS_CNT (FZC_IPP + 0x00028UL)
1683e689cf4aSJeff Kirsher #define IPP_BAD_CS_CNT_COUNT 0x0000000000003fffULL
1684e689cf4aSJeff Kirsher
1685e689cf4aSJeff Kirsher #define IPP_ECC (FZC_IPP + 0x00030UL)
1686e689cf4aSJeff Kirsher #define IPP_ECC_COUNT 0x00000000000000ffULL
1687e689cf4aSJeff Kirsher
1688e689cf4aSJeff Kirsher #define IPP_INT_STAT (FZC_IPP + 0x00040UL)
1689e689cf4aSJeff Kirsher #define IPP_INT_STAT_SOP_MISS 0x0000000080000000ULL
1690e689cf4aSJeff Kirsher #define IPP_INT_STAT_EOP_MISS 0x0000000040000000ULL
1691e689cf4aSJeff Kirsher #define IPP_INT_STAT_DFIFO_UE 0x0000000030000000ULL
1692e689cf4aSJeff Kirsher #define IPP_INT_STAT_DFIFO_CE 0x000000000c000000ULL
1693e689cf4aSJeff Kirsher #define IPP_INT_STAT_DFIFO_ECC 0x0000000003000000ULL
1694e689cf4aSJeff Kirsher #define IPP_INT_STAT_DFIFO_ECC_IDX 0x00000000007ff000ULL
1695e689cf4aSJeff Kirsher #define IPP_INT_STAT_PFIFO_PERR 0x0000000000000800ULL
1696e689cf4aSJeff Kirsher #define IPP_INT_STAT_ECC_ERR_MAX 0x0000000000000400ULL
1697e689cf4aSJeff Kirsher #define IPP_INT_STAT_PFIFO_ERR_IDX 0x00000000000003f0ULL
1698e689cf4aSJeff Kirsher #define IPP_INT_STAT_PFIFO_OVER 0x0000000000000008ULL
1699e689cf4aSJeff Kirsher #define IPP_INT_STAT_PFIFO_UND 0x0000000000000004ULL
1700e689cf4aSJeff Kirsher #define IPP_INT_STAT_BAD_CS_MX 0x0000000000000002ULL
1701e689cf4aSJeff Kirsher #define IPP_INT_STAT_PKT_DIS_MX 0x0000000000000001ULL
1702e689cf4aSJeff Kirsher #define IPP_INT_STAT_ALL 0x00000000ff7fffffULL
1703e689cf4aSJeff Kirsher
1704e689cf4aSJeff Kirsher #define IPP_MSK (FZC_IPP + 0x00048UL)
1705e689cf4aSJeff Kirsher #define IPP_MSK_ECC_ERR_MX 0x0000000000000080ULL
1706e689cf4aSJeff Kirsher #define IPP_MSK_DFIFO_EOP_SOP 0x0000000000000040ULL
1707e689cf4aSJeff Kirsher #define IPP_MSK_DFIFO_UC 0x0000000000000020ULL
1708e689cf4aSJeff Kirsher #define IPP_MSK_PFIFO_PAR 0x0000000000000010ULL
1709e689cf4aSJeff Kirsher #define IPP_MSK_PFIFO_OVER 0x0000000000000008ULL
1710e689cf4aSJeff Kirsher #define IPP_MSK_PFIFO_UND 0x0000000000000004ULL
1711e689cf4aSJeff Kirsher #define IPP_MSK_BAD_CS 0x0000000000000002ULL
1712e689cf4aSJeff Kirsher #define IPP_MSK_PKT_DIS_CNT 0x0000000000000001ULL
1713e689cf4aSJeff Kirsher #define IPP_MSK_ALL 0x00000000000000ffULL
1714e689cf4aSJeff Kirsher
1715e689cf4aSJeff Kirsher #define IPP_PFIFO_RD0 (FZC_IPP + 0x00060UL)
1716e689cf4aSJeff Kirsher #define IPP_PFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1717e689cf4aSJeff Kirsher
1718e689cf4aSJeff Kirsher #define IPP_PFIFO_RD1 (FZC_IPP + 0x00068UL)
1719e689cf4aSJeff Kirsher #define IPP_PFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1720e689cf4aSJeff Kirsher
1721e689cf4aSJeff Kirsher #define IPP_PFIFO_RD2 (FZC_IPP + 0x00070UL)
1722e689cf4aSJeff Kirsher #define IPP_PFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1723e689cf4aSJeff Kirsher
1724e689cf4aSJeff Kirsher #define IPP_PFIFO_RD3 (FZC_IPP + 0x00078UL)
1725e689cf4aSJeff Kirsher #define IPP_PFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1726e689cf4aSJeff Kirsher
1727e689cf4aSJeff Kirsher #define IPP_PFIFO_RD4 (FZC_IPP + 0x00080UL)
1728e689cf4aSJeff Kirsher #define IPP_PFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1729e689cf4aSJeff Kirsher
1730e689cf4aSJeff Kirsher #define IPP_PFIFO_WR0 (FZC_IPP + 0x00088UL)
1731e689cf4aSJeff Kirsher #define IPP_PFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1732e689cf4aSJeff Kirsher
1733e689cf4aSJeff Kirsher #define IPP_PFIFO_WR1 (FZC_IPP + 0x00090UL)
1734e689cf4aSJeff Kirsher #define IPP_PFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1735e689cf4aSJeff Kirsher
1736e689cf4aSJeff Kirsher #define IPP_PFIFO_WR2 (FZC_IPP + 0x00098UL)
1737e689cf4aSJeff Kirsher #define IPP_PFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1738e689cf4aSJeff Kirsher
1739e689cf4aSJeff Kirsher #define IPP_PFIFO_WR3 (FZC_IPP + 0x000a0UL)
1740e689cf4aSJeff Kirsher #define IPP_PFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1741e689cf4aSJeff Kirsher
1742e689cf4aSJeff Kirsher #define IPP_PFIFO_WR4 (FZC_IPP + 0x000a8UL)
1743e689cf4aSJeff Kirsher #define IPP_PFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1744e689cf4aSJeff Kirsher
1745e689cf4aSJeff Kirsher #define IPP_PFIFO_RD_PTR (FZC_IPP + 0x000b0UL)
1746e689cf4aSJeff Kirsher #define IPP_PFIFO_RD_PTR_PTR 0x000000000000003fULL
1747e689cf4aSJeff Kirsher
1748e689cf4aSJeff Kirsher #define IPP_PFIFO_WR_PTR (FZC_IPP + 0x000b8UL)
1749e689cf4aSJeff Kirsher #define IPP_PFIFO_WR_PTR_PTR 0x000000000000007fULL
1750e689cf4aSJeff Kirsher
1751e689cf4aSJeff Kirsher #define IPP_DFIFO_RD0 (FZC_IPP + 0x000c0UL)
1752e689cf4aSJeff Kirsher #define IPP_DFIFO_RD0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1753e689cf4aSJeff Kirsher
1754e689cf4aSJeff Kirsher #define IPP_DFIFO_RD1 (FZC_IPP + 0x000c8UL)
1755e689cf4aSJeff Kirsher #define IPP_DFIFO_RD1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1756e689cf4aSJeff Kirsher
1757e689cf4aSJeff Kirsher #define IPP_DFIFO_RD2 (FZC_IPP + 0x000d0UL)
1758e689cf4aSJeff Kirsher #define IPP_DFIFO_RD2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1759e689cf4aSJeff Kirsher
1760e689cf4aSJeff Kirsher #define IPP_DFIFO_RD3 (FZC_IPP + 0x000d8UL)
1761e689cf4aSJeff Kirsher #define IPP_DFIFO_RD3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1762e689cf4aSJeff Kirsher
1763e689cf4aSJeff Kirsher #define IPP_DFIFO_RD4 (FZC_IPP + 0x000e0UL)
1764e689cf4aSJeff Kirsher #define IPP_DFIFO_RD4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1765e689cf4aSJeff Kirsher
1766e689cf4aSJeff Kirsher #define IPP_DFIFO_WR0 (FZC_IPP + 0x000e8UL)
1767e689cf4aSJeff Kirsher #define IPP_DFIFO_WR0_DATA 0x00000000ffffffffULL /* bits 31:0 */
1768e689cf4aSJeff Kirsher
1769e689cf4aSJeff Kirsher #define IPP_DFIFO_WR1 (FZC_IPP + 0x000f0UL)
1770e689cf4aSJeff Kirsher #define IPP_DFIFO_WR1_DATA 0x00000000ffffffffULL /* bits 63:32 */
1771e689cf4aSJeff Kirsher
1772e689cf4aSJeff Kirsher #define IPP_DFIFO_WR2 (FZC_IPP + 0x000f8UL)
1773e689cf4aSJeff Kirsher #define IPP_DFIFO_WR2_DATA 0x00000000ffffffffULL /* bits 95:64 */
1774e689cf4aSJeff Kirsher
1775e689cf4aSJeff Kirsher #define IPP_DFIFO_WR3 (FZC_IPP + 0x00100UL)
1776e689cf4aSJeff Kirsher #define IPP_DFIFO_WR3_DATA 0x00000000ffffffffULL /* bits 127:96 */
1777e689cf4aSJeff Kirsher
1778e689cf4aSJeff Kirsher #define IPP_DFIFO_WR4 (FZC_IPP + 0x00108UL)
1779e689cf4aSJeff Kirsher #define IPP_DFIFO_WR4_DATA 0x00000000ffffffffULL /* bits 145:128 */
1780e689cf4aSJeff Kirsher
1781e689cf4aSJeff Kirsher #define IPP_DFIFO_RD_PTR (FZC_IPP + 0x00110UL)
1782e689cf4aSJeff Kirsher #define IPP_DFIFO_RD_PTR_PTR 0x0000000000000fffULL
1783e689cf4aSJeff Kirsher
1784e689cf4aSJeff Kirsher #define IPP_DFIFO_WR_PTR (FZC_IPP + 0x00118UL)
1785e689cf4aSJeff Kirsher #define IPP_DFIFO_WR_PTR_PTR 0x0000000000000fffULL
1786e689cf4aSJeff Kirsher
1787e689cf4aSJeff Kirsher #define IPP_SM (FZC_IPP + 0x00120UL)
1788e689cf4aSJeff Kirsher #define IPP_SM_SM 0x00000000ffffffffULL
1789e689cf4aSJeff Kirsher
1790e689cf4aSJeff Kirsher #define IPP_CS_STAT (FZC_IPP + 0x00128UL)
1791e689cf4aSJeff Kirsher #define IPP_CS_STAT_BCYC_CNT 0x00000000ff000000ULL
1792e689cf4aSJeff Kirsher #define IPP_CS_STAT_IP_LEN 0x0000000000fff000ULL
1793e689cf4aSJeff Kirsher #define IPP_CS_STAT_CS_FAIL 0x0000000000000800ULL
1794e689cf4aSJeff Kirsher #define IPP_CS_STAT_TERM 0x0000000000000400ULL
1795e689cf4aSJeff Kirsher #define IPP_CS_STAT_BAD_NUM 0x0000000000000200ULL
1796e689cf4aSJeff Kirsher #define IPP_CS_STAT_CS_STATE 0x00000000000001ffULL
1797e689cf4aSJeff Kirsher
1798e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO (FZC_IPP + 0x00130UL)
1799e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO_PKT_ID 0x0000000000003c00ULL
1800e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO_L4_PROTO 0x0000000000000300ULL
1801e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO_V4_HD_LEN 0x00000000000000f0ULL
1802e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO_L3_VER 0x000000000000000cULL
1803e689cf4aSJeff Kirsher #define IPP_FFLP_CS_INFO_L2_OP 0x0000000000000003ULL
1804e689cf4aSJeff Kirsher
1805e689cf4aSJeff Kirsher #define IPP_DBG_SEL (FZC_IPP + 0x00138UL)
1806e689cf4aSJeff Kirsher #define IPP_DBG_SEL_SEL 0x000000000000000fULL
1807e689cf4aSJeff Kirsher
1808e689cf4aSJeff Kirsher #define IPP_DFIFO_ECC_SYND (FZC_IPP + 0x00140UL)
1809e689cf4aSJeff Kirsher #define IPP_DFIFO_ECC_SYND_SYND 0x000000000000ffffULL
1810e689cf4aSJeff Kirsher
1811e689cf4aSJeff Kirsher #define IPP_DFIFO_EOP_RD_PTR (FZC_IPP + 0x00148UL)
1812e689cf4aSJeff Kirsher #define IPP_DFIFO_EOP_RD_PTR_PTR 0x0000000000000fffULL
1813e689cf4aSJeff Kirsher
1814e689cf4aSJeff Kirsher #define IPP_ECC_CTL (FZC_IPP + 0x00150UL)
1815e689cf4aSJeff Kirsher #define IPP_ECC_CTL_DIS_DBL 0x0000000080000000ULL
1816e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_DBL 0x0000000000020000ULL
1817e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_SNG 0x0000000000010000ULL
1818e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_ALL 0x0000000000000400ULL
1819e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_1 0x0000000000000100ULL
1820e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_LST 0x0000000000000004ULL
1821e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_SND 0x0000000000000002ULL
1822e689cf4aSJeff Kirsher #define IPP_ECC_CTL_COR_FSR 0x0000000000000001ULL
1823e689cf4aSJeff Kirsher
1824e689cf4aSJeff Kirsher #define NIU_DFIFO_ENTRIES 1024
1825e689cf4aSJeff Kirsher #define ATLAS_P0_P1_DFIFO_ENTRIES 2048
1826e689cf4aSJeff Kirsher #define ATLAS_P2_P3_DFIFO_ENTRIES 1024
1827e689cf4aSJeff Kirsher
1828e689cf4aSJeff Kirsher #define ZCP_CFIG (FZC_ZCP + 0x00000UL)
1829e689cf4aSJeff Kirsher #define ZCP_CFIG_ZCP_32BIT_MODE 0x0000000001000000ULL
1830e689cf4aSJeff Kirsher #define ZCP_CFIG_ZCP_DEBUG_SEL 0x0000000000ff0000ULL
1831e689cf4aSJeff Kirsher #define ZCP_CFIG_DMA_TH 0x000000000000ffe0ULL
1832e689cf4aSJeff Kirsher #define ZCP_CFIG_ECC_CHK_DIS 0x0000000000000010ULL
1833e689cf4aSJeff Kirsher #define ZCP_CFIG_PAR_CHK_DIS 0x0000000000000008ULL
1834e689cf4aSJeff Kirsher #define ZCP_CFIG_DIS_BUFF_RSP_IF 0x0000000000000004ULL
1835e689cf4aSJeff Kirsher #define ZCP_CFIG_DIS_BUFF_REQ_IF 0x0000000000000002ULL
1836e689cf4aSJeff Kirsher #define ZCP_CFIG_ZC_ENABLE 0x0000000000000001ULL
1837e689cf4aSJeff Kirsher
1838e689cf4aSJeff Kirsher #define ZCP_INT_STAT (FZC_ZCP + 0x00008UL)
1839e689cf4aSJeff Kirsher #define ZCP_INT_STAT_RRFIFO_UNDERRUN 0x0000000000008000ULL
1840e689cf4aSJeff Kirsher #define ZCP_INT_STAT_RRFIFO_OVERRUN 0x0000000000004000ULL
1841e689cf4aSJeff Kirsher #define ZCP_INT_STAT_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1842e689cf4aSJeff Kirsher #define ZCP_INT_STAT_BUFFER_OVERFLOW 0x0000000000000800ULL
1843e689cf4aSJeff Kirsher #define ZCP_INT_STAT_STAT_TBL_PERR 0x0000000000000400ULL
1844e689cf4aSJeff Kirsher #define ZCP_INT_STAT_DYN_TBL_PERR 0x0000000000000200ULL
1845e689cf4aSJeff Kirsher #define ZCP_INT_STAT_BUF_TBL_PERR 0x0000000000000100ULL
1846e689cf4aSJeff Kirsher #define ZCP_INT_STAT_TT_PROGRAM_ERR 0x0000000000000080ULL
1847e689cf4aSJeff Kirsher #define ZCP_INT_STAT_RSP_TT_INDEX_ERR 0x0000000000000040ULL
1848e689cf4aSJeff Kirsher #define ZCP_INT_STAT_SLV_TT_INDEX_ERR 0x0000000000000020ULL
1849e689cf4aSJeff Kirsher #define ZCP_INT_STAT_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
1850e689cf4aSJeff Kirsher #define ZCP_INT_STAT_CFIFO_ECC3 0x0000000000000008ULL
1851e689cf4aSJeff Kirsher #define ZCP_INT_STAT_CFIFO_ECC2 0x0000000000000004ULL
1852e689cf4aSJeff Kirsher #define ZCP_INT_STAT_CFIFO_ECC1 0x0000000000000002ULL
1853e689cf4aSJeff Kirsher #define ZCP_INT_STAT_CFIFO_ECC0 0x0000000000000001ULL
1854e689cf4aSJeff Kirsher #define ZCP_INT_STAT_ALL 0x000000000000ffffULL
1855e689cf4aSJeff Kirsher
1856e689cf4aSJeff Kirsher #define ZCP_INT_MASK (FZC_ZCP + 0x00010UL)
1857e689cf4aSJeff Kirsher #define ZCP_INT_MASK_RRFIFO_UNDERRUN 0x0000000000008000ULL
1858e689cf4aSJeff Kirsher #define ZCP_INT_MASK_RRFIFO_OVERRUN 0x0000000000004000ULL
1859e689cf4aSJeff Kirsher #define ZCP_INT_MASK_LOJ 0x0000000000002000ULL
1860e689cf4aSJeff Kirsher #define ZCP_INT_MASK_RSPFIFO_UNCOR_ERR 0x0000000000001000ULL
1861e689cf4aSJeff Kirsher #define ZCP_INT_MASK_BUFFER_OVERFLOW 0x0000000000000800ULL
1862e689cf4aSJeff Kirsher #define ZCP_INT_MASK_STAT_TBL_PERR 0x0000000000000400ULL
1863e689cf4aSJeff Kirsher #define ZCP_INT_MASK_DYN_TBL_PERR 0x0000000000000200ULL
1864e689cf4aSJeff Kirsher #define ZCP_INT_MASK_BUF_TBL_PERR 0x0000000000000100ULL
1865e689cf4aSJeff Kirsher #define ZCP_INT_MASK_TT_PROGRAM_ERR 0x0000000000000080ULL
1866e689cf4aSJeff Kirsher #define ZCP_INT_MASK_RSP_TT_INDEX_ERR 0x0000000000000040ULL
1867e689cf4aSJeff Kirsher #define ZCP_INT_MASK_SLV_TT_INDEX_ERR 0x0000000000000020ULL
1868e689cf4aSJeff Kirsher #define ZCP_INT_MASK_ZCP_TT_INDEX_ERR 0x0000000000000010ULL
1869e689cf4aSJeff Kirsher #define ZCP_INT_MASK_CFIFO_ECC3 0x0000000000000008ULL
1870e689cf4aSJeff Kirsher #define ZCP_INT_MASK_CFIFO_ECC2 0x0000000000000004ULL
1871e689cf4aSJeff Kirsher #define ZCP_INT_MASK_CFIFO_ECC1 0x0000000000000002ULL
1872e689cf4aSJeff Kirsher #define ZCP_INT_MASK_CFIFO_ECC0 0x0000000000000001ULL
1873e689cf4aSJeff Kirsher #define ZCP_INT_MASK_ALL 0x000000000000ffffULL
1874e689cf4aSJeff Kirsher
1875e689cf4aSJeff Kirsher #define BAM4BUF (FZC_ZCP + 0x00018UL)
1876e689cf4aSJeff Kirsher #define BAM4BUF_LOJ 0x0000000080000000ULL
1877e689cf4aSJeff Kirsher #define BAM4BUF_EN_CK 0x0000000040000000ULL
1878e689cf4aSJeff Kirsher #define BAM4BUF_IDX_END0 0x000000003ff00000ULL
1879e689cf4aSJeff Kirsher #define BAM4BUF_IDX_ST0 0x00000000000ffc00ULL
1880e689cf4aSJeff Kirsher #define BAM4BUF_OFFSET0 0x00000000000003ffULL
1881e689cf4aSJeff Kirsher
1882e689cf4aSJeff Kirsher #define BAM8BUF (FZC_ZCP + 0x00020UL)
1883e689cf4aSJeff Kirsher #define BAM8BUF_LOJ 0x0000000080000000ULL
1884e689cf4aSJeff Kirsher #define BAM8BUF_EN_CK 0x0000000040000000ULL
1885e689cf4aSJeff Kirsher #define BAM8BUF_IDX_END1 0x000000003ff00000ULL
1886e689cf4aSJeff Kirsher #define BAM8BUF_IDX_ST1 0x00000000000ffc00ULL
1887e689cf4aSJeff Kirsher #define BAM8BUF_OFFSET1 0x00000000000003ffULL
1888e689cf4aSJeff Kirsher
1889e689cf4aSJeff Kirsher #define BAM16BUF (FZC_ZCP + 0x00028UL)
1890e689cf4aSJeff Kirsher #define BAM16BUF_LOJ 0x0000000080000000ULL
1891e689cf4aSJeff Kirsher #define BAM16BUF_EN_CK 0x0000000040000000ULL
1892e689cf4aSJeff Kirsher #define BAM16BUF_IDX_END2 0x000000003ff00000ULL
1893e689cf4aSJeff Kirsher #define BAM16BUF_IDX_ST2 0x00000000000ffc00ULL
1894e689cf4aSJeff Kirsher #define BAM16BUF_OFFSET2 0x00000000000003ffULL
1895e689cf4aSJeff Kirsher
1896e689cf4aSJeff Kirsher #define BAM32BUF (FZC_ZCP + 0x00030UL)
1897e689cf4aSJeff Kirsher #define BAM32BUF_LOJ 0x0000000080000000ULL
1898e689cf4aSJeff Kirsher #define BAM32BUF_EN_CK 0x0000000040000000ULL
1899e689cf4aSJeff Kirsher #define BAM32BUF_IDX_END3 0x000000003ff00000ULL
1900e689cf4aSJeff Kirsher #define BAM32BUF_IDX_ST3 0x00000000000ffc00ULL
1901e689cf4aSJeff Kirsher #define BAM32BUF_OFFSET3 0x00000000000003ffULL
1902e689cf4aSJeff Kirsher
1903e689cf4aSJeff Kirsher #define DST4BUF (FZC_ZCP + 0x00038UL)
1904e689cf4aSJeff Kirsher #define DST4BUF_DS_OFFSET0 0x00000000000003ffULL
1905e689cf4aSJeff Kirsher
1906e689cf4aSJeff Kirsher #define DST8BUF (FZC_ZCP + 0x00040UL)
1907e689cf4aSJeff Kirsher #define DST8BUF_DS_OFFSET1 0x00000000000003ffULL
1908e689cf4aSJeff Kirsher
1909e689cf4aSJeff Kirsher #define DST16BUF (FZC_ZCP + 0x00048UL)
1910e689cf4aSJeff Kirsher #define DST16BUF_DS_OFFSET2 0x00000000000003ffULL
1911e689cf4aSJeff Kirsher
1912e689cf4aSJeff Kirsher #define DST32BUF (FZC_ZCP + 0x00050UL)
1913e689cf4aSJeff Kirsher #define DST32BUF_DS_OFFSET3 0x00000000000003ffULL
1914e689cf4aSJeff Kirsher
1915e689cf4aSJeff Kirsher #define ZCP_RAM_DATA0 (FZC_ZCP + 0x00058UL)
1916e689cf4aSJeff Kirsher #define ZCP_RAM_DATA0_DAT0 0x00000000ffffffffULL
1917e689cf4aSJeff Kirsher
1918e689cf4aSJeff Kirsher #define ZCP_RAM_DATA1 (FZC_ZCP + 0x00060UL)
1919e689cf4aSJeff Kirsher #define ZCP_RAM_DAT10_DAT1 0x00000000ffffffffULL
1920e689cf4aSJeff Kirsher
1921e689cf4aSJeff Kirsher #define ZCP_RAM_DATA2 (FZC_ZCP + 0x00068UL)
1922e689cf4aSJeff Kirsher #define ZCP_RAM_DATA2_DAT2 0x00000000ffffffffULL
1923e689cf4aSJeff Kirsher
1924e689cf4aSJeff Kirsher #define ZCP_RAM_DATA3 (FZC_ZCP + 0x00070UL)
1925e689cf4aSJeff Kirsher #define ZCP_RAM_DATA3_DAT3 0x00000000ffffffffULL
1926e689cf4aSJeff Kirsher
1927e689cf4aSJeff Kirsher #define ZCP_RAM_DATA4 (FZC_ZCP + 0x00078UL)
1928e689cf4aSJeff Kirsher #define ZCP_RAM_DATA4_DAT4 0x00000000000000ffULL
1929e689cf4aSJeff Kirsher
1930e689cf4aSJeff Kirsher #define ZCP_RAM_BE (FZC_ZCP + 0x00080UL)
1931e689cf4aSJeff Kirsher #define ZCP_RAM_BE_VAL 0x000000000001ffffULL
1932e689cf4aSJeff Kirsher
1933e689cf4aSJeff Kirsher #define ZCP_RAM_ACC (FZC_ZCP + 0x00088UL)
1934e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_BUSY 0x0000000080000000ULL
1935e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_READ 0x0000000040000000ULL
1936e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_WRITE 0x0000000000000000ULL
1937e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_LOJ 0x0000000020000000ULL
1938e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_ZFCID 0x000000001ffe0000ULL
1939e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_ZFCID_SHIFT 17
1940e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_RAM_SEL 0x000000000001f000ULL
1941e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_RAM_SEL_SHIFT 12
1942e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_CFIFOADDR 0x0000000000000fffULL
1943e689cf4aSJeff Kirsher #define ZCP_RAM_ACC_CFIFOADDR_SHIFT 0
1944e689cf4aSJeff Kirsher
1945e689cf4aSJeff Kirsher #define ZCP_RAM_SEL_BAM(INDEX) (0x00 + (INDEX))
1946e689cf4aSJeff Kirsher #define ZCP_RAM_SEL_TT_STATIC 0x08
1947e689cf4aSJeff Kirsher #define ZCP_RAM_SEL_TT_DYNAMIC 0x09
1948e689cf4aSJeff Kirsher #define ZCP_RAM_SEL_CFIFO(PORT) (0x10 + (PORT))
1949e689cf4aSJeff Kirsher
1950e689cf4aSJeff Kirsher #define NIU_CFIFO_ENTRIES 1024
1951e689cf4aSJeff Kirsher #define ATLAS_P0_P1_CFIFO_ENTRIES 2048
1952e689cf4aSJeff Kirsher #define ATLAS_P2_P3_CFIFO_ENTRIES 1024
1953e689cf4aSJeff Kirsher
1954e689cf4aSJeff Kirsher #define CHK_BIT_DATA (FZC_ZCP + 0x00090UL)
1955e689cf4aSJeff Kirsher #define CHK_BIT_DATA_DATA 0x000000000000ffffULL
1956e689cf4aSJeff Kirsher
1957e689cf4aSJeff Kirsher #define RESET_CFIFO (FZC_ZCP + 0x00098UL)
1958e689cf4aSJeff Kirsher #define RESET_CFIFO_RST(PORT) (0x1 << (PORT))
1959e689cf4aSJeff Kirsher
1960e689cf4aSJeff Kirsher #define CFIFO_ECC(PORT) (FZC_ZCP + 0x000a0UL + (PORT) * 8UL)
1961e689cf4aSJeff Kirsher #define CFIFO_ECC_DIS_DBLBIT_ERR 0x0000000080000000ULL
1962e689cf4aSJeff Kirsher #define CFIFO_ECC_DBLBIT_ERR 0x0000000000020000ULL
1963e689cf4aSJeff Kirsher #define CFIFO_ECC_SINGLEBIT_ERR 0x0000000000010000ULL
1964e689cf4aSJeff Kirsher #define CFIFO_ECC_ALL_PKT 0x0000000000000400ULL
1965e689cf4aSJeff Kirsher #define CFIFO_ECC_LAST_LINE 0x0000000000000004ULL
1966e689cf4aSJeff Kirsher #define CFIFO_ECC_2ND_LINE 0x0000000000000002ULL
1967e689cf4aSJeff Kirsher #define CFIFO_ECC_1ST_LINE 0x0000000000000001ULL
1968e689cf4aSJeff Kirsher
1969e689cf4aSJeff Kirsher #define ZCP_TRAINING_VECTOR (FZC_ZCP + 0x000c0UL)
1970e689cf4aSJeff Kirsher #define ZCP_TRAINING_VECTOR_VECTOR 0x00000000ffffffffULL
1971e689cf4aSJeff Kirsher
1972e689cf4aSJeff Kirsher #define ZCP_STATE_MACHINE (FZC_ZCP + 0x000c8UL)
1973e689cf4aSJeff Kirsher #define ZCP_STATE_MACHINE_SM 0x00000000ffffffffULL
1974e689cf4aSJeff Kirsher
1975e689cf4aSJeff Kirsher /* Same bits as ZCP_INT_STAT */
1976e689cf4aSJeff Kirsher #define ZCP_INT_STAT_TEST (FZC_ZCP + 0x00108UL)
1977e689cf4aSJeff Kirsher
1978e689cf4aSJeff Kirsher #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1979e689cf4aSJeff Kirsher #define RXDMA_CFIG1_EN 0x0000000080000000ULL
1980e689cf4aSJeff Kirsher #define RXDMA_CFIG1_RST 0x0000000040000000ULL
1981e689cf4aSJeff Kirsher #define RXDMA_CFIG1_QST 0x0000000020000000ULL
1982e689cf4aSJeff Kirsher #define RXDMA_CFIG1_MBADDR_H 0x0000000000000fffULL /* mboxaddr 43:32 */
1983e689cf4aSJeff Kirsher
1984e689cf4aSJeff Kirsher #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1985e689cf4aSJeff Kirsher #define RXDMA_CFIG2_MBADDR_L 0x00000000ffffffc0ULL /* mboxaddr 31:6 */
1986e689cf4aSJeff Kirsher #define RXDMA_CFIG2_OFFSET 0x0000000000000006ULL
1987e689cf4aSJeff Kirsher #define RXDMA_CFIG2_OFFSET_SHIFT 1
1988e689cf4aSJeff Kirsher #define RXDMA_CFIG2_FULL_HDR 0x0000000000000001ULL
1989e689cf4aSJeff Kirsher
1990e689cf4aSJeff Kirsher #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1991e689cf4aSJeff Kirsher #define RBR_CFIG_A_LEN 0xffff000000000000ULL
1992e689cf4aSJeff Kirsher #define RBR_CFIG_A_LEN_SHIFT 48
1993e689cf4aSJeff Kirsher #define RBR_CFIG_A_STADDR_BASE 0x00000ffffffc0000ULL
1994e689cf4aSJeff Kirsher #define RBR_CFIG_A_STADDR 0x000000000003ffc0ULL
1995e689cf4aSJeff Kirsher
1996e689cf4aSJeff Kirsher #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
1997e689cf4aSJeff Kirsher #define RBR_CFIG_B_BLKSIZE 0x0000000003000000ULL
1998e689cf4aSJeff Kirsher #define RBR_CFIG_B_BLKSIZE_SHIFT 24
1999e689cf4aSJeff Kirsher #define RBR_CFIG_B_VLD2 0x0000000000800000ULL
2000e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ2 0x0000000000030000ULL
2001e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ2_SHIFT 16
2002e689cf4aSJeff Kirsher #define RBR_CFIG_B_VLD1 0x0000000000008000ULL
2003e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ1 0x0000000000000300ULL
2004e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ1_SHIFT 8
2005e689cf4aSJeff Kirsher #define RBR_CFIG_B_VLD0 0x0000000000000080ULL
2006e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ0 0x0000000000000003ULL
2007e689cf4aSJeff Kirsher #define RBR_CFIG_B_BUFSZ0_SHIFT 0
2008e689cf4aSJeff Kirsher
2009e689cf4aSJeff Kirsher #define RBR_BLKSIZE_4K 0x0
2010e689cf4aSJeff Kirsher #define RBR_BLKSIZE_8K 0x1
2011e689cf4aSJeff Kirsher #define RBR_BLKSIZE_16K 0x2
2012e689cf4aSJeff Kirsher #define RBR_BLKSIZE_32K 0x3
2013e689cf4aSJeff Kirsher #define RBR_BUFSZ2_2K 0x0
2014e689cf4aSJeff Kirsher #define RBR_BUFSZ2_4K 0x1
2015e689cf4aSJeff Kirsher #define RBR_BUFSZ2_8K 0x2
2016e689cf4aSJeff Kirsher #define RBR_BUFSZ2_16K 0x3
2017e689cf4aSJeff Kirsher #define RBR_BUFSZ1_1K 0x0
2018e689cf4aSJeff Kirsher #define RBR_BUFSZ1_2K 0x1
2019e689cf4aSJeff Kirsher #define RBR_BUFSZ1_4K 0x2
2020e689cf4aSJeff Kirsher #define RBR_BUFSZ1_8K 0x3
2021e689cf4aSJeff Kirsher #define RBR_BUFSZ0_256 0x0
2022e689cf4aSJeff Kirsher #define RBR_BUFSZ0_512 0x1
2023e689cf4aSJeff Kirsher #define RBR_BUFSZ0_1K 0x2
2024e689cf4aSJeff Kirsher #define RBR_BUFSZ0_2K 0x3
2025e689cf4aSJeff Kirsher
2026e689cf4aSJeff Kirsher #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2027e689cf4aSJeff Kirsher #define RBR_KICK_BKADD 0x000000000000ffffULL
2028e689cf4aSJeff Kirsher
2029e689cf4aSJeff Kirsher #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2030e689cf4aSJeff Kirsher #define RBR_STAT_QLEN 0x000000000000ffffULL
2031e689cf4aSJeff Kirsher
2032e689cf4aSJeff Kirsher #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2033e689cf4aSJeff Kirsher #define RBR_HDH_HEAD_H 0x0000000000000fffULL
2034e689cf4aSJeff Kirsher
2035e689cf4aSJeff Kirsher #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2036e689cf4aSJeff Kirsher #define RBR_HDL_HEAD_L 0x00000000fffffffcULL
2037e689cf4aSJeff Kirsher
2038e689cf4aSJeff Kirsher #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
2039e689cf4aSJeff Kirsher #define RCRCFIG_A_LEN 0xffff000000000000ULL
2040e689cf4aSJeff Kirsher #define RCRCFIG_A_LEN_SHIFT 48
2041e689cf4aSJeff Kirsher #define RCRCFIG_A_STADDR_BASE 0x00000ffffff80000ULL
2042e689cf4aSJeff Kirsher #define RCRCFIG_A_STADDR 0x000000000007ffc0ULL
2043e689cf4aSJeff Kirsher
2044e689cf4aSJeff Kirsher #define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL)
2045e689cf4aSJeff Kirsher #define RCRCFIG_B_PTHRES 0x00000000ffff0000ULL
2046e689cf4aSJeff Kirsher #define RCRCFIG_B_PTHRES_SHIFT 16
2047e689cf4aSJeff Kirsher #define RCRCFIG_B_ENTOUT 0x0000000000008000ULL
2048e689cf4aSJeff Kirsher #define RCRCFIG_B_TIMEOUT 0x000000000000003fULL
2049e689cf4aSJeff Kirsher #define RCRCFIG_B_TIMEOUT_SHIFT 0
2050e689cf4aSJeff Kirsher
2051e689cf4aSJeff Kirsher #define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL)
2052e689cf4aSJeff Kirsher #define RCRSTAT_A_QLEN 0x000000000000ffffULL
2053e689cf4aSJeff Kirsher
2054e689cf4aSJeff Kirsher #define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL)
2055e689cf4aSJeff Kirsher #define RCRSTAT_B_TIPTR_H 0x0000000000000fffULL
2056e689cf4aSJeff Kirsher
2057e689cf4aSJeff Kirsher #define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL)
2058e689cf4aSJeff Kirsher #define RCRSTAT_C_TIPTR_L 0x00000000fffffff8ULL
2059e689cf4aSJeff Kirsher
2060e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL)
2061e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBR_TMOUT 0x0020000000000000ULL
2062e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RSP_CNT_ERR 0x0010000000000000ULL
2063e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_BYTE_EN_BUS 0x0008000000000000ULL
2064e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RSP_DAT_ERR 0x0004000000000000ULL
2065e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCR_ACK_ERR 0x0002000000000000ULL
2066e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DC_FIFO_ERR 0x0001000000000000ULL
2067e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_MEX 0x0000800000000000ULL
2068e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCRTHRES 0x0000400000000000ULL
2069e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCRTO 0x0000200000000000ULL
2070e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCR_SHA_PAR 0x0000100000000000ULL
2071e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBR_PRE_PAR 0x0000080000000000ULL
2072e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PORT_DROP_PKT 0x0000040000000000ULL
2073e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_WRED_DROP 0x0000020000000000ULL
2074e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBR_PRE_EMTY 0x0000010000000000ULL
2075e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCRSHADOW_FULL 0x0000008000000000ULL
2076e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_CONFIG_ERR 0x0000004000000000ULL
2077e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCRINCON 0x0000002000000000ULL
2078e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RCRFULL 0x0000001000000000ULL
2079e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBR_EMPTY 0x0000000800000000ULL
2080e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBRFULL 0x0000000400000000ULL
2081e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_RBRLOGPAGE 0x0000000200000000ULL
2082e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_CFIGLOGPAGE 0x0000000100000000ULL
2083e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PTRREAD 0x00000000ffff0000ULL
2084e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PTRREAD_SHIFT 16
2085e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PKTREAD 0x000000000000ffffULL
2086e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PKTREAD_SHIFT 0
2087e689cf4aSJeff Kirsher
2088e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_CHAN_FATAL (RX_DMA_CTL_STAT_RBR_TMOUT | \
2089e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RSP_CNT_ERR | \
2090e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_BYTE_EN_BUS | \
2091e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RSP_DAT_ERR | \
2092e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCR_ACK_ERR | \
2093e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCR_SHA_PAR | \
2094e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RBR_PRE_PAR | \
2095e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_CONFIG_ERR | \
2096e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCRINCON | \
2097e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCRFULL | \
2098e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RBRFULL | \
2099e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RBRLOGPAGE | \
2100e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_CFIGLOGPAGE)
2101e689cf4aSJeff Kirsher
2102e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_PORT_FATAL (RX_DMA_CTL_STAT_DC_FIFO_ERR)
2103e689cf4aSJeff Kirsher
2104e689cf4aSJeff Kirsher #define RX_DMA_CTL_WRITE_CLEAR_ERRS (RX_DMA_CTL_STAT_RBR_EMPTY | \
2105e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCRSHADOW_FULL | \
2106e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RBR_PRE_EMTY | \
2107e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_WRED_DROP | \
2108e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_PORT_DROP_PKT | \
2109e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCRTO | \
2110e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_RCRTHRES | \
2111e689cf4aSJeff Kirsher RX_DMA_CTL_STAT_DC_FIFO_ERR)
2112e689cf4aSJeff Kirsher
2113e689cf4aSJeff Kirsher #define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL)
2114e689cf4aSJeff Kirsher #define RCR_FLSH_FLSH 0x0000000000000001ULL
2115e689cf4aSJeff Kirsher
2116e689cf4aSJeff Kirsher #define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL)
2117e689cf4aSJeff Kirsher #define RXMISC_OFLOW 0x0000000000010000ULL
2118e689cf4aSJeff Kirsher #define RXMISC_COUNT 0x000000000000ffffULL
2119e689cf4aSJeff Kirsher
2120e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL)
2121e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBR_TMOUT 0x0020000000000000ULL
2122e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR 0x0010000000000000ULL
2123e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS 0x0008000000000000ULL
2124e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR 0x0004000000000000ULL
2125e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR 0x0002000000000000ULL
2126e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR 0x0001000000000000ULL
2127e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_MEX 0x0000800000000000ULL
2128e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCRTHRES 0x0000400000000000ULL
2129e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCRTO 0x0000200000000000ULL
2130e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR 0x0000100000000000ULL
2131e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR 0x0000080000000000ULL
2132e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT 0x0000040000000000ULL
2133e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_WRED_DROP 0x0000020000000000ULL
2134e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY 0x0000010000000000ULL
2135e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL 0x0000008000000000ULL
2136e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_CONFIG_ERR 0x0000004000000000ULL
2137e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCRINCON 0x0000002000000000ULL
2138e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RCRFULL 0x0000001000000000ULL
2139e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBR_EMPTY 0x0000000800000000ULL
2140e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBRFULL 0x0000000400000000ULL
2141e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_RBRLOGPAGE 0x0000000200000000ULL
2142e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE 0x0000000100000000ULL
2143e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_PTRREAD 0x00000000ffff0000ULL
2144e689cf4aSJeff Kirsher #define RX_DMA_CTL_STAT_DBG_PKTREAD 0x000000000000ffffULL
2145e689cf4aSJeff Kirsher
2146e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL)
2147e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBR_TMOUT 0x0000000000200000ULL
2148e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RSP_CNT_ERR 0x0000000000100000ULL
2149e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_BYTE_EN_BUS 0x0000000000080000ULL
2150e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RSP_DAT_ERR 0x0000000000040000ULL
2151e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCR_ACK_ERR 0x0000000000020000ULL
2152e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_DC_FIFO_ERR 0x0000000000010000ULL
2153e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCRTHRES 0x0000000000004000ULL
2154e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCRTO 0x0000000000002000ULL
2155e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCR_SHA_PAR 0x0000000000001000ULL
2156e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBR_PRE_PAR 0x0000000000000800ULL
2157e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_PORT_DROP_PKT 0x0000000000000400ULL
2158e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_WRED_DROP 0x0000000000000200ULL
2159e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBR_PRE_EMTY 0x0000000000000100ULL
2160e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCR_SHADOW_FULL 0x0000000000000080ULL
2161e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_CONFIG_ERR 0x0000000000000040ULL
2162e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCRINCON 0x0000000000000020ULL
2163e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RCRFULL 0x0000000000000010ULL
2164e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBR_EMPTY 0x0000000000000008ULL
2165e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBRFULL 0x0000000000000004ULL
2166e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_RBRLOGPAGE 0x0000000000000002ULL
2167e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_CFIGLOGPAGE 0x0000000000000001ULL
2168e689cf4aSJeff Kirsher #define RX_DMA_ENT_MSK_ALL 0x00000000003f7fffULL
2169e689cf4aSJeff Kirsher
2170e689cf4aSJeff Kirsher #define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL)
2171e689cf4aSJeff Kirsher #define TX_RNG_CFIG_LEN 0x1fff000000000000ULL
2172e689cf4aSJeff Kirsher #define TX_RNG_CFIG_LEN_SHIFT 48
2173e689cf4aSJeff Kirsher #define TX_RNG_CFIG_STADDR_BASE 0x00000ffffff80000ULL
2174e689cf4aSJeff Kirsher #define TX_RNG_CFIG_STADDR 0x000000000007ffc0ULL
2175e689cf4aSJeff Kirsher
2176e689cf4aSJeff Kirsher #define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL)
2177e689cf4aSJeff Kirsher #define TX_RING_HDL_WRAP 0x0000000000080000ULL
2178e689cf4aSJeff Kirsher #define TX_RING_HDL_HEAD 0x000000000007fff8ULL
2179e689cf4aSJeff Kirsher #define TX_RING_HDL_HEAD_SHIFT 3
2180e689cf4aSJeff Kirsher
2181e689cf4aSJeff Kirsher #define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL)
2182e689cf4aSJeff Kirsher #define TX_RING_KICK_WRAP 0x0000000000080000ULL
2183e689cf4aSJeff Kirsher #define TX_RING_KICK_TAIL 0x000000000007fff8ULL
2184e689cf4aSJeff Kirsher
2185e689cf4aSJeff Kirsher #define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL)
2186e689cf4aSJeff Kirsher #define TX_ENT_MSK_MK 0x0000000000008000ULL
2187e689cf4aSJeff Kirsher #define TX_ENT_MSK_MBOX_ERR 0x0000000000000080ULL
2188e689cf4aSJeff Kirsher #define TX_ENT_MSK_PKT_SIZE_ERR 0x0000000000000040ULL
2189e689cf4aSJeff Kirsher #define TX_ENT_MSK_TX_RING_OFLOW 0x0000000000000020ULL
2190e689cf4aSJeff Kirsher #define TX_ENT_MSK_PREF_BUF_ECC_ERR 0x0000000000000010ULL
2191e689cf4aSJeff Kirsher #define TX_ENT_MSK_NACK_PREF 0x0000000000000008ULL
2192e689cf4aSJeff Kirsher #define TX_ENT_MSK_NACK_PKT_RD 0x0000000000000004ULL
2193e689cf4aSJeff Kirsher #define TX_ENT_MSK_CONF_PART_ERR 0x0000000000000002ULL
2194e689cf4aSJeff Kirsher #define TX_ENT_MSK_PKT_PRT_ERR 0x0000000000000001ULL
2195e689cf4aSJeff Kirsher
2196e689cf4aSJeff Kirsher #define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL)
2197e689cf4aSJeff Kirsher #define TX_CS_PKT_CNT 0x0fff000000000000ULL
2198e689cf4aSJeff Kirsher #define TX_CS_PKT_CNT_SHIFT 48
2199e689cf4aSJeff Kirsher #define TX_CS_LASTMARK 0x00000fff00000000ULL
2200e689cf4aSJeff Kirsher #define TX_CS_LASTMARK_SHIFT 32
2201e689cf4aSJeff Kirsher #define TX_CS_RST 0x0000000080000000ULL
2202e689cf4aSJeff Kirsher #define TX_CS_RST_STATE 0x0000000040000000ULL
2203e689cf4aSJeff Kirsher #define TX_CS_MB 0x0000000020000000ULL
2204e689cf4aSJeff Kirsher #define TX_CS_STOP_N_GO 0x0000000010000000ULL
2205e689cf4aSJeff Kirsher #define TX_CS_SNG_STATE 0x0000000008000000ULL
2206e689cf4aSJeff Kirsher #define TX_CS_MK 0x0000000000008000ULL
2207e689cf4aSJeff Kirsher #define TX_CS_MMK 0x0000000000004000ULL
2208e689cf4aSJeff Kirsher #define TX_CS_MBOX_ERR 0x0000000000000080ULL
2209e689cf4aSJeff Kirsher #define TX_CS_PKT_SIZE_ERR 0x0000000000000040ULL
2210e689cf4aSJeff Kirsher #define TX_CS_TX_RING_OFLOW 0x0000000000000020ULL
2211e689cf4aSJeff Kirsher #define TX_CS_PREF_BUF_PAR_ERR 0x0000000000000010ULL
2212e689cf4aSJeff Kirsher #define TX_CS_NACK_PREF 0x0000000000000008ULL
2213e689cf4aSJeff Kirsher #define TX_CS_NACK_PKT_RD 0x0000000000000004ULL
2214e689cf4aSJeff Kirsher #define TX_CS_CONF_PART_ERR 0x0000000000000002ULL
2215e689cf4aSJeff Kirsher #define TX_CS_PKT_PRT_ERR 0x0000000000000001ULL
2216e689cf4aSJeff Kirsher
2217e689cf4aSJeff Kirsher #define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL)
2218e689cf4aSJeff Kirsher #define TXDMA_MBH_MBADDR 0x0000000000000fffULL
2219e689cf4aSJeff Kirsher
2220e689cf4aSJeff Kirsher #define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL)
2221e689cf4aSJeff Kirsher #define TXDMA_MBL_MBADDR 0x00000000ffffffc0ULL
2222e689cf4aSJeff Kirsher
2223e689cf4aSJeff Kirsher #define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL)
2224e689cf4aSJeff Kirsher #define TX_DMA_PRE_ST_SHADOW_HD 0x000000000007ffffULL
2225e689cf4aSJeff Kirsher
2226e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL)
2227e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGH_ERR 0x0000000080000000ULL
2228e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGH_MERR 0x0000000040000000ULL
2229e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGH_ERRCODE 0x0000000038000000ULL
2230e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGH_ERRADDR 0x0000000000000fffULL
2231e689cf4aSJeff Kirsher
2232e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL)
2233e689cf4aSJeff Kirsher #define TX_RNG_ERR_LOGL_ERRADDR 0x00000000ffffffffULL
2234e689cf4aSJeff Kirsher
2235e689cf4aSJeff Kirsher #define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL)
2236e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_MK 0x0000000000008000ULL
2237e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_MBOX_ERR 0x0000000000000080ULL
2238e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_PKT_SIZE_ERR 0x0000000000000040ULL
2239e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_TX_RING_OFLOW 0x0000000000000020ULL
2240e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_PREF_BUF_PAR_ERR 0x0000000000000010ULL
2241e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_NACK_PREF 0x0000000000000008ULL
2242e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_NACK_PKT_RD 0x0000000000000004ULL
2243e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_CONF_PART_ERR 0x0000000000000002ULL
2244e689cf4aSJeff Kirsher #define TDMC_INTR_DBG_PKT_PART_ERR 0x0000000000000001ULL
2245e689cf4aSJeff Kirsher
2246e689cf4aSJeff Kirsher #define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL)
2247e689cf4aSJeff Kirsher #define TX_CS_DBG_PKT_CNT 0x0fff000000000000ULL
2248e689cf4aSJeff Kirsher
2249e689cf4aSJeff Kirsher #define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL)
2250e689cf4aSJeff Kirsher #define TDMC_INJ_PAR_ERR_VAL 0x000000000000ffffULL
2251e689cf4aSJeff Kirsher
2252e689cf4aSJeff Kirsher #define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL)
2253e689cf4aSJeff Kirsher #define TDMC_DBG_SEL_DBG_SEL 0x000000000000003fULL
2254e689cf4aSJeff Kirsher
2255e689cf4aSJeff Kirsher #define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL)
2256e689cf4aSJeff Kirsher #define TDMC_TRAINING_VECTOR_VEC 0x00000000ffffffffULL
2257e689cf4aSJeff Kirsher
2258e689cf4aSJeff Kirsher #define TXC_DMA_MAX(CHAN) (FZC_TXC + 0x00000UL + (CHAN)*0x1000UL)
2259e689cf4aSJeff Kirsher #define TXC_DMA_MAX_LEN(CHAN) (FZC_TXC + 0x00008UL + (CHAN)*0x1000UL)
2260e689cf4aSJeff Kirsher
2261e689cf4aSJeff Kirsher #define TXC_CONTROL (FZC_TXC + 0x20000UL)
2262e689cf4aSJeff Kirsher #define TXC_CONTROL_ENABLE 0x0000000000000010ULL
2263e689cf4aSJeff Kirsher #define TXC_CONTROL_PORT_ENABLE(X) (1 << (X))
2264e689cf4aSJeff Kirsher
2265e689cf4aSJeff Kirsher #define TXC_TRAINING_VEC (FZC_TXC + 0x20008UL)
2266e689cf4aSJeff Kirsher #define TXC_TRAINING_VEC_MASK 0x00000000ffffffffULL
2267e689cf4aSJeff Kirsher
2268e689cf4aSJeff Kirsher #define TXC_DEBUG (FZC_TXC + 0x20010UL)
2269e689cf4aSJeff Kirsher #define TXC_DEBUG_SELECT 0x000000000000003fULL
2270e689cf4aSJeff Kirsher
2271e689cf4aSJeff Kirsher #define TXC_MAX_REORDER (FZC_TXC + 0x20018UL)
2272e689cf4aSJeff Kirsher #define TXC_MAX_REORDER_PORT3 0x000000000f000000ULL
2273e689cf4aSJeff Kirsher #define TXC_MAX_REORDER_PORT2 0x00000000000f0000ULL
2274e689cf4aSJeff Kirsher #define TXC_MAX_REORDER_PORT1 0x0000000000000f00ULL
2275e689cf4aSJeff Kirsher #define TXC_MAX_REORDER_PORT0 0x000000000000000fULL
2276e689cf4aSJeff Kirsher
2277e689cf4aSJeff Kirsher #define TXC_PORT_CTL(PORT) (FZC_TXC + 0x20020UL + (PORT)*0x100UL)
2278e689cf4aSJeff Kirsher #define TXC_PORT_CTL_CLR_ALL_STAT 0x0000000000000001ULL
2279e689cf4aSJeff Kirsher
2280e689cf4aSJeff Kirsher #define TXC_PKT_STUFFED(PORT) (FZC_TXC + 0x20030UL + (PORT)*0x100UL)
2281e689cf4aSJeff Kirsher #define TXC_PKT_STUFFED_PP_REORDER 0x00000000ffff0000ULL
2282e689cf4aSJeff Kirsher #define TXC_PKT_STUFFED_PP_PACKETASSY 0x000000000000ffffULL
2283e689cf4aSJeff Kirsher
2284e689cf4aSJeff Kirsher #define TXC_PKT_XMIT(PORT) (FZC_TXC + 0x20038UL + (PORT)*0x100UL)
2285e689cf4aSJeff Kirsher #define TXC_PKT_XMIT_BYTES 0x00000000ffff0000ULL
2286e689cf4aSJeff Kirsher #define TXC_PKT_XMIT_PKTS 0x000000000000ffffULL
2287e689cf4aSJeff Kirsher
2288e689cf4aSJeff Kirsher #define TXC_ROECC_CTL(PORT) (FZC_TXC + 0x20040UL + (PORT)*0x100UL)
2289e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_DISABLE_UE 0x0000000080000000ULL
2290e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
2291e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
2292e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_ALL_PKTS 0x0000000000000400ULL
2293e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_ALT_PKTS 0x0000000000000200ULL
2294e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
2295e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
2296e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
2297e689cf4aSJeff Kirsher #define TXC_ROECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
2298e689cf4aSJeff Kirsher
2299e689cf4aSJeff Kirsher #define TXC_ROECC_ST(PORT) (FZC_TXC + 0x20048UL + (PORT)*0x100UL)
2300e689cf4aSJeff Kirsher #define TXC_ROECC_CLR_ST 0x0000000080000000ULL
2301e689cf4aSJeff Kirsher #define TXC_ROECC_CE 0x0000000000020000ULL
2302e689cf4aSJeff Kirsher #define TXC_ROECC_UE 0x0000000000010000ULL
2303e689cf4aSJeff Kirsher #define TXC_ROECC_ST_ECC_ADDR 0x00000000000003ffULL
2304e689cf4aSJeff Kirsher
2305e689cf4aSJeff Kirsher #define TXC_RO_DATA0(PORT) (FZC_TXC + 0x20050UL + (PORT)*0x100UL)
2306e689cf4aSJeff Kirsher #define TXC_RO_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
2307e689cf4aSJeff Kirsher
2308e689cf4aSJeff Kirsher #define TXC_RO_DATA1(PORT) (FZC_TXC + 0x20058UL + (PORT)*0x100UL)
2309e689cf4aSJeff Kirsher #define TXC_RO_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
2310e689cf4aSJeff Kirsher
2311e689cf4aSJeff Kirsher #define TXC_RO_DATA2(PORT) (FZC_TXC + 0x20060UL + (PORT)*0x100UL)
2312e689cf4aSJeff Kirsher #define TXC_RO_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
2313e689cf4aSJeff Kirsher
2314e689cf4aSJeff Kirsher #define TXC_RO_DATA3(PORT) (FZC_TXC + 0x20068UL + (PORT)*0x100UL)
2315e689cf4aSJeff Kirsher #define TXC_RO_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
2316e689cf4aSJeff Kirsher
2317e689cf4aSJeff Kirsher #define TXC_RO_DATA4(PORT) (FZC_TXC + 0x20070UL + (PORT)*0x100UL)
2318e689cf4aSJeff Kirsher #define TXC_RO_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
2319e689cf4aSJeff Kirsher
2320e689cf4aSJeff Kirsher #define TXC_SFECC_CTL(PORT) (FZC_TXC + 0x20078UL + (PORT)*0x100UL)
2321e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_DISABLE_UE 0x0000000080000000ULL
2322e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_DBL_BIT_ERR 0x0000000000020000ULL
2323e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_SNGL_BIT_ERR 0x0000000000010000ULL
2324e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_ALL_PKTS 0x0000000000000400ULL
2325e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_ALT_PKTS 0x0000000000000200ULL
2326e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_ONE_PKT_ONLY 0x0000000000000100ULL
2327e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_LST_PKT_LINE 0x0000000000000004ULL
2328e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_2ND_PKT_LINE 0x0000000000000002ULL
2329e689cf4aSJeff Kirsher #define TXC_SFECC_CTL_1ST_PKT_LINE 0x0000000000000001ULL
2330e689cf4aSJeff Kirsher
2331e689cf4aSJeff Kirsher #define TXC_SFECC_ST(PORT) (FZC_TXC + 0x20080UL + (PORT)*0x100UL)
2332e689cf4aSJeff Kirsher #define TXC_SFECC_ST_CLR_ST 0x0000000080000000ULL
2333e689cf4aSJeff Kirsher #define TXC_SFECC_ST_CE 0x0000000000020000ULL
2334e689cf4aSJeff Kirsher #define TXC_SFECC_ST_UE 0x0000000000010000ULL
2335e689cf4aSJeff Kirsher #define TXC_SFECC_ST_ECC_ADDR 0x00000000000003ffULL
2336e689cf4aSJeff Kirsher
2337e689cf4aSJeff Kirsher #define TXC_SF_DATA0(PORT) (FZC_TXC + 0x20088UL + (PORT)*0x100UL)
2338e689cf4aSJeff Kirsher #define TXC_SF_DATA0_DATA0 0x00000000ffffffffULL /* bits 31:0 */
2339e689cf4aSJeff Kirsher
2340e689cf4aSJeff Kirsher #define TXC_SF_DATA1(PORT) (FZC_TXC + 0x20090UL + (PORT)*0x100UL)
2341e689cf4aSJeff Kirsher #define TXC_SF_DATA1_DATA1 0x00000000ffffffffULL /* bits 63:32 */
2342e689cf4aSJeff Kirsher
2343e689cf4aSJeff Kirsher #define TXC_SF_DATA2(PORT) (FZC_TXC + 0x20098UL + (PORT)*0x100UL)
2344e689cf4aSJeff Kirsher #define TXC_SF_DATA2_DATA2 0x00000000ffffffffULL /* bits 95:64 */
2345e689cf4aSJeff Kirsher
2346e689cf4aSJeff Kirsher #define TXC_SF_DATA3(PORT) (FZC_TXC + 0x200a0UL + (PORT)*0x100UL)
2347e689cf4aSJeff Kirsher #define TXC_SF_DATA3_DATA3 0x00000000ffffffffULL /* bits 127:96 */
2348e689cf4aSJeff Kirsher
2349e689cf4aSJeff Kirsher #define TXC_SF_DATA4(PORT) (FZC_TXC + 0x200a8UL + (PORT)*0x100UL)
2350e689cf4aSJeff Kirsher #define TXC_SF_DATA4_DATA4 0x0000000000ffffffULL /* bits 151:128 */
2351e689cf4aSJeff Kirsher
2352e689cf4aSJeff Kirsher #define TXC_RO_TIDS(PORT) (FZC_TXC + 0x200b0UL + (PORT)*0x100UL)
2353e689cf4aSJeff Kirsher #define TXC_RO_TIDS_IN_USE 0x00000000ffffffffULL
2354e689cf4aSJeff Kirsher
2355e689cf4aSJeff Kirsher #define TXC_RO_STATE0(PORT) (FZC_TXC + 0x200b8UL + (PORT)*0x100UL)
2356e689cf4aSJeff Kirsher #define TXC_RO_STATE0_DUPLICATE_TID 0x00000000ffffffffULL
2357e689cf4aSJeff Kirsher
2358e689cf4aSJeff Kirsher #define TXC_RO_STATE1(PORT) (FZC_TXC + 0x200c0UL + (PORT)*0x100UL)
2359e689cf4aSJeff Kirsher #define TXC_RO_STATE1_UNUSED_TID 0x00000000ffffffffULL
2360e689cf4aSJeff Kirsher
2361e689cf4aSJeff Kirsher #define TXC_RO_STATE2(PORT) (FZC_TXC + 0x200c8UL + (PORT)*0x100UL)
2362e689cf4aSJeff Kirsher #define TXC_RO_STATE2_TRANS_TIMEOUT 0x00000000ffffffffULL
2363e689cf4aSJeff Kirsher
2364e689cf4aSJeff Kirsher #define TXC_RO_STATE3(PORT) (FZC_TXC + 0x200d0UL + (PORT)*0x100UL)
2365e689cf4aSJeff Kirsher #define TXC_RO_STATE3_ENAB_SPC_WMARK 0x0000000080000000ULL
2366e689cf4aSJeff Kirsher #define TXC_RO_STATE3_RO_SPC_WMARK 0x000000007fe00000ULL
2367e689cf4aSJeff Kirsher #define TXC_RO_STATE3_ROFIFO_SPC_AVAIL 0x00000000001ff800ULL
2368e689cf4aSJeff Kirsher #define TXC_RO_STATE3_ENAB_RO_WMARK 0x0000000000000100ULL
2369e689cf4aSJeff Kirsher #define TXC_RO_STATE3_HIGH_RO_USED 0x00000000000000f0ULL
2370e689cf4aSJeff Kirsher #define TXC_RO_STATE3_NUM_RO_USED 0x000000000000000fULL
2371e689cf4aSJeff Kirsher
2372e689cf4aSJeff Kirsher #define TXC_RO_CTL(PORT) (FZC_TXC + 0x200d8UL + (PORT)*0x100UL)
2373e689cf4aSJeff Kirsher #define TXC_RO_CTL_CLR_FAIL_STATE 0x0000000080000000ULL
2374e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_ADDR 0x000000000f000000ULL
2375e689cf4aSJeff Kirsher #define TXC_RO_CTL_ADDR_FAILED 0x0000000000400000ULL
2376e689cf4aSJeff Kirsher #define TXC_RO_CTL_DMA_FAILED 0x0000000000200000ULL
2377e689cf4aSJeff Kirsher #define TXC_RO_CTL_LEN_FAILED 0x0000000000100000ULL
2378e689cf4aSJeff Kirsher #define TXC_RO_CTL_CAPT_ADDR_FAILED 0x0000000000040000ULL
2379e689cf4aSJeff Kirsher #define TXC_RO_CTL_CAPT_DMA_FAILED 0x0000000000020000ULL
2380e689cf4aSJeff Kirsher #define TXC_RO_CTL_CAPT_LEN_FAILED 0x0000000000010000ULL
2381e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_STATE_RD_DONE 0x0000000000000080ULL
2382e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_STATE_WR_DONE 0x0000000000000040ULL
2383e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_STATE_RD 0x0000000000000020ULL
2384e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_STATE_WR 0x0000000000000010ULL
2385e689cf4aSJeff Kirsher #define TXC_RO_CTL_RO_STATE_ADDR 0x000000000000000fULL
2386e689cf4aSJeff Kirsher
2387e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA0(PORT) (FZC_TXC + 0x200e0UL + (PORT)*0x100UL)
2388e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA0_DATA0 0x00000000ffffffffULL
2389e689cf4aSJeff Kirsher
2390e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA1(PORT) (FZC_TXC + 0x200e8UL + (PORT)*0x100UL)
2391e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA1_DATA1 0x00000000ffffffffULL
2392e689cf4aSJeff Kirsher
2393e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA2(PORT) (FZC_TXC + 0x200f0UL + (PORT)*0x100UL)
2394e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA2_DATA2 0x00000000ffffffffULL
2395e689cf4aSJeff Kirsher
2396e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA3(PORT) (FZC_TXC + 0x200f8UL + (PORT)*0x100UL)
2397e689cf4aSJeff Kirsher #define TXC_RO_ST_DATA3_DATA3 0x00000000ffffffffULL
2398e689cf4aSJeff Kirsher
2399e689cf4aSJeff Kirsher #define TXC_PORT_PACKET_REQ(PORT) (FZC_TXC + 0x20100UL + (PORT)*0x100UL)
2400e689cf4aSJeff Kirsher #define TXC_PORT_PACKET_REQ_GATHER_REQ 0x00000000f0000000ULL
2401e689cf4aSJeff Kirsher #define TXC_PORT_PACKET_REQ_PKT_REQ 0x000000000fff0000ULL
2402e689cf4aSJeff Kirsher #define TXC_PORT_PACKET_REQ_PERR_ABRT 0x000000000000ffffULL
2403e689cf4aSJeff Kirsher
2404e689cf4aSJeff Kirsher /* bits are same as TXC_INT_STAT */
2405e689cf4aSJeff Kirsher #define TXC_INT_STAT_DBG (FZC_TXC + 0x20420UL)
2406e689cf4aSJeff Kirsher
2407e689cf4aSJeff Kirsher #define TXC_INT_STAT (FZC_TXC + 0x20428UL)
2408e689cf4aSJeff Kirsher #define TXC_INT_STAT_VAL_SHIFT(PORT) ((PORT) * 8)
2409e689cf4aSJeff Kirsher #define TXC_INT_STAT_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2410e689cf4aSJeff Kirsher #define TXC_INT_STAT_SF_CE(PORT) (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT))
2411e689cf4aSJeff Kirsher #define TXC_INT_STAT_SF_UE(PORT) (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT))
2412e689cf4aSJeff Kirsher #define TXC_INT_STAT_RO_CE(PORT) (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT))
2413e689cf4aSJeff Kirsher #define TXC_INT_STAT_RO_UE(PORT) (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT))
2414e689cf4aSJeff Kirsher #define TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT))
2415e689cf4aSJeff Kirsher #define TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT))
2416e689cf4aSJeff Kirsher
2417e689cf4aSJeff Kirsher #define TXC_INT_MASK (FZC_TXC + 0x20430UL)
2418e689cf4aSJeff Kirsher #define TXC_INT_MASK_VAL_SHIFT(PORT) ((PORT) * 8)
2419e689cf4aSJeff Kirsher #define TXC_INT_MASK_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
2420e689cf4aSJeff Kirsher
2421e689cf4aSJeff Kirsher #define TXC_INT_MASK_SF_CE 0x01
2422e689cf4aSJeff Kirsher #define TXC_INT_MASK_SF_UE 0x02
2423e689cf4aSJeff Kirsher #define TXC_INT_MASK_RO_CE 0x04
2424e689cf4aSJeff Kirsher #define TXC_INT_MASK_RO_UE 0x08
2425e689cf4aSJeff Kirsher #define TXC_INT_MASK_REORDER_ERR 0x10
2426e689cf4aSJeff Kirsher #define TXC_INT_MASK_PKTASM_DEAD 0x20
2427e689cf4aSJeff Kirsher #define TXC_INT_MASK_ALL 0x3f
2428e689cf4aSJeff Kirsher
2429e689cf4aSJeff Kirsher #define TXC_PORT_DMA(IDX) (FZC_TXC + 0x20028UL + (IDX)*0x100UL)
2430e689cf4aSJeff Kirsher
2431e689cf4aSJeff Kirsher #define ESPC_PIO_EN (FZC_PROM + 0x40000UL)
2432e689cf4aSJeff Kirsher #define ESPC_PIO_EN_ENABLE 0x0000000000000001ULL
2433e689cf4aSJeff Kirsher
2434e689cf4aSJeff Kirsher #define ESPC_PIO_STAT (FZC_PROM + 0x40008UL)
2435e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_READ_START 0x0000000080000000ULL
2436e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_READ_END 0x0000000040000000ULL
2437e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_WRITE_INIT 0x0000000020000000ULL
2438e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_WRITE_END 0x0000000010000000ULL
2439e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_ADDR 0x0000000003ffff00ULL
2440e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_ADDR_SHIFT 8
2441e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_DATA 0x00000000000000ffULL
2442e689cf4aSJeff Kirsher #define ESPC_PIO_STAT_DATA_SHIFT 0
2443e689cf4aSJeff Kirsher
2444e689cf4aSJeff Kirsher #define ESPC_NCR(IDX) (FZC_PROM + 0x40020UL + (IDX)*0x8UL)
2445e689cf4aSJeff Kirsher #define ESPC_NCR_VAL 0x00000000ffffffffULL
2446e689cf4aSJeff Kirsher
2447e689cf4aSJeff Kirsher #define ESPC_MAC_ADDR0 ESPC_NCR(0)
2448e689cf4aSJeff Kirsher #define ESPC_MAC_ADDR1 ESPC_NCR(1)
2449e689cf4aSJeff Kirsher #define ESPC_NUM_PORTS_MACS ESPC_NCR(2)
2450e689cf4aSJeff Kirsher #define ESPC_NUM_PORTS_MACS_VAL 0x00000000000000ffULL
2451e689cf4aSJeff Kirsher #define ESPC_MOD_STR_LEN ESPC_NCR(4)
2452e689cf4aSJeff Kirsher #define ESPC_MOD_STR_1 ESPC_NCR(5)
2453e689cf4aSJeff Kirsher #define ESPC_MOD_STR_2 ESPC_NCR(6)
2454e689cf4aSJeff Kirsher #define ESPC_MOD_STR_3 ESPC_NCR(7)
2455e689cf4aSJeff Kirsher #define ESPC_MOD_STR_4 ESPC_NCR(8)
2456e689cf4aSJeff Kirsher #define ESPC_MOD_STR_5 ESPC_NCR(9)
2457e689cf4aSJeff Kirsher #define ESPC_MOD_STR_6 ESPC_NCR(10)
2458e689cf4aSJeff Kirsher #define ESPC_MOD_STR_7 ESPC_NCR(11)
2459e689cf4aSJeff Kirsher #define ESPC_MOD_STR_8 ESPC_NCR(12)
2460e689cf4aSJeff Kirsher #define ESPC_BD_MOD_STR_LEN ESPC_NCR(13)
2461e689cf4aSJeff Kirsher #define ESPC_BD_MOD_STR_1 ESPC_NCR(14)
2462e689cf4aSJeff Kirsher #define ESPC_BD_MOD_STR_2 ESPC_NCR(15)
2463e689cf4aSJeff Kirsher #define ESPC_BD_MOD_STR_3 ESPC_NCR(16)
2464e689cf4aSJeff Kirsher #define ESPC_BD_MOD_STR_4 ESPC_NCR(17)
2465e689cf4aSJeff Kirsher
2466e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE ESPC_NCR(18)
2467e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT0 0x00000000ff000000ULL
2468e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT0_SHIFT 24
2469e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT1 0x0000000000ff0000ULL
2470e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT1_SHIFT 16
2471e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT2 0x000000000000ff00ULL
2472e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT2_SHIFT 8
2473e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT3 0x00000000000000ffULL
2474e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_PORT3_SHIFT 0
2475e689cf4aSJeff Kirsher
2476e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_1G_COPPER 3
2477e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_1G_FIBER 2
2478e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_10G_COPPER 1
2479e689cf4aSJeff Kirsher #define ESPC_PHY_TYPE_10G_FIBER 0
2480e689cf4aSJeff Kirsher
2481e689cf4aSJeff Kirsher #define ESPC_MAX_FM_SZ ESPC_NCR(19)
2482e689cf4aSJeff Kirsher
2483e689cf4aSJeff Kirsher #define ESPC_INTR_NUM ESPC_NCR(20)
2484e689cf4aSJeff Kirsher #define ESPC_INTR_NUM_PORT0 0x00000000ff000000ULL
2485e689cf4aSJeff Kirsher #define ESPC_INTR_NUM_PORT1 0x0000000000ff0000ULL
2486e689cf4aSJeff Kirsher #define ESPC_INTR_NUM_PORT2 0x000000000000ff00ULL
2487e689cf4aSJeff Kirsher #define ESPC_INTR_NUM_PORT3 0x00000000000000ffULL
2488e689cf4aSJeff Kirsher
2489e689cf4aSJeff Kirsher #define ESPC_VER_IMGSZ ESPC_NCR(21)
2490e689cf4aSJeff Kirsher #define ESPC_VER_IMGSZ_IMGSZ 0x00000000ffff0000ULL
2491e689cf4aSJeff Kirsher #define ESPC_VER_IMGSZ_IMGSZ_SHIFT 16
2492e689cf4aSJeff Kirsher #define ESPC_VER_IMGSZ_VER 0x000000000000ffffULL
2493e689cf4aSJeff Kirsher #define ESPC_VER_IMGSZ_VER_SHIFT 0
2494e689cf4aSJeff Kirsher
2495e689cf4aSJeff Kirsher #define ESPC_CHKSUM ESPC_NCR(22)
2496e689cf4aSJeff Kirsher #define ESPC_CHKSUM_SUM 0x00000000000000ffULL
2497e689cf4aSJeff Kirsher
2498e689cf4aSJeff Kirsher #define ESPC_EEPROM_SIZE 0x100000
2499e689cf4aSJeff Kirsher
2500e689cf4aSJeff Kirsher #define CLASS_CODE_UNRECOG 0x00
2501e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY1 0x01
2502e689cf4aSJeff Kirsher #define CLASS_CODE_ETHERTYPE1 0x02
2503e689cf4aSJeff Kirsher #define CLASS_CODE_ETHERTYPE2 0x03
2504e689cf4aSJeff Kirsher #define CLASS_CODE_USER_PROG1 0x04
2505e689cf4aSJeff Kirsher #define CLASS_CODE_USER_PROG2 0x05
2506e689cf4aSJeff Kirsher #define CLASS_CODE_USER_PROG3 0x06
2507e689cf4aSJeff Kirsher #define CLASS_CODE_USER_PROG4 0x07
2508e689cf4aSJeff Kirsher #define CLASS_CODE_TCP_IPV4 0x08
2509e689cf4aSJeff Kirsher #define CLASS_CODE_UDP_IPV4 0x09
2510e689cf4aSJeff Kirsher #define CLASS_CODE_AH_ESP_IPV4 0x0a
2511e689cf4aSJeff Kirsher #define CLASS_CODE_SCTP_IPV4 0x0b
2512e689cf4aSJeff Kirsher #define CLASS_CODE_TCP_IPV6 0x0c
2513e689cf4aSJeff Kirsher #define CLASS_CODE_UDP_IPV6 0x0d
2514e689cf4aSJeff Kirsher #define CLASS_CODE_AH_ESP_IPV6 0x0e
2515e689cf4aSJeff Kirsher #define CLASS_CODE_SCTP_IPV6 0x0f
2516e689cf4aSJeff Kirsher #define CLASS_CODE_ARP 0x10
2517e689cf4aSJeff Kirsher #define CLASS_CODE_RARP 0x11
2518e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY2 0x12
2519e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY3 0x13
2520e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY4 0x14
2521e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY5 0x15
2522e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY6 0x16
2523e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY7 0x17
2524e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY8 0x18
2525e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY9 0x19
2526e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY10 0x1a
2527e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY11 0x1b
2528e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY12 0x1c
2529e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY13 0x1d
2530e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY14 0x1e
2531e689cf4aSJeff Kirsher #define CLASS_CODE_DUMMY15 0x1f
2532e689cf4aSJeff Kirsher
2533e689cf4aSJeff Kirsher /* Logical devices and device groups */
2534e689cf4aSJeff Kirsher #define LDN_RXDMA(CHAN) (0 + (CHAN))
2535e689cf4aSJeff Kirsher #define LDN_RESV1(OFF) (16 + (OFF))
2536e689cf4aSJeff Kirsher #define LDN_TXDMA(CHAN) (32 + (CHAN))
2537e689cf4aSJeff Kirsher #define LDN_RESV2(OFF) (56 + (OFF))
2538e689cf4aSJeff Kirsher #define LDN_MIF 63
2539e689cf4aSJeff Kirsher #define LDN_MAC(PORT) (64 + (PORT))
2540e689cf4aSJeff Kirsher #define LDN_DEVICE_ERROR 68
2541e689cf4aSJeff Kirsher #define LDN_MAX LDN_DEVICE_ERROR
2542e689cf4aSJeff Kirsher
2543e689cf4aSJeff Kirsher #define NIU_LDG_MIN 0
2544e689cf4aSJeff Kirsher #define NIU_LDG_MAX 63
2545e689cf4aSJeff Kirsher #define NIU_NUM_LDG 64
2546e689cf4aSJeff Kirsher #define LDG_INVALID 0xff
2547e689cf4aSJeff Kirsher
2548e689cf4aSJeff Kirsher /* PHY stuff */
2549e689cf4aSJeff Kirsher #define NIU_PMA_PMD_DEV_ADDR 1
2550e689cf4aSJeff Kirsher #define NIU_PCS_DEV_ADDR 3
2551e689cf4aSJeff Kirsher
2552e689cf4aSJeff Kirsher #define NIU_PHY_ID_MASK 0xfffff0f0
2553e689cf4aSJeff Kirsher #define NIU_PHY_ID_BCM8704 0x00206030
2554e689cf4aSJeff Kirsher #define NIU_PHY_ID_BCM8706 0x00206035
2555e689cf4aSJeff Kirsher #define NIU_PHY_ID_BCM5464R 0x002060b0
2556e689cf4aSJeff Kirsher #define NIU_PHY_ID_MRVL88X2011 0x01410020
2557e689cf4aSJeff Kirsher
2558e689cf4aSJeff Kirsher /* MRVL88X2011 register addresses */
2559e689cf4aSJeff Kirsher #define MRVL88X2011_USER_DEV1_ADDR 1
2560e689cf4aSJeff Kirsher #define MRVL88X2011_USER_DEV2_ADDR 2
2561e689cf4aSJeff Kirsher #define MRVL88X2011_USER_DEV3_ADDR 3
2562e689cf4aSJeff Kirsher #define MRVL88X2011_USER_DEV4_ADDR 4
2563e689cf4aSJeff Kirsher #define MRVL88X2011_PMA_PMD_CTL_1 0x0000
2564e689cf4aSJeff Kirsher #define MRVL88X2011_PMA_PMD_STATUS_1 0x0001
2565e689cf4aSJeff Kirsher #define MRVL88X2011_10G_PMD_STATUS_2 0x0008
2566e689cf4aSJeff Kirsher #define MRVL88X2011_10G_PMD_TX_DIS 0x0009
2567e689cf4aSJeff Kirsher #define MRVL88X2011_10G_XGXS_LANE_STAT 0x0018
2568e689cf4aSJeff Kirsher #define MRVL88X2011_GENERAL_CTL 0x8300
2569e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLINK_CTL 0x8303
2570e689cf4aSJeff Kirsher #define MRVL88X2011_LED_8_TO_11_CTL 0x8306
2571e689cf4aSJeff Kirsher
2572e689cf4aSJeff Kirsher /* MRVL88X2011 register control */
2573e689cf4aSJeff Kirsher #define MRVL88X2011_ENA_XFPREFCLK 0x0001
2574e689cf4aSJeff Kirsher #define MRVL88X2011_ENA_PMDTX 0x0000
2575e689cf4aSJeff Kirsher #define MRVL88X2011_LOOPBACK 0x1
2576e689cf4aSJeff Kirsher #define MRVL88X2011_LED_ACT 0x1
2577e689cf4aSJeff Kirsher #define MRVL88X2011_LNK_STATUS_OK 0x4
2578e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_MASK 0x70
2579e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_034MS 0x0
2580e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_067MS 0x1
2581e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_134MS 0x2
2582e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_269MS 0x3
2583e689cf4aSJeff Kirsher #define MRVL88X2011_LED_BLKRATE_538MS 0x4
2584e689cf4aSJeff Kirsher #define MRVL88X2011_LED_CTL_OFF 0x0
2585e689cf4aSJeff Kirsher #define MRVL88X2011_LED_CTL_PCS_ACT 0x5
2586e689cf4aSJeff Kirsher #define MRVL88X2011_LED_CTL_MASK 0x7
2587e689cf4aSJeff Kirsher #define MRVL88X2011_LED(n,v) ((v)<<((n)*4))
2588e689cf4aSJeff Kirsher #define MRVL88X2011_LED_STAT(n,v) ((v)>>((n)*4))
2589e689cf4aSJeff Kirsher
2590e689cf4aSJeff Kirsher #define BCM8704_PMA_PMD_DEV_ADDR 1
2591e689cf4aSJeff Kirsher #define BCM8704_PCS_DEV_ADDR 2
2592e689cf4aSJeff Kirsher #define BCM8704_USER_DEV3_ADDR 3
2593e689cf4aSJeff Kirsher #define BCM8704_PHYXS_DEV_ADDR 4
2594e689cf4aSJeff Kirsher #define BCM8704_USER_DEV4_ADDR 4
2595e689cf4aSJeff Kirsher
2596e689cf4aSJeff Kirsher #define BCM8704_PMD_RCV_SIGDET 0x000a
2597e689cf4aSJeff Kirsher #define PMD_RCV_SIGDET_LANE3 0x0010
2598e689cf4aSJeff Kirsher #define PMD_RCV_SIGDET_LANE2 0x0008
2599e689cf4aSJeff Kirsher #define PMD_RCV_SIGDET_LANE1 0x0004
2600e689cf4aSJeff Kirsher #define PMD_RCV_SIGDET_LANE0 0x0002
2601e689cf4aSJeff Kirsher #define PMD_RCV_SIGDET_GLOBAL 0x0001
2602e689cf4aSJeff Kirsher
2603e689cf4aSJeff Kirsher #define BCM8704_PCS_10G_R_STATUS 0x0020
2604e689cf4aSJeff Kirsher #define PCS_10G_R_STATUS_LINKSTAT 0x1000
2605e689cf4aSJeff Kirsher #define PCS_10G_R_STATUS_PRBS31_ABLE 0x0004
2606e689cf4aSJeff Kirsher #define PCS_10G_R_STATUS_HI_BER 0x0002
2607e689cf4aSJeff Kirsher #define PCS_10G_R_STATUS_BLK_LOCK 0x0001
2608e689cf4aSJeff Kirsher
2609e689cf4aSJeff Kirsher #define BCM8704_USER_CONTROL 0xc800
2610e689cf4aSJeff Kirsher #define USER_CONTROL_OPTXENB_LVL 0x8000
2611e689cf4aSJeff Kirsher #define USER_CONTROL_OPTXRST_LVL 0x4000
2612e689cf4aSJeff Kirsher #define USER_CONTROL_OPBIASFLT_LVL 0x2000
2613e689cf4aSJeff Kirsher #define USER_CONTROL_OBTMPFLT_LVL 0x1000
2614e689cf4aSJeff Kirsher #define USER_CONTROL_OPPRFLT_LVL 0x0800
2615e689cf4aSJeff Kirsher #define USER_CONTROL_OPTXFLT_LVL 0x0400
2616e689cf4aSJeff Kirsher #define USER_CONTROL_OPRXLOS_LVL 0x0200
2617e689cf4aSJeff Kirsher #define USER_CONTROL_OPRXFLT_LVL 0x0100
2618e689cf4aSJeff Kirsher #define USER_CONTROL_OPTXON_LVL 0x0080
2619e689cf4aSJeff Kirsher #define USER_CONTROL_RES1 0x007f
2620e689cf4aSJeff Kirsher #define USER_CONTROL_RES1_SHIFT 0
2621e689cf4aSJeff Kirsher
2622e689cf4aSJeff Kirsher #define BCM8704_USER_ANALOG_CLK 0xc801
2623e689cf4aSJeff Kirsher #define BCM8704_USER_PMD_RX_CONTROL 0xc802
2624e689cf4aSJeff Kirsher
2625e689cf4aSJeff Kirsher #define BCM8704_USER_PMD_TX_CONTROL 0xc803
2626e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_RES1 0xfe00
2627e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_XFP_CLKEN 0x0100
2628e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TX_DAC_TXD 0x00c0
2629e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TX_DAC_TXD_SH 6
2630e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TX_DAC_TXCK 0x0030
2631e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TX_DAC_TXCK_SH 4
2632e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TSD_LPWREN 0x0008
2633e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_TSCK_LPWREN 0x0004
2634e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_CMU_LPWREN 0x0002
2635e689cf4aSJeff Kirsher #define USER_PMD_TX_CTL_SFIFORST 0x0001
2636e689cf4aSJeff Kirsher
2637e689cf4aSJeff Kirsher #define BCM8704_USER_ANALOG_STATUS0 0xc804
2638e689cf4aSJeff Kirsher #define BCM8704_USER_OPT_DIGITAL_CTRL 0xc808
2639e689cf4aSJeff Kirsher #define BCM8704_USER_TX_ALARM_STATUS 0x9004
2640e689cf4aSJeff Kirsher
2641e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_FMODE 0x8000
2642e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_TX_PDOWN 0x4000
2643e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_RX_PDOWN 0x2000
2644e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_EFILT_EN 0x1000
2645e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_OPT_RST 0x0800
2646e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_PCS_TIB 0x0400
2647e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_PCS_RI 0x0200
2648e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_RESV1 0x0180
2649e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_GPIOS 0x0060
2650e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_GPIOS_SHIFT 5
2651e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_RESV2 0x0010
2652e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_LB_ERR_DIS 0x0008
2653e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_RESV3 0x0006
2654e689cf4aSJeff Kirsher #define USER_ODIG_CTRL_TXONOFF_PD_DIS 0x0001
2655e689cf4aSJeff Kirsher
2656e689cf4aSJeff Kirsher #define BCM8704_PHYXS_XGXS_LANE_STAT 0x0018
2657e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_ALINGED 0x1000
2658e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_PATTEST 0x0800
2659e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_MAGIC 0x0400
2660e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_LANE3 0x0008
2661e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_LANE2 0x0004
2662e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_LANE1 0x0002
2663e689cf4aSJeff Kirsher #define PHYXS_XGXS_LANE_STAT_LANE0 0x0001
2664e689cf4aSJeff Kirsher
2665e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL 24
2666e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_EXT_LB 0x8000
2667e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_EXT_PLEN 0x4000
2668e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_ER1000 0x3000
2669e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_ER1000_SHIFT 12
2670e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_RESV1 0x0800
2671e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_WRITE_1 0x0400
2672e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_RESV2 0x0300
2673e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_PRESP_DIS 0x0080
2674e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_RESV3 0x0040
2675e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_ER100 0x0030
2676e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_ER100_SHIFT 4
2677e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_DIAG_MODE 0x0008
2678e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_SR_SEL 0x0007
2679e689cf4aSJeff Kirsher #define BCM5464R_AUX_CTL_SR_SEL_SHIFT 0
2680e689cf4aSJeff Kirsher
2681e689cf4aSJeff Kirsher #define BCM5464R_CTRL1000_AS_MASTER 0x0800
2682e689cf4aSJeff Kirsher #define BCM5464R_CTRL1000_ENABLE_AS_MASTER 0x1000
2683e689cf4aSJeff Kirsher
2684e689cf4aSJeff Kirsher #define RCR_ENTRY_MULTI 0x8000000000000000ULL
2685e689cf4aSJeff Kirsher #define RCR_ENTRY_PKT_TYPE 0x6000000000000000ULL
2686e689cf4aSJeff Kirsher #define RCR_ENTRY_PKT_TYPE_SHIFT 61
2687e689cf4aSJeff Kirsher #define RCR_ENTRY_ZERO_COPY 0x1000000000000000ULL
2688e689cf4aSJeff Kirsher #define RCR_ENTRY_NOPORT 0x0800000000000000ULL
2689e689cf4aSJeff Kirsher #define RCR_ENTRY_PROMISC 0x0400000000000000ULL
2690e689cf4aSJeff Kirsher #define RCR_ENTRY_ERROR 0x0380000000000000ULL
2691e689cf4aSJeff Kirsher #define RCR_ENTRY_DCF_ERR 0x0040000000000000ULL
2692e689cf4aSJeff Kirsher #define RCR_ENTRY_L2_LEN 0x003fff0000000000ULL
2693e689cf4aSJeff Kirsher #define RCR_ENTRY_L2_LEN_SHIFT 40
2694e689cf4aSJeff Kirsher #define RCR_ENTRY_PKTBUFSZ 0x000000c000000000ULL
2695e689cf4aSJeff Kirsher #define RCR_ENTRY_PKTBUFSZ_SHIFT 38
2696e689cf4aSJeff Kirsher #define RCR_ENTRY_PKT_BUF_ADDR 0x0000003fffffffffULL /* bits 43:6 */
2697e689cf4aSJeff Kirsher #define RCR_ENTRY_PKT_BUF_ADDR_SHIFT 6
2698e689cf4aSJeff Kirsher
2699e689cf4aSJeff Kirsher #define RCR_PKT_TYPE_OTHER 0x0
2700e689cf4aSJeff Kirsher #define RCR_PKT_TYPE_TCP 0x1
2701e689cf4aSJeff Kirsher #define RCR_PKT_TYPE_UDP 0x2
2702e689cf4aSJeff Kirsher #define RCR_PKT_TYPE_SCTP 0x3
2703e689cf4aSJeff Kirsher
2704e689cf4aSJeff Kirsher #define NIU_RXPULL_MAX ETH_HLEN
2705e689cf4aSJeff Kirsher
2706e689cf4aSJeff Kirsher struct rx_pkt_hdr0 {
2707e689cf4aSJeff Kirsher #if defined(__LITTLE_ENDIAN_BITFIELD)
2708e689cf4aSJeff Kirsher u8 inputport:2,
2709e689cf4aSJeff Kirsher maccheck:1,
2710e689cf4aSJeff Kirsher class:5;
2711e689cf4aSJeff Kirsher u8 vlan:1,
2712e689cf4aSJeff Kirsher llcsnap:1,
2713e689cf4aSJeff Kirsher noport:1,
2714e689cf4aSJeff Kirsher badip:1,
2715e689cf4aSJeff Kirsher tcamhit:1,
2716e689cf4aSJeff Kirsher tres:2,
2717e689cf4aSJeff Kirsher tzfvld:1;
2718e689cf4aSJeff Kirsher #elif defined(__BIG_ENDIAN_BITFIELD)
2719e689cf4aSJeff Kirsher u8 class:5,
2720e689cf4aSJeff Kirsher maccheck:1,
2721e689cf4aSJeff Kirsher inputport:2;
2722e689cf4aSJeff Kirsher u8 tzfvld:1,
2723e689cf4aSJeff Kirsher tres:2,
2724e689cf4aSJeff Kirsher tcamhit:1,
2725e689cf4aSJeff Kirsher badip:1,
2726e689cf4aSJeff Kirsher noport:1,
2727e689cf4aSJeff Kirsher llcsnap:1,
2728e689cf4aSJeff Kirsher vlan:1;
2729e689cf4aSJeff Kirsher #endif
2730e689cf4aSJeff Kirsher };
2731e689cf4aSJeff Kirsher
2732e689cf4aSJeff Kirsher struct rx_pkt_hdr1 {
2733e689cf4aSJeff Kirsher u8 hwrsvd1;
2734e689cf4aSJeff Kirsher u8 tcammatch;
2735e689cf4aSJeff Kirsher #if defined(__LITTLE_ENDIAN_BITFIELD)
2736e689cf4aSJeff Kirsher u8 hwrsvd2:2,
2737e689cf4aSJeff Kirsher hashit:1,
2738e689cf4aSJeff Kirsher exact:1,
2739e689cf4aSJeff Kirsher hzfvld:1,
2740e689cf4aSJeff Kirsher hashsidx:3;
2741e689cf4aSJeff Kirsher #elif defined(__BIG_ENDIAN_BITFIELD)
2742e689cf4aSJeff Kirsher u8 hashsidx:3,
2743e689cf4aSJeff Kirsher hzfvld:1,
2744e689cf4aSJeff Kirsher exact:1,
2745e689cf4aSJeff Kirsher hashit:1,
2746e689cf4aSJeff Kirsher hwrsvd2:2;
2747e689cf4aSJeff Kirsher #endif
2748e689cf4aSJeff Kirsher u8 zcrsvd;
2749e689cf4aSJeff Kirsher
2750e689cf4aSJeff Kirsher /* Bits 11:8 of zero copy flow ID. */
2751e689cf4aSJeff Kirsher #if defined(__LITTLE_ENDIAN_BITFIELD)
2752e689cf4aSJeff Kirsher u8 hwrsvd3:4, zflowid0:4;
2753e689cf4aSJeff Kirsher #elif defined(__BIG_ENDIAN_BITFIELD)
2754e689cf4aSJeff Kirsher u8 zflowid0:4, hwrsvd3:4;
2755e689cf4aSJeff Kirsher #endif
2756e689cf4aSJeff Kirsher
2757e689cf4aSJeff Kirsher /* Bits 7:0 of zero copy flow ID. */
2758e689cf4aSJeff Kirsher u8 zflowid1;
2759e689cf4aSJeff Kirsher
2760e689cf4aSJeff Kirsher /* Bits 15:8 of hash value, H2. */
2761e689cf4aSJeff Kirsher u8 hashval2_0;
2762e689cf4aSJeff Kirsher
2763e689cf4aSJeff Kirsher /* Bits 7:0 of hash value, H2. */
2764e689cf4aSJeff Kirsher u8 hashval2_1;
2765e689cf4aSJeff Kirsher
2766e689cf4aSJeff Kirsher /* Bits 19:16 of hash value, H1. */
2767e689cf4aSJeff Kirsher #if defined(__LITTLE_ENDIAN_BITFIELD)
2768e689cf4aSJeff Kirsher u8 hwrsvd4:4, hashval1_0:4;
2769e689cf4aSJeff Kirsher #elif defined(__BIG_ENDIAN_BITFIELD)
2770e689cf4aSJeff Kirsher u8 hashval1_0:4, hwrsvd4:4;
2771e689cf4aSJeff Kirsher #endif
2772e689cf4aSJeff Kirsher
2773e689cf4aSJeff Kirsher /* Bits 15:8 of hash value, H1. */
2774e689cf4aSJeff Kirsher u8 hashval1_1;
2775e689cf4aSJeff Kirsher
2776e689cf4aSJeff Kirsher /* Bits 7:0 of hash value, H1. */
2777e689cf4aSJeff Kirsher u8 hashval1_2;
2778e689cf4aSJeff Kirsher
2779e689cf4aSJeff Kirsher u8 hwrsvd5;
2780e689cf4aSJeff Kirsher u8 hwrsvd6;
2781e689cf4aSJeff Kirsher
2782e689cf4aSJeff Kirsher u8 usrdata_0; /* Bits 39:32 of user data. */
2783e689cf4aSJeff Kirsher u8 usrdata_1; /* Bits 31:24 of user data. */
2784e689cf4aSJeff Kirsher u8 usrdata_2; /* Bits 23:16 of user data. */
2785e689cf4aSJeff Kirsher u8 usrdata_3; /* Bits 15:8 of user data. */
2786e689cf4aSJeff Kirsher u8 usrdata_4; /* Bits 7:0 of user data. */
2787e689cf4aSJeff Kirsher };
2788e689cf4aSJeff Kirsher
2789e689cf4aSJeff Kirsher struct tx_dma_mbox {
2790e689cf4aSJeff Kirsher u64 tx_dma_pre_st;
2791e689cf4aSJeff Kirsher u64 tx_cs;
2792e689cf4aSJeff Kirsher u64 tx_ring_kick;
2793e689cf4aSJeff Kirsher u64 tx_ring_hdl;
2794e689cf4aSJeff Kirsher u64 resv1;
2795e689cf4aSJeff Kirsher u32 tx_rng_err_logl;
2796e689cf4aSJeff Kirsher u32 tx_rng_err_logh;
2797e689cf4aSJeff Kirsher u64 resv2;
2798e689cf4aSJeff Kirsher u64 resv3;
2799e689cf4aSJeff Kirsher };
2800e689cf4aSJeff Kirsher
2801e689cf4aSJeff Kirsher struct tx_pkt_hdr {
2802e689cf4aSJeff Kirsher __le64 flags;
2803e689cf4aSJeff Kirsher #define TXHDR_PAD 0x0000000000000007ULL
2804e689cf4aSJeff Kirsher #define TXHDR_PAD_SHIFT 0
2805e689cf4aSJeff Kirsher #define TXHDR_LEN 0x000000003fff0000ULL
2806e689cf4aSJeff Kirsher #define TXHDR_LEN_SHIFT 16
2807e689cf4aSJeff Kirsher #define TXHDR_L4STUFF 0x0000003f00000000ULL
2808e689cf4aSJeff Kirsher #define TXHDR_L4STUFF_SHIFT 32
2809e689cf4aSJeff Kirsher #define TXHDR_L4START 0x00003f0000000000ULL
2810e689cf4aSJeff Kirsher #define TXHDR_L4START_SHIFT 40
2811e689cf4aSJeff Kirsher #define TXHDR_L3START 0x000f000000000000ULL
2812e689cf4aSJeff Kirsher #define TXHDR_L3START_SHIFT 48
2813e689cf4aSJeff Kirsher #define TXHDR_IHL 0x00f0000000000000ULL
2814e689cf4aSJeff Kirsher #define TXHDR_IHL_SHIFT 52
2815e689cf4aSJeff Kirsher #define TXHDR_VLAN 0x0100000000000000ULL
2816e689cf4aSJeff Kirsher #define TXHDR_LLC 0x0200000000000000ULL
2817e689cf4aSJeff Kirsher #define TXHDR_IP_VER 0x2000000000000000ULL
2818e689cf4aSJeff Kirsher #define TXHDR_CSUM_NONE 0x0000000000000000ULL
2819e689cf4aSJeff Kirsher #define TXHDR_CSUM_TCP 0x4000000000000000ULL
2820e689cf4aSJeff Kirsher #define TXHDR_CSUM_UDP 0x8000000000000000ULL
2821e689cf4aSJeff Kirsher #define TXHDR_CSUM_SCTP 0xc000000000000000ULL
2822e689cf4aSJeff Kirsher __le64 resv;
2823e689cf4aSJeff Kirsher };
2824e689cf4aSJeff Kirsher
2825e689cf4aSJeff Kirsher #define TX_DESC_SOP 0x8000000000000000ULL
2826e689cf4aSJeff Kirsher #define TX_DESC_MARK 0x4000000000000000ULL
2827e689cf4aSJeff Kirsher #define TX_DESC_NUM_PTR 0x3c00000000000000ULL
2828e689cf4aSJeff Kirsher #define TX_DESC_NUM_PTR_SHIFT 58
2829e689cf4aSJeff Kirsher #define TX_DESC_TR_LEN 0x01fff00000000000ULL
2830e689cf4aSJeff Kirsher #define TX_DESC_TR_LEN_SHIFT 44
2831e689cf4aSJeff Kirsher #define TX_DESC_SAD 0x00000fffffffffffULL
2832e689cf4aSJeff Kirsher #define TX_DESC_SAD_SHIFT 0
2833e689cf4aSJeff Kirsher
2834e689cf4aSJeff Kirsher struct tx_buff_info {
2835e689cf4aSJeff Kirsher struct sk_buff *skb;
2836e689cf4aSJeff Kirsher u64 mapping;
2837e689cf4aSJeff Kirsher };
2838e689cf4aSJeff Kirsher
2839e689cf4aSJeff Kirsher struct txdma_mailbox {
2840e689cf4aSJeff Kirsher __le64 tx_dma_pre_st;
2841e689cf4aSJeff Kirsher __le64 tx_cs;
2842e689cf4aSJeff Kirsher __le64 tx_ring_kick;
2843e689cf4aSJeff Kirsher __le64 tx_ring_hdl;
2844e689cf4aSJeff Kirsher __le64 resv1;
2845e689cf4aSJeff Kirsher __le32 tx_rng_err_logl;
2846e689cf4aSJeff Kirsher __le32 tx_rng_err_logh;
2847e689cf4aSJeff Kirsher __le64 resv2[2];
2848e689cf4aSJeff Kirsher } __attribute__((aligned(64)));
2849e689cf4aSJeff Kirsher
2850e689cf4aSJeff Kirsher #define MAX_TX_RING_SIZE 256
2851e689cf4aSJeff Kirsher #define MAX_TX_DESC_LEN 4076
2852e689cf4aSJeff Kirsher
2853e689cf4aSJeff Kirsher struct tx_ring_info {
2854e689cf4aSJeff Kirsher struct tx_buff_info tx_buffs[MAX_TX_RING_SIZE];
2855e689cf4aSJeff Kirsher struct niu *np;
2856e689cf4aSJeff Kirsher u64 tx_cs;
2857e689cf4aSJeff Kirsher int pending;
2858e689cf4aSJeff Kirsher int prod;
2859e689cf4aSJeff Kirsher int cons;
2860e689cf4aSJeff Kirsher int wrap_bit;
2861e689cf4aSJeff Kirsher u16 last_pkt_cnt;
2862e689cf4aSJeff Kirsher u16 tx_channel;
2863e689cf4aSJeff Kirsher u16 mark_counter;
2864e689cf4aSJeff Kirsher u16 mark_freq;
2865e689cf4aSJeff Kirsher u16 mark_pending;
2866e689cf4aSJeff Kirsher u16 __pad;
2867e689cf4aSJeff Kirsher struct txdma_mailbox *mbox;
2868e689cf4aSJeff Kirsher __le64 *descr;
2869e689cf4aSJeff Kirsher
2870e689cf4aSJeff Kirsher u64 tx_packets;
2871e689cf4aSJeff Kirsher u64 tx_bytes;
2872e689cf4aSJeff Kirsher u64 tx_errors;
2873e689cf4aSJeff Kirsher
2874e689cf4aSJeff Kirsher u64 mbox_dma;
2875e689cf4aSJeff Kirsher u64 descr_dma;
2876e689cf4aSJeff Kirsher int max_burst;
2877e689cf4aSJeff Kirsher };
2878e689cf4aSJeff Kirsher
2879e689cf4aSJeff Kirsher #define NEXT_TX(tp, index) \
2880e689cf4aSJeff Kirsher (((index) + 1) < (tp)->pending ? ((index) + 1) : 0)
2881e689cf4aSJeff Kirsher
niu_tx_avail(struct tx_ring_info * tp)2882e689cf4aSJeff Kirsher static inline u32 niu_tx_avail(struct tx_ring_info *tp)
2883e689cf4aSJeff Kirsher {
2884e689cf4aSJeff Kirsher return (tp->pending -
2885e689cf4aSJeff Kirsher ((tp->prod - tp->cons) & (MAX_TX_RING_SIZE - 1)));
2886e689cf4aSJeff Kirsher }
2887e689cf4aSJeff Kirsher
2888e689cf4aSJeff Kirsher struct rxdma_mailbox {
2889e689cf4aSJeff Kirsher __le64 rx_dma_ctl_stat;
2890e689cf4aSJeff Kirsher __le64 rbr_stat;
2891e689cf4aSJeff Kirsher __le32 rbr_hdl;
2892e689cf4aSJeff Kirsher __le32 rbr_hdh;
2893e689cf4aSJeff Kirsher __le64 resv1;
2894e689cf4aSJeff Kirsher __le32 rcrstat_c;
2895e689cf4aSJeff Kirsher __le32 rcrstat_b;
2896e689cf4aSJeff Kirsher __le64 rcrstat_a;
2897e689cf4aSJeff Kirsher __le64 resv2[2];
2898e689cf4aSJeff Kirsher } __attribute__((aligned(64)));
2899e689cf4aSJeff Kirsher
2900e689cf4aSJeff Kirsher #define MAX_RBR_RING_SIZE 128
2901e689cf4aSJeff Kirsher #define MAX_RCR_RING_SIZE (MAX_RBR_RING_SIZE * 2)
2902e689cf4aSJeff Kirsher
2903e689cf4aSJeff Kirsher #define RBR_REFILL_MIN 16
2904e689cf4aSJeff Kirsher
2905e689cf4aSJeff Kirsher #define RX_SKB_ALLOC_SIZE 128 + NET_IP_ALIGN
2906e689cf4aSJeff Kirsher
2907e689cf4aSJeff Kirsher struct rx_ring_info {
2908e689cf4aSJeff Kirsher struct niu *np;
2909e689cf4aSJeff Kirsher int rx_channel;
2910e689cf4aSJeff Kirsher u16 rbr_block_size;
2911e689cf4aSJeff Kirsher u16 rbr_blocks_per_page;
2912e689cf4aSJeff Kirsher u16 rbr_sizes[4];
2913e689cf4aSJeff Kirsher unsigned int rcr_index;
2914e689cf4aSJeff Kirsher unsigned int rcr_table_size;
2915e689cf4aSJeff Kirsher unsigned int rbr_index;
2916e689cf4aSJeff Kirsher unsigned int rbr_pending;
2917e689cf4aSJeff Kirsher unsigned int rbr_refill_pending;
2918e689cf4aSJeff Kirsher unsigned int rbr_kick_thresh;
2919e689cf4aSJeff Kirsher unsigned int rbr_table_size;
2920e689cf4aSJeff Kirsher struct page **rxhash;
2921e689cf4aSJeff Kirsher struct rxdma_mailbox *mbox;
2922e689cf4aSJeff Kirsher __le64 *rcr;
2923e689cf4aSJeff Kirsher __le32 *rbr;
2924e689cf4aSJeff Kirsher #define RBR_DESCR_ADDR_SHIFT 12
2925e689cf4aSJeff Kirsher
2926e689cf4aSJeff Kirsher u64 rx_packets;
2927e689cf4aSJeff Kirsher u64 rx_bytes;
2928e689cf4aSJeff Kirsher u64 rx_dropped;
2929e689cf4aSJeff Kirsher u64 rx_errors;
2930e689cf4aSJeff Kirsher
2931e689cf4aSJeff Kirsher u64 mbox_dma;
2932e689cf4aSJeff Kirsher u64 rcr_dma;
2933e689cf4aSJeff Kirsher u64 rbr_dma;
2934e689cf4aSJeff Kirsher
2935e689cf4aSJeff Kirsher /* WRED */
2936e689cf4aSJeff Kirsher int nonsyn_window;
2937e689cf4aSJeff Kirsher int nonsyn_threshold;
2938e689cf4aSJeff Kirsher int syn_window;
2939e689cf4aSJeff Kirsher int syn_threshold;
2940e689cf4aSJeff Kirsher
2941e689cf4aSJeff Kirsher /* interrupt mitigation */
2942e689cf4aSJeff Kirsher int rcr_pkt_threshold;
2943e689cf4aSJeff Kirsher int rcr_timeout;
2944e689cf4aSJeff Kirsher };
2945e689cf4aSJeff Kirsher
2946e689cf4aSJeff Kirsher #define NEXT_RCR(rp, index) \
2947e689cf4aSJeff Kirsher (((index) + 1) < (rp)->rcr_table_size ? ((index) + 1) : 0)
2948e689cf4aSJeff Kirsher #define NEXT_RBR(rp, index) \
2949e689cf4aSJeff Kirsher (((index) + 1) < (rp)->rbr_table_size ? ((index) + 1) : 0)
2950e689cf4aSJeff Kirsher
2951e689cf4aSJeff Kirsher #define NIU_MAX_PORTS 4
2952e689cf4aSJeff Kirsher #define NIU_NUM_RXCHAN 16
2953e689cf4aSJeff Kirsher #define NIU_NUM_TXCHAN 24
2954e689cf4aSJeff Kirsher #define MAC_NUM_HASH 16
2955e689cf4aSJeff Kirsher
2956e689cf4aSJeff Kirsher #define NIU_MAX_MTU 9216
2957e689cf4aSJeff Kirsher
2958e689cf4aSJeff Kirsher /* VPD strings */
2959e689cf4aSJeff Kirsher #define NIU_QGC_LP_BM_STR "501-7606"
2960e689cf4aSJeff Kirsher #define NIU_2XGF_LP_BM_STR "501-7283"
2961e689cf4aSJeff Kirsher #define NIU_QGC_PEM_BM_STR "501-7765"
2962e689cf4aSJeff Kirsher #define NIU_2XGF_PEM_BM_STR "501-7626"
2963e689cf4aSJeff Kirsher #define NIU_ALONSO_BM_STR "373-0202"
2964e689cf4aSJeff Kirsher #define NIU_FOXXY_BM_STR "501-7961"
2965e689cf4aSJeff Kirsher #define NIU_2XGF_MRVL_BM_STR "SK-6E82"
2966e689cf4aSJeff Kirsher #define NIU_QGC_LP_MDL_STR "SUNW,pcie-qgc"
2967e689cf4aSJeff Kirsher #define NIU_2XGF_LP_MDL_STR "SUNW,pcie-2xgf"
2968e689cf4aSJeff Kirsher #define NIU_QGC_PEM_MDL_STR "SUNW,pcie-qgc-pem"
2969e689cf4aSJeff Kirsher #define NIU_2XGF_PEM_MDL_STR "SUNW,pcie-2xgf-pem"
2970e689cf4aSJeff Kirsher #define NIU_ALONSO_MDL_STR "SUNW,CP3220"
2971e689cf4aSJeff Kirsher #define NIU_KIMI_MDL_STR "SUNW,CP3260"
2972e689cf4aSJeff Kirsher #define NIU_MARAMBA_MDL_STR "SUNW,pcie-neptune"
2973e689cf4aSJeff Kirsher #define NIU_FOXXY_MDL_STR "SUNW,pcie-rfem"
2974e689cf4aSJeff Kirsher #define NIU_2XGF_MRVL_MDL_STR "SysKonnect,pcie-2xgf"
2975e689cf4aSJeff Kirsher
2976e689cf4aSJeff Kirsher #define NIU_VPD_MIN_MAJOR 3
2977e689cf4aSJeff Kirsher #define NIU_VPD_MIN_MINOR 4
2978e689cf4aSJeff Kirsher
2979e689cf4aSJeff Kirsher #define NIU_VPD_MODEL_MAX 32
2980e689cf4aSJeff Kirsher #define NIU_VPD_BD_MODEL_MAX 16
2981e689cf4aSJeff Kirsher #define NIU_VPD_VERSION_MAX 64
2982e689cf4aSJeff Kirsher #define NIU_VPD_PHY_TYPE_MAX 8
2983e689cf4aSJeff Kirsher
2984e689cf4aSJeff Kirsher struct niu_vpd {
2985e689cf4aSJeff Kirsher char model[NIU_VPD_MODEL_MAX];
2986e689cf4aSJeff Kirsher char board_model[NIU_VPD_BD_MODEL_MAX];
2987e689cf4aSJeff Kirsher char version[NIU_VPD_VERSION_MAX];
2988e689cf4aSJeff Kirsher char phy_type[NIU_VPD_PHY_TYPE_MAX];
2989e689cf4aSJeff Kirsher u8 mac_num;
2990e689cf4aSJeff Kirsher u8 __pad;
2991e689cf4aSJeff Kirsher u8 local_mac[6];
2992e689cf4aSJeff Kirsher int fcode_major;
2993e689cf4aSJeff Kirsher int fcode_minor;
2994e689cf4aSJeff Kirsher };
2995e689cf4aSJeff Kirsher
2996e689cf4aSJeff Kirsher struct niu_altmac_rdc {
2997e689cf4aSJeff Kirsher u8 alt_mac_num;
2998e689cf4aSJeff Kirsher u8 rdc_num;
2999e689cf4aSJeff Kirsher u8 mac_pref;
3000e689cf4aSJeff Kirsher };
3001e689cf4aSJeff Kirsher
3002e689cf4aSJeff Kirsher struct niu_vlan_rdc {
3003e689cf4aSJeff Kirsher u8 rdc_num;
3004e689cf4aSJeff Kirsher u8 vlan_pref;
3005e689cf4aSJeff Kirsher };
3006e689cf4aSJeff Kirsher
3007e689cf4aSJeff Kirsher struct niu_classifier {
3008e689cf4aSJeff Kirsher struct niu_altmac_rdc alt_mac_mappings[16];
3009e689cf4aSJeff Kirsher struct niu_vlan_rdc vlan_mappings[ENET_VLAN_TBL_NUM_ENTRIES];
3010e689cf4aSJeff Kirsher
3011e689cf4aSJeff Kirsher u16 tcam_top;
3012e689cf4aSJeff Kirsher u16 tcam_sz;
3013e689cf4aSJeff Kirsher u16 tcam_valid_entries;
3014e689cf4aSJeff Kirsher u16 num_alt_mac_mappings;
3015e689cf4aSJeff Kirsher
3016e689cf4aSJeff Kirsher u32 h1_init;
3017e689cf4aSJeff Kirsher u16 h2_init;
3018e689cf4aSJeff Kirsher };
3019e689cf4aSJeff Kirsher
3020e689cf4aSJeff Kirsher #define NIU_NUM_RDC_TABLES 8
3021e689cf4aSJeff Kirsher #define NIU_RDC_TABLE_SLOTS 16
3022e689cf4aSJeff Kirsher
3023e689cf4aSJeff Kirsher struct rdc_table {
3024e689cf4aSJeff Kirsher u8 rxdma_channel[NIU_RDC_TABLE_SLOTS];
3025e689cf4aSJeff Kirsher };
3026e689cf4aSJeff Kirsher
3027e689cf4aSJeff Kirsher struct niu_rdc_tables {
3028e689cf4aSJeff Kirsher struct rdc_table tables[NIU_NUM_RDC_TABLES];
3029e689cf4aSJeff Kirsher int first_table_num;
3030e689cf4aSJeff Kirsher int num_tables;
3031e689cf4aSJeff Kirsher };
3032e689cf4aSJeff Kirsher
3033e689cf4aSJeff Kirsher #define PHY_TYPE_PMA_PMD 0
3034e689cf4aSJeff Kirsher #define PHY_TYPE_PCS 1
3035e689cf4aSJeff Kirsher #define PHY_TYPE_MII 2
3036e689cf4aSJeff Kirsher #define PHY_TYPE_MAX 3
3037e689cf4aSJeff Kirsher
3038e689cf4aSJeff Kirsher struct phy_probe_info {
3039e689cf4aSJeff Kirsher u32 phy_id[PHY_TYPE_MAX][NIU_MAX_PORTS];
3040e689cf4aSJeff Kirsher u8 phy_port[PHY_TYPE_MAX][NIU_MAX_PORTS];
3041e689cf4aSJeff Kirsher u8 cur[PHY_TYPE_MAX];
3042e689cf4aSJeff Kirsher
3043e689cf4aSJeff Kirsher struct device_attribute phy_port_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3044e689cf4aSJeff Kirsher struct device_attribute phy_type_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3045e689cf4aSJeff Kirsher struct device_attribute phy_id_attrs[PHY_TYPE_MAX * NIU_MAX_PORTS];
3046e689cf4aSJeff Kirsher };
3047e689cf4aSJeff Kirsher
3048e689cf4aSJeff Kirsher struct niu_tcam_entry {
3049e689cf4aSJeff Kirsher u8 valid;
3050e689cf4aSJeff Kirsher u64 key[4];
3051e689cf4aSJeff Kirsher u64 key_mask[4];
3052e689cf4aSJeff Kirsher u64 assoc_data;
3053e689cf4aSJeff Kirsher };
3054e689cf4aSJeff Kirsher
3055e689cf4aSJeff Kirsher struct device_node;
3056e689cf4aSJeff Kirsher union niu_parent_id {
3057e689cf4aSJeff Kirsher struct {
3058e689cf4aSJeff Kirsher int domain;
3059e689cf4aSJeff Kirsher int bus;
3060e689cf4aSJeff Kirsher int device;
3061e689cf4aSJeff Kirsher } pci;
3062e689cf4aSJeff Kirsher struct device_node *of;
3063e689cf4aSJeff Kirsher };
3064e689cf4aSJeff Kirsher
3065e689cf4aSJeff Kirsher struct niu;
3066e689cf4aSJeff Kirsher struct niu_parent {
3067e689cf4aSJeff Kirsher struct platform_device *plat_dev;
3068e689cf4aSJeff Kirsher int index;
3069e689cf4aSJeff Kirsher
3070e689cf4aSJeff Kirsher union niu_parent_id id;
3071e689cf4aSJeff Kirsher
3072e689cf4aSJeff Kirsher struct niu *ports[NIU_MAX_PORTS];
3073e689cf4aSJeff Kirsher
3074e689cf4aSJeff Kirsher atomic_t refcnt;
3075e689cf4aSJeff Kirsher struct list_head list;
3076e689cf4aSJeff Kirsher
3077e689cf4aSJeff Kirsher spinlock_t lock;
3078e689cf4aSJeff Kirsher
3079e689cf4aSJeff Kirsher u32 flags;
3080e689cf4aSJeff Kirsher #define PARENT_FLGS_CLS_HWINIT 0x00000001
3081e689cf4aSJeff Kirsher
3082e689cf4aSJeff Kirsher u32 port_phy;
3083e689cf4aSJeff Kirsher #define PORT_PHY_UNKNOWN 0x00000000
3084e689cf4aSJeff Kirsher #define PORT_PHY_INVALID 0xffffffff
3085e689cf4aSJeff Kirsher #define PORT_TYPE_10G 0x01
3086e689cf4aSJeff Kirsher #define PORT_TYPE_1G 0x02
3087e689cf4aSJeff Kirsher #define PORT_TYPE_MASK 0x03
3088e689cf4aSJeff Kirsher
3089e689cf4aSJeff Kirsher u8 rxchan_per_port[NIU_MAX_PORTS];
3090e689cf4aSJeff Kirsher u8 txchan_per_port[NIU_MAX_PORTS];
3091e689cf4aSJeff Kirsher
3092e689cf4aSJeff Kirsher struct niu_rdc_tables rdc_group_cfg[NIU_MAX_PORTS];
3093e689cf4aSJeff Kirsher u8 rdc_default[NIU_MAX_PORTS];
3094e689cf4aSJeff Kirsher
3095e689cf4aSJeff Kirsher u8 ldg_map[LDN_MAX + 1];
3096e689cf4aSJeff Kirsher
3097e689cf4aSJeff Kirsher u8 plat_type;
3098e689cf4aSJeff Kirsher #define PLAT_TYPE_INVALID 0x00
3099e689cf4aSJeff Kirsher #define PLAT_TYPE_ATLAS 0x01
3100e689cf4aSJeff Kirsher #define PLAT_TYPE_NIU 0x02
3101e689cf4aSJeff Kirsher #define PLAT_TYPE_VF_P0 0x03
3102e689cf4aSJeff Kirsher #define PLAT_TYPE_VF_P1 0x04
3103e689cf4aSJeff Kirsher #define PLAT_TYPE_ATCA_CP3220 0x08
3104e689cf4aSJeff Kirsher
3105e689cf4aSJeff Kirsher u8 num_ports;
3106e689cf4aSJeff Kirsher
3107e689cf4aSJeff Kirsher u16 tcam_num_entries;
3108e689cf4aSJeff Kirsher #define NIU_PCI_TCAM_ENTRIES 256
3109e689cf4aSJeff Kirsher #define NIU_NONPCI_TCAM_ENTRIES 128
3110e689cf4aSJeff Kirsher #define NIU_TCAM_ENTRIES_MAX 256
3111e689cf4aSJeff Kirsher
3112e689cf4aSJeff Kirsher int rxdma_clock_divider;
3113e689cf4aSJeff Kirsher
3114e689cf4aSJeff Kirsher struct phy_probe_info phy_probe_info;
3115e689cf4aSJeff Kirsher
3116e689cf4aSJeff Kirsher struct niu_tcam_entry tcam[NIU_TCAM_ENTRIES_MAX];
3117e689cf4aSJeff Kirsher
3118e689cf4aSJeff Kirsher #define NIU_L2_PROG_CLS 2
3119e689cf4aSJeff Kirsher #define NIU_L3_PROG_CLS 4
3120e689cf4aSJeff Kirsher u64 l2_cls[NIU_L2_PROG_CLS];
3121e689cf4aSJeff Kirsher u64 l3_cls[NIU_L3_PROG_CLS];
3122e689cf4aSJeff Kirsher u64 tcam_key[12];
3123e689cf4aSJeff Kirsher u64 flow_key[12];
3124e689cf4aSJeff Kirsher u16 l3_cls_refcnt[NIU_L3_PROG_CLS];
3125e689cf4aSJeff Kirsher u8 l3_cls_pid[NIU_L3_PROG_CLS];
3126e689cf4aSJeff Kirsher };
3127e689cf4aSJeff Kirsher
3128e689cf4aSJeff Kirsher struct niu_ops {
3129e689cf4aSJeff Kirsher void *(*alloc_coherent)(struct device *dev, size_t size,
3130e689cf4aSJeff Kirsher u64 *handle, gfp_t flag);
3131e689cf4aSJeff Kirsher void (*free_coherent)(struct device *dev, size_t size,
3132e689cf4aSJeff Kirsher void *cpu_addr, u64 handle);
3133e689cf4aSJeff Kirsher u64 (*map_page)(struct device *dev, struct page *page,
3134e689cf4aSJeff Kirsher unsigned long offset, size_t size,
3135e689cf4aSJeff Kirsher enum dma_data_direction direction);
3136e689cf4aSJeff Kirsher void (*unmap_page)(struct device *dev, u64 dma_address,
3137e689cf4aSJeff Kirsher size_t size, enum dma_data_direction direction);
3138e689cf4aSJeff Kirsher u64 (*map_single)(struct device *dev, void *cpu_addr,
3139e689cf4aSJeff Kirsher size_t size,
3140e689cf4aSJeff Kirsher enum dma_data_direction direction);
3141e689cf4aSJeff Kirsher void (*unmap_single)(struct device *dev, u64 dma_address,
3142e689cf4aSJeff Kirsher size_t size, enum dma_data_direction direction);
3143e689cf4aSJeff Kirsher };
3144e689cf4aSJeff Kirsher
3145e689cf4aSJeff Kirsher struct niu_link_config {
3146e689cf4aSJeff Kirsher u32 supported;
3147e689cf4aSJeff Kirsher
3148e689cf4aSJeff Kirsher /* Describes what we're trying to get. */
3149e689cf4aSJeff Kirsher u32 advertising;
3150e689cf4aSJeff Kirsher u16 speed;
3151e689cf4aSJeff Kirsher u8 duplex;
3152e689cf4aSJeff Kirsher u8 autoneg;
3153e689cf4aSJeff Kirsher
3154e689cf4aSJeff Kirsher /* Describes what we actually have. */
3155e689cf4aSJeff Kirsher u32 active_advertising;
3156e689cf4aSJeff Kirsher u16 active_speed;
3157e689cf4aSJeff Kirsher u8 active_duplex;
3158e689cf4aSJeff Kirsher u8 active_autoneg;
3159e689cf4aSJeff Kirsher #define SPEED_INVALID 0xffff
3160e689cf4aSJeff Kirsher #define DUPLEX_INVALID 0xff
3161e689cf4aSJeff Kirsher #define AUTONEG_INVALID 0xff
3162e689cf4aSJeff Kirsher
3163e689cf4aSJeff Kirsher u8 loopback_mode;
3164e689cf4aSJeff Kirsher #define LOOPBACK_DISABLED 0x00
3165e689cf4aSJeff Kirsher #define LOOPBACK_PHY 0x01
3166e689cf4aSJeff Kirsher #define LOOPBACK_MAC 0x02
3167e689cf4aSJeff Kirsher };
3168e689cf4aSJeff Kirsher
3169e689cf4aSJeff Kirsher struct niu_ldg {
3170e689cf4aSJeff Kirsher struct napi_struct napi;
3171e689cf4aSJeff Kirsher struct niu *np;
3172e689cf4aSJeff Kirsher u8 ldg_num;
3173e689cf4aSJeff Kirsher u8 timer;
3174e689cf4aSJeff Kirsher u64 v0, v1, v2;
3175e689cf4aSJeff Kirsher unsigned int irq;
3176e689cf4aSJeff Kirsher };
3177e689cf4aSJeff Kirsher
3178e689cf4aSJeff Kirsher struct niu_xmac_stats {
3179e689cf4aSJeff Kirsher u64 tx_frames;
3180e689cf4aSJeff Kirsher u64 tx_bytes;
3181e689cf4aSJeff Kirsher u64 tx_fifo_errors;
3182e689cf4aSJeff Kirsher u64 tx_overflow_errors;
3183e689cf4aSJeff Kirsher u64 tx_max_pkt_size_errors;
3184e689cf4aSJeff Kirsher u64 tx_underflow_errors;
3185e689cf4aSJeff Kirsher
3186e689cf4aSJeff Kirsher u64 rx_local_faults;
3187e689cf4aSJeff Kirsher u64 rx_remote_faults;
3188e689cf4aSJeff Kirsher u64 rx_link_faults;
3189e689cf4aSJeff Kirsher u64 rx_align_errors;
3190e689cf4aSJeff Kirsher u64 rx_frags;
3191e689cf4aSJeff Kirsher u64 rx_mcasts;
3192e689cf4aSJeff Kirsher u64 rx_bcasts;
3193e689cf4aSJeff Kirsher u64 rx_hist_cnt1;
3194e689cf4aSJeff Kirsher u64 rx_hist_cnt2;
3195e689cf4aSJeff Kirsher u64 rx_hist_cnt3;
3196e689cf4aSJeff Kirsher u64 rx_hist_cnt4;
3197e689cf4aSJeff Kirsher u64 rx_hist_cnt5;
3198e689cf4aSJeff Kirsher u64 rx_hist_cnt6;
3199e689cf4aSJeff Kirsher u64 rx_hist_cnt7;
3200e689cf4aSJeff Kirsher u64 rx_octets;
3201e689cf4aSJeff Kirsher u64 rx_code_violations;
3202e689cf4aSJeff Kirsher u64 rx_len_errors;
3203e689cf4aSJeff Kirsher u64 rx_crc_errors;
3204e689cf4aSJeff Kirsher u64 rx_underflows;
3205e689cf4aSJeff Kirsher u64 rx_overflows;
3206e689cf4aSJeff Kirsher
3207e689cf4aSJeff Kirsher u64 pause_off_state;
3208e689cf4aSJeff Kirsher u64 pause_on_state;
3209e689cf4aSJeff Kirsher u64 pause_received;
3210e689cf4aSJeff Kirsher };
3211e689cf4aSJeff Kirsher
3212e689cf4aSJeff Kirsher struct niu_bmac_stats {
3213e689cf4aSJeff Kirsher u64 tx_underflow_errors;
3214e689cf4aSJeff Kirsher u64 tx_max_pkt_size_errors;
3215e689cf4aSJeff Kirsher u64 tx_bytes;
3216e689cf4aSJeff Kirsher u64 tx_frames;
3217e689cf4aSJeff Kirsher
3218e689cf4aSJeff Kirsher u64 rx_overflows;
3219e689cf4aSJeff Kirsher u64 rx_frames;
3220e689cf4aSJeff Kirsher u64 rx_align_errors;
3221e689cf4aSJeff Kirsher u64 rx_crc_errors;
3222e689cf4aSJeff Kirsher u64 rx_len_errors;
3223e689cf4aSJeff Kirsher
3224e689cf4aSJeff Kirsher u64 pause_off_state;
3225e689cf4aSJeff Kirsher u64 pause_on_state;
3226e689cf4aSJeff Kirsher u64 pause_received;
3227e689cf4aSJeff Kirsher };
3228e689cf4aSJeff Kirsher
3229e689cf4aSJeff Kirsher union niu_mac_stats {
3230e689cf4aSJeff Kirsher struct niu_xmac_stats xmac;
3231e689cf4aSJeff Kirsher struct niu_bmac_stats bmac;
3232e689cf4aSJeff Kirsher };
3233e689cf4aSJeff Kirsher
3234e689cf4aSJeff Kirsher struct niu_phy_ops {
3235e689cf4aSJeff Kirsher int (*serdes_init)(struct niu *np);
3236e689cf4aSJeff Kirsher int (*xcvr_init)(struct niu *np);
3237e689cf4aSJeff Kirsher int (*link_status)(struct niu *np, int *);
3238e689cf4aSJeff Kirsher };
3239e689cf4aSJeff Kirsher
3240e689cf4aSJeff Kirsher struct platform_device;
3241e689cf4aSJeff Kirsher struct niu {
3242e689cf4aSJeff Kirsher void __iomem *regs;
3243e689cf4aSJeff Kirsher struct net_device *dev;
3244e689cf4aSJeff Kirsher struct pci_dev *pdev;
3245e689cf4aSJeff Kirsher struct device *device;
3246e689cf4aSJeff Kirsher struct niu_parent *parent;
3247e689cf4aSJeff Kirsher
3248e689cf4aSJeff Kirsher u32 flags;
3249e689cf4aSJeff Kirsher #define NIU_FLAGS_HOTPLUG_PHY_PRESENT 0x02000000 /* Removeable PHY detected*/
3250e689cf4aSJeff Kirsher #define NIU_FLAGS_HOTPLUG_PHY 0x01000000 /* Removeable PHY */
3251e689cf4aSJeff Kirsher #define NIU_FLAGS_VPD_VALID 0x00800000 /* VPD has valid version */
3252e689cf4aSJeff Kirsher #define NIU_FLAGS_MSIX 0x00400000 /* MSI-X in use */
3253e689cf4aSJeff Kirsher #define NIU_FLAGS_MCAST 0x00200000 /* multicast filter enabled */
3254e689cf4aSJeff Kirsher #define NIU_FLAGS_PROMISC 0x00100000 /* PROMISC enabled */
3255e689cf4aSJeff Kirsher #define NIU_FLAGS_XCVR_SERDES 0x00080000 /* 0=PHY 1=SERDES */
3256e689cf4aSJeff Kirsher #define NIU_FLAGS_10G 0x00040000 /* 0=1G 1=10G */
3257e689cf4aSJeff Kirsher #define NIU_FLAGS_FIBER 0x00020000 /* 0=COPPER 1=FIBER */
3258e689cf4aSJeff Kirsher #define NIU_FLAGS_XMAC 0x00010000 /* 0=BMAC 1=XMAC */
3259e689cf4aSJeff Kirsher
3260e689cf4aSJeff Kirsher u32 msg_enable;
3261e689cf4aSJeff Kirsher char irq_name[NIU_NUM_RXCHAN+NIU_NUM_TXCHAN+3][IFNAMSIZ + 6];
3262e689cf4aSJeff Kirsher
3263e689cf4aSJeff Kirsher /* Protects hw programming, and ring state. */
3264e689cf4aSJeff Kirsher spinlock_t lock;
3265e689cf4aSJeff Kirsher
3266e689cf4aSJeff Kirsher const struct niu_ops *ops;
3267e689cf4aSJeff Kirsher union niu_mac_stats mac_stats;
3268e689cf4aSJeff Kirsher
3269e689cf4aSJeff Kirsher struct rx_ring_info *rx_rings;
3270e689cf4aSJeff Kirsher struct tx_ring_info *tx_rings;
3271e689cf4aSJeff Kirsher int num_rx_rings;
3272e689cf4aSJeff Kirsher int num_tx_rings;
3273e689cf4aSJeff Kirsher
3274e689cf4aSJeff Kirsher struct niu_ldg ldg[NIU_NUM_LDG];
3275e689cf4aSJeff Kirsher int num_ldg;
3276e689cf4aSJeff Kirsher
3277e689cf4aSJeff Kirsher void __iomem *mac_regs;
3278e689cf4aSJeff Kirsher unsigned long ipp_off;
3279e689cf4aSJeff Kirsher unsigned long pcs_off;
3280e689cf4aSJeff Kirsher unsigned long xpcs_off;
3281e689cf4aSJeff Kirsher
3282e689cf4aSJeff Kirsher struct timer_list timer;
3283e689cf4aSJeff Kirsher u64 orig_led_state;
3284e689cf4aSJeff Kirsher const struct niu_phy_ops *phy_ops;
3285e689cf4aSJeff Kirsher int phy_addr;
3286e689cf4aSJeff Kirsher
3287e689cf4aSJeff Kirsher struct niu_link_config link_config;
3288e689cf4aSJeff Kirsher
3289e689cf4aSJeff Kirsher struct work_struct reset_task;
3290e689cf4aSJeff Kirsher
3291e689cf4aSJeff Kirsher u8 port;
3292e689cf4aSJeff Kirsher u8 mac_xcvr;
3293e689cf4aSJeff Kirsher #define MAC_XCVR_MII 1
3294e689cf4aSJeff Kirsher #define MAC_XCVR_PCS 2
3295e689cf4aSJeff Kirsher #define MAC_XCVR_XPCS 3
3296e689cf4aSJeff Kirsher
3297e689cf4aSJeff Kirsher struct niu_classifier clas;
3298e689cf4aSJeff Kirsher
3299e689cf4aSJeff Kirsher struct niu_vpd vpd;
3300e689cf4aSJeff Kirsher u32 eeprom_len;
3301e689cf4aSJeff Kirsher
3302e689cf4aSJeff Kirsher struct platform_device *op;
3303e689cf4aSJeff Kirsher void __iomem *vir_regs_1;
3304e689cf4aSJeff Kirsher void __iomem *vir_regs_2;
3305e689cf4aSJeff Kirsher };
3306e689cf4aSJeff Kirsher
3307e689cf4aSJeff Kirsher #endif /* _NIU_H */
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