Lines Matching +full:0 +full:x00580000
30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
49 reg = <0x100>;
67 reg = <0x101>;
80 reg = <0x102>;
93 reg = <0x103>;
102 CPU4: cpu@0 {
106 reg = <0x0>;
124 reg = <0x1>;
137 reg = <0x2>;
150 reg = <0x3>;
160 CPU_SLEEP_0: cpu-sleep-0 {
202 /* Boot CPU is cluster 1 core 0 */
231 qcom,dload-mode = <&tcsr 0x6100>;
238 reg = <0x0 0x80000000 0x0 0x0>;
251 qcom,ipc = <&apcs1_mbox 8 0>;
308 reg = <0x0 0x86000000 0x0 0x300000>;
314 reg = <0x0 0x86300000 0x0 0x100000>;
322 reg = <0x0 0x86400000 0x0 0x100000>;
327 reg = <0x0 0x86500000 0x0 0x180000>;
332 reg = <0x0 0x86680000 0x0 0x80000>;
338 reg = <0x0 0x86700000 0x0 0xe0000>;
345 reg = <0x0 0x867e0000 0x0 0x20000>;
357 * alignment = <0x0 0x400000>;
358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
366 size = <0x0 0x600000>;
367 alignment = <0x0 0x100000>;
368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
374 size = <0x0 0x500000>;
375 alignment = <0x0 0x100000>;
376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
382 size = <0x0 0x100000>;
383 alignment = <0x0 0x100000>;
384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
398 qcom,local-pid = <0>;
423 qcom,local-pid = <0>;
444 #size-cells = <0>;
446 mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>;
448 apps_smsm: apps@0 {
449 reg = <0>;
471 soc: soc@0 {
475 ranges = <0 0 0 0xffffffff>;
479 reg = <0x00022000 0x200>;
486 reg = <0x0005c000 0x1000>;
491 reg = <0xa0 0x1>;
492 bits = <0 8>;
496 reg = <0xa1 0x1>;
497 bits = <0 6>;
501 reg = <0xa1 0x2>;
506 reg = <0xa2 0x2>;
511 reg = <0xa3 0x1>;
516 reg = <0xa4 0x1>;
517 bits = <0 6>;
521 reg = <0xa4 0x2>;
526 reg = <0xa5 0x2>;
531 reg = <0xa6 0x1>;
536 reg = <0xa7 0x1>;
537 bits = <0 8>;
541 reg = <0xd0 0x1>;
542 bits = <0 3>;
546 reg = <0xd0 0x2>;
551 reg = <0xd1 0x1>;
556 reg = <0xd1 0x2>;
561 reg = <0xd2 0x2>;
566 reg = <0xd3 0x2>;
571 reg = <0xd4 0x1>;
576 reg = <0xd4 0x2>;
581 reg = <0xd5 0x2>;
586 reg = <0xd6 0x2>;
591 reg = <0xd7 0x1>;
598 reg = <0x00060000 0x8000>;
603 reg = <0x00400000 0x62000>;
609 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x1000>; /* SROT */
641 reg = <0x004ab000 0x4>;
646 reg = <0x00500000 0x11000>;
652 reg = <0x00580000 0x14080>;
663 reg = <0x01000000 0x300000>;
666 gpio-ranges = <&tlmm 0 0 122>;
1172 reg = <0x01800000 0x80000>;
1176 <&mdss_dsi0_phy 0>,
1177 <0>,
1178 <0>,
1179 <0>;
1194 reg = <0x01905000 0x20000>;
1200 reg = <0x01937000 0x30000>;
1205 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3000>;
1230 reg = <0x01a01000 0x89000>;
1234 interrupts = <0>;
1253 #size-cells = <0>;
1255 port@0 {
1256 reg = <0>;
1274 reg = <0x01a98000 0x25c>;
1294 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1301 #size-cells = <0>;
1305 #size-cells = <0>;
1307 port@0 {
1308 reg = <0>;
1324 reg = <0x01a98300 0xd4>,
1325 <0x01a98500 0x280>,
1326 <0x01a98780 0x30>;
1336 #phy-cells = <0>;
1343 reg = <0x01aa0000 0x25c>;
1363 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1370 #size-cells = <0>;
1372 port@0 {
1373 reg = <0>;
1389 reg = <0x01aa0300 0xd4>,
1390 <0x01aa0500 0x280>,
1391 <0x01aa0780 0x30>;
1401 #phy-cells = <0>;
1408 reg = <0x01c00000 0x10000>;
1460 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e20000 0x20000>;
1473 reg = <0x4000 0x1000>;
1480 reg = <0x5000 0x1000>;
1487 ranges = <0 0x1f08000 0x10000>;
1500 reg = <0x1000 0x1000>;
1507 reg = <0x2000 0x1000>;
1514 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x400000>,
1516 <0x02c00000 0x400000>,
1517 <0x03800000 0x200000>,
1518 <0x0200a000 0x002100>;
1522 qcom,ee = <0>;
1523 qcom,channel = <0>;
1525 #size-cells = <0>;
1532 reg = <0x04044000 0x19000>;
1535 qcom,ee = <0>;
1546 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1549 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1569 qcom,smem-states = <&hexagon_smp2p_out 0>;
1571 resets = <&scm 0>;
1573 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1603 qcom,smd-edge = <0>;
1614 #size-cells = <0>;
1629 #size-cells = <0>;
1641 #size-cells = <0>;
1652 #sound-dai-cells = <0>;
1661 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4>;
1669 reg = <0x07708000 0x10000>;
1689 #size-cells = <0>;
1695 reg = <0x0771c000 0x400>;
1705 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1716 pinctrl-0 = <&sdc1_default>;
1727 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1738 pinctrl-0 = <&sdc2_default>;
1747 reg = <0x07884000 0x23000>;
1752 qcom,ee = <0>;
1758 reg = <0x078af000 0x200>;
1762 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1764 pinctrl-0 = <&blsp_uart1_default>;
1772 reg = <0x078b0000 0x200>;
1778 pinctrl-0 = <&blsp_uart2_default>;
1786 reg = <0x078b5000 0x500>;
1793 pinctrl-0 = <&blsp_i2c1_default>;
1797 #size-cells = <0>;
1803 reg = <0x078b5000 0x500>;
1810 pinctrl-0 = <&blsp_spi1_default>;
1814 #size-cells = <0>;
1820 reg = <0x078b6000 0x500>;
1827 pinctrl-0 = <&blsp_i2c2_default>;
1831 #size-cells = <0>;
1837 reg = <0x078b6000 0x500>;
1844 pinctrl-0 = <&blsp_spi2_default>;
1848 #size-cells = <0>;
1854 reg = <0x078b7000 0x500>;
1861 pinctrl-0 = <&blsp_i2c3_default>;
1865 #size-cells = <0>;
1871 reg = <0x078b7000 0x500>;
1878 pinctrl-0 = <&blsp_spi3_default>;
1882 #size-cells = <0>;
1888 reg = <0x078b8000 0x500>;
1895 pinctrl-0 = <&blsp_i2c4_default>;
1899 #size-cells = <0>;
1905 reg = <0x078b8000 0x500>;
1912 pinctrl-0 = <&blsp_spi4_default>;
1916 #size-cells = <0>;
1922 reg = <0x078b9000 0x500>;
1929 pinctrl-0 = <&blsp_i2c5_default>;
1933 #size-cells = <0>;
1939 reg = <0x078b9000 0x500>;
1946 pinctrl-0 = <&blsp_spi5_default>;
1950 #size-cells = <0>;
1956 reg = <0x078ba000 0x500>;
1963 pinctrl-0 = <&blsp_i2c6_default>;
1967 #size-cells = <0>;
1973 reg = <0x078ba000 0x500>;
1980 pinctrl-0 = <&blsp_spi6_default>;
1984 #size-cells = <0>;
1990 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x200>;
2007 ahb-burst-config = <0>;
2019 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2021 #phy-cells = <0>;
2022 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 <0x1 0x6b>,
2024 <0x2 0x24>,
2025 <0x3 0x13>;
2033 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2042 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3000>;
2053 qcom,smem-states = <&wcnss_smp2p_out 0>;
2057 pinctrl-0 = <&wcss_wlan_default>;
2103 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2107 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2112 reg = <0x0b011000 0x1000>;
2115 #clock-cells = <0>;
2123 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>;
2129 reg = <0x0b088000 0x1000>;
2133 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1000>;
2139 reg = <0x0b098000 0x1000>;
2143 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1000>;
2149 reg = <0x0b0a8000 0x1000>;
2153 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1000>;
2159 reg = <0x0b0b8000 0x1000>;
2163 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1000>;
2169 reg = <0x0b111000 0x1000>;
2172 #clock-cells = <0>;
2178 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>;
2184 reg = <0x0b120000 0x1000>;
2192 reg = <0x0b121000 0x1000>,
2193 <0x0b122000 0x1000>;
2196 frame-number = <0>;
2200 reg = <0x0b123000 0x1000>;
2207 reg = <0x0b124000 0x1000>;
2214 reg = <0x0b125000 0x1000>;
2221 reg = <0x0b126000 0x1000>;
2228 reg = <0x0b127000 0x1000>;
2235 reg = <0x0b128000 0x1000>;
2244 reg = <0x0b188000 0x1000>;
2248 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1000>;
2254 reg = <0x0b198000 0x1000>;
2258 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1000>;
2264 reg = <0x0b1a8000 0x1000>;
2268 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1000>;
2274 reg = <0x0b1b8000 0x1000>;
2278 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1000>;
2284 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>;
2290 reg = <0x0b1d1000 0x1000>;
2293 #clock-cells = <0>;
2313 hysteresis = <0>;
2479 thermal-sensors = <&tsens 0>;