Lines Matching +full:0 +full:x00580000
24 #define DFLT_FQ_ID 0x00FFFFFF
27 #define PORT_BMI_FIFO_UNITS 0x100
34 #define PORT_IC_OFFSET_UNITS 0x10
38 #define BMI_PORT_REGS_OFFSET 0
39 #define QMI_PORT_REGS_OFFSET 0x400
40 #define HWP_PORT_REGS_OFFSET 0x800
59 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0
62 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f
64 #define QMI_PORT_CFG_EN 0x80000000
65 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
67 #define QMI_DEQ_CFG_PRI 0x80000000
68 #define QMI_DEQ_CFG_TYPE1 0x10000000
69 #define QMI_DEQ_CFG_TYPE2 0x20000000
70 #define QMI_DEQ_CFG_TYPE3 0x30000000
71 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000
72 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000
73 #define QMI_DEQ_CFG_SP_MASK 0xf
77 (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400)
80 #define BMI_EBD_EN 0x80000000
82 #define BMI_PORT_CFG_EN 0x80000000
84 #define BMI_PORT_STATUS_BSY 0x80000000
90 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
93 #define BMI_FRAME_END_CS_IGNORE_MASK 0x0000001f
96 #define BMI_RX_FRAME_END_CUT_MASK 0x0000001f
99 #define BMI_IC_TO_EXT_MASK 0x0000001f
101 #define BMI_IC_FROM_INT_MASK 0x0000000f
102 #define BMI_IC_SIZE_MASK 0x0000001f
105 #define BMI_INT_BUF_MARG_MASK 0x0000000f
107 #define BMI_EXT_BUF_MARG_START_MASK 0x000001ff
108 #define BMI_EXT_BUF_MARG_END_MASK 0x000001ff
110 #define BMI_CMD_MR_LEAC 0x00200000
111 #define BMI_CMD_MR_SLEAC 0x00100000
112 #define BMI_CMD_MR_MA 0x00080000
113 #define BMI_CMD_MR_DEAS 0x00040000
118 #define BMI_CMD_TX_MR_DEF 0
120 #define BMI_CMD_ATTR_ORDER 0x80000000
121 #define BMI_CMD_ATTR_SYNC 0x02000000
125 #define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000000f
132 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
137 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
138 #define BMI_FIFO_THRESHOLD ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
157 #define NIA_ORDER_RESTOR 0x00800000
158 #define NIA_ENG_BMI 0x00500000
159 #define NIA_ENG_QMI_ENQ 0x00540000
160 #define NIA_ENG_QMI_DEQ 0x00580000
161 #define NIA_ENG_HWP 0x00440000
162 #define NIA_ENG_HWK 0x00480000
163 #define NIA_BMI_AC_ENQ_FRAME 0x00000002
164 #define NIA_BMI_AC_TX_RELEASE 0x000002C0
165 #define NIA_BMI_AC_RELEASE 0x000000C0
166 #define NIA_BMI_AC_TX 0x00000274
167 #define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c
170 #define TX_10G_PORT_BASE 0x30
171 #define RX_10G_PORT_BASE 0x10
190 u32 reserved003c[1]; /* (0x03C 0x03F) */
198 u32 reserved0074[0x2]; /* (0x074-0x07C) */
200 u32 reserved0080[0x20]; /* (0x080 0x0FF) */
204 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */
207 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */
218 u32 reserved0224[0x16]; /* (0x224 0x27F) */
227 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */
228 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */
230 u32 reserved0310[0x3a];
248 u32 reserved0034[0x0e]; /* (0x034-0x6c) */
251 u32 fmbm_tpfcm[0x02];
254 u32 reserved0080[0x60]; /* (0x080-0x200) */
261 u32 reserved0218[0x1A]; /* (0x218-0x280) */
269 u32 reserved029c[16]; /* (0x29C-0x2FF) */
270 u32 fmbm_tdcfg[0x3]; /* Tx Debug Configuration */
272 u32 reserved0310[0x3a]; /* (0x310-0x3FF) */
286 u32 reserved00c[4]; /* 0xn00C - 0xn01B */
289 u32 reserved024[2]; /* 0xn024 - 0x02B */
298 #define HWP_HXS_PHE_REPORT 0x00000800
299 #define HWP_HXS_PCAC_PSTAT 0x00000100
300 #define HWP_HXS_PCAC_PSTOP 0x00000001
301 #define HWP_HXS_TCP_OFFSET 0xA
302 #define HWP_HXS_UDP_OFFSET 0xB
303 #define HWP_HXS_SH_PAD_REM 0x80000000
310 u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */
485 tmp &= 0xffe0ffff; in init_bmi_rx()
537 return 0; in init_bmi_rx()
547 tmp = 0; in init_bmi_tx()
603 return 0; in init_bmi_tx()
616 return 0; in init_qmi()
629 tmp = 0; in init_qmi()
664 return 0; in init_qmi()
674 while (cnt-- > 0 && in stop_port_hwp()
686 iowrite32be(0, ®s->fmpr_pcac); in start_port_hwp()
688 while (cnt-- > 0 && in start_port_hwp()
702 for (i = 0; i < HWP_HXS_COUNT; i++) { in init_hwp()
704 iowrite32be(0x00000000, ®s->pmda[i].ssa); in init_hwp()
705 iowrite32be(0xffffffff, ®s->pmda[i].lcv); in init_hwp()
741 return 0; in init()
765 for (i = 0; (i < (bp->count - 1) && in set_bpools()
773 for (i = 0; i < bp->count; i++) { in set_bpools()
793 iowrite32be(0, &bp_reg[i]); in set_bpools()
796 tmp = 0; in set_bpools()
797 for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { in set_bpools()
800 tmp |= 0x80000000 >> i; in set_bpools()
804 tmp |= 0x80 >> i; in set_bpools()
812 return 0; in set_bpools()
826 u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0; in verify_size_of_fifo()
857 /* 4 according to spec + 1 for FOF>0 */ in verify_size_of_fifo()
877 WARN_ON(min_fifo_size_required <= 0); in verify_size_of_fifo()
888 return 0; in verify_size_of_fifo()
898 int i = 0, j = 0, err; in set_ext_buffer_pools()
901 memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM); in set_ext_buffer_pools()
902 memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS); in set_ext_buffer_pools()
910 memset(&bpools, 0, sizeof(struct fman_port_bpools)); in set_ext_buffer_pools()
913 for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) { in set_ext_buffer_pools()
926 for (i = 0; i < port->bm_max_num_of_pools; i++) { in set_ext_buffer_pools()
928 for (j = 0; j < ext_buf_pools-> in set_ext_buffer_pools()
941 for (i = 0; i < port->bm_max_num_of_pools; i++) { in set_ext_buffer_pools()
944 for (j = 0; j < ext_buf_pools-> in set_ext_buffer_pools()
957 if (err != 0) { in set_ext_buffer_pools()
962 return 0; in set_ext_buffer_pools()
984 if (init(port) != 0) { in init_low_level_driver()
995 /* override fmbm_tcfqid 0 with a false non-0 value. in init_low_level_driver()
997 * Otherwise, if fmbm_tcfqid is 0 the FM will release in init_low_level_driver()
1000 iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid); in init_low_level_driver()
1006 return 0; in init_low_level_driver()
1038 return 0; in fill_soc_specific_params()
1056 return 0; in get_dflt_fifo_deq_pipeline_depth()
1059 return 0; in get_dflt_fifo_deq_pipeline_depth()
1078 return 0; in get_dflt_num_of_tasks()
1081 return 0; in get_dflt_num_of_tasks()
1092 return 0; in get_dflt_extra_num_of_tasks()
1101 return 0; in get_dflt_extra_num_of_tasks()
1125 return 0; in get_dflt_num_of_open_dmas()
1137 val = 0; in get_dflt_num_of_open_dmas()
1149 return 0; in get_dflt_extra_num_of_open_dmas()
1160 return 0; in get_dflt_extra_num_of_open_dmas()
1184 val = 0; in get_dflt_num_of_fifo_bufs()
1201 val = 0; in get_dflt_num_of_fifo_bufs()
1232 ((port->rev_info.minor == 0) || (port->rev_info.minor == 3))) in set_dflt_cfg()
1292 * Return: 0 on success; Error code otherwise.
1360 if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) && in fman_port_config()
1364 port->open_dmas.extra = 0; in fman_port_config()
1375 reg = 0x00001013; in fman_port_config()
1379 return 0; in fman_port_config()
1414 * Return: 0 on success; Error code otherwise.
1457 memset(¶ms, 0, sizeof(params)); in fman_port_init()
1498 return 0; in fman_port_init()
1525 * Return: 0 on success; Error code otherwise.
1544 return 0; in fman_port_cfg_buf_prefix_content()
1560 * Return: 0 on success; Error code otherwise.
1599 if (count == 0) { in fman_port_disable()
1616 if (count == 0) { in fman_port_disable()
1625 return 0; in fman_port_disable()
1637 * Return: 0 on success; Error code otherwise.
1671 return 0; in fman_port_enable()
1726 return 0; in fman_port_get_hash_result_offset()
1738 return 0; in fman_port_get_tstamp()
1751 int err = 0; in fman_port_probe()
1834 if (qman_channel_id == 0) { in fman_port_probe()
1843 err = of_address_to_resource(port_node, 0, &res); in fman_port_probe()
1844 if (err < 0) { in fman_port_probe()
1871 return 0; in fman_port_probe()
1907 if (err < 0) in fman_port_load()