Lines Matching +full:0 +full:x00580000
24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
177 mboxes = <&apcs_glb 0>;
253 reg = <0 0x85900000 0 0x500000>;
258 reg = <0 0x85e00000 0 0x100000>;
263 reg = <0 0x85f00000 0 0x200000>;
268 reg = <0 0x86100000 0 0x300000>;
273 reg = <0 0x86400000 0 0x1100000>;
278 reg = <0 0x87500000 0 0x1a00000>;
283 reg = <0 0x88f00000 0 0x600000>;
288 reg = <0 0x89500000 0 0x100000>;
293 reg = <0 0x9f800000 0 0x800000>;
307 soc: soc@0 {
310 ranges = <0 0 0 0xffffffff>;
315 reg = <0x00800000 0x30000>;
326 reg = <0x00060000 0x6000>;
331 reg = <0x00078000 0x400>;
332 #phy-cells = <0>;
345 reg = <0x0007a000 0x200>;
346 #phy-cells = <0>;
359 reg = <0x0007c000 0x200>;
360 #phy-cells = <0>;
373 reg = <0x000a4000 0x1000>;
377 reg = <0x13c 0x4>;
382 reg = <0x1f8 0x1>;
383 bits = <0 6>;
387 reg = <0x1f8 0x2>;
392 reg = <0x1f9 0x2>;
397 reg = <0x1fa 0x1>;
402 reg = <0x1fb 0x1>;
403 bits = <0 6>;
407 reg = <0x1fb 0x2>;
412 reg = <0x1fc 0x2>;
417 reg = <0x1fd 0x1>;
422 reg = <0x1fe 0x1>;
423 bits = <0 6>;
427 reg = <0x1fe 0x2>;
432 reg = <0x200 0x1>;
433 bits = <0 6>;
437 reg = <0x200 0x2>;
442 reg = <0x201 0x2>;
447 reg = <0x202 0x1>;
452 reg = <0x203 0x1>;
453 bits = <0 6>;
457 reg = <0x203 0x2>;
462 reg = <0x204 0x2>;
467 reg = <0x205 0x1>;
472 reg = <0x206 0x1>;
473 bits = <0 6>;
477 reg = <0x206 0x2>;
482 reg = <0x208 1>;
483 bits = <0 3>;
487 reg = <0x208 2>;
492 reg = <0x209 2>;
497 reg = <0x231 0x4>;
501 reg = <0x232 0x4>;
505 reg = <0x233 0x4>;
509 reg = <0x229 0x4>;
513 reg = <0x22a 0x4>;
517 reg = <0x22b 0x4>;
518 bits = <0 6>;
521 reg = <0x22b 0x4>;
525 reg = <0x22d 0x4>;
529 reg = <0x230 0x4>;
530 bits = <0 12>;
533 reg = <0x228 0x4>;
534 bits = <0 3>;
537 reg = <0x228 0x4>;
541 reg = <0x229 0x4>;
542 bits = <0 3>;
545 reg = <0x218 0x4>;
552 reg = <0x000e3000 0x1000>;
558 reg = <0x00400000 0x80000>;
565 reg = <0x004a9000 0x1000>, /* TM */
566 <0x004a8000 0x1000>; /* SROT */
598 reg = <0x00500000 0x15080>;
604 reg = <0x00580000 0x23080>;
611 reg = <0x00b00000 0x4040>;
614 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
644 * qcom,halt-regs = <&tcsr 0x19004>;
649 qcom,smem-states = <&cdsp_smp2p_out 0>;
666 reg = <0x07678800 0x400>;
690 reg = <0x07580000 0xcd00>;
695 snps,hird-threshold = /bits/ 8 <0x10>;
703 reg = <0x079b8800 0x400>;
727 reg = <0x078c0000 0xcc00>;
732 snps,hird-threshold = /bits/ 8 <0x10>;
740 reg = <0x01000000 0x200000>,
741 <0x01300000 0x200000>,
742 <0x07b00000 0x200000>;
745 gpio-ranges = <&tlmm 0 0 120>;
882 reg = <0x01800000 0x80000>;
890 <0>,
891 <0>,
892 <0>;
900 reg = <0x01905000 0x20000>;
906 reg = <0x01937000 0x25000>;
911 reg = <0x00290000 0x10000>;
916 reg = <0x0200f000 0x001000>,
917 <0x02400000 0x800000>,
918 <0x02c00000 0x800000>,
919 <0x03800000 0x200000>,
920 <0x0200a000 0x002100>;
924 qcom,ee = <0>;
925 qcom,channel = <0>;
927 #size-cells = <0>;
934 reg = <0x07400000 0x4040>;
937 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
949 qcom,smem-states = <&wcss_smp2p_out 0>;
966 reg = <0x07786000 0xb8>;
974 #clock-cells = <0>;
975 #phy-cells = <0>;
982 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
999 reg = <0x07884000 0x25000>;
1004 qcom,ee = <0>;
1010 reg = <0x078af000 0x200>;
1014 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1017 pinctrl-0 = <&blsp1_uart0_default>;
1023 reg = <0x078b0000 0x200>;
1030 pinctrl-0 = <&blsp1_uart1_default>;
1036 reg = <0x078b1000 0x200>;
1043 pinctrl-0 = <&blsp1_uart2_default>;
1049 reg = <0x07a80000 0x10000>,
1050 <0x07a96000 0x100>;
1070 reg = <0xa000000 0x800000>;
1090 reg = <0x078b2000 0x200>;
1097 pinctrl-0 = <&blsp1_uart3_default>;
1103 reg = <0x078b5000 0x600>;
1109 pinctrl-0 = <&blsp1_i2c0_default>;
1111 #size-cells = <0>;
1117 reg = <0x078b5000 0x600>;
1123 pinctrl-0 = <&blsp1_spi0_default>;
1125 #size-cells = <0>;
1131 reg = <0x078b6000 0x600>;
1137 pinctrl-0 = <&blsp1_i2c1_default>;
1139 #size-cells = <0>;
1145 reg = <0x078b6000 0x600>;
1151 pinctrl-0 = <&blsp1_spi1_default>;
1153 #size-cells = <0>;
1159 reg = <0x078b7000 0x600>;
1165 pinctrl-0 = <&blsp1_i2c2_default>;
1167 #size-cells = <0>;
1173 reg = <0x078b7000 0x600>;
1179 pinctrl-0 = <&blsp1_spi2_default>;
1181 #size-cells = <0>;
1187 reg = <0x078b8000 0x600>;
1193 pinctrl-0 = <&blsp1_i2c3_default>;
1195 #size-cells = <0>;
1201 reg = <0x078b8000 0x600>;
1207 pinctrl-0 = <&blsp1_spi3_default>;
1209 #size-cells = <0>;
1215 reg = <0x078b9000 0x600>;
1221 pinctrl-0 = <&blsp1_i2c4_default>;
1223 #size-cells = <0>;
1229 reg = <0x078b9000 0x600>;
1235 pinctrl-0 = <&blsp1_spi4_default>;
1237 #size-cells = <0>;
1243 reg = <0x07ac4000 0x17000>;
1248 qcom,ee = <0>;
1254 reg = <0x07aef000 0x200>;
1258 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1261 pinctrl-0 = <&blsp2_uart0_default>;
1267 reg = <0x07af5000 0x600>;
1273 pinctrl-0 = <&blsp2_i2c0_default>;
1275 #size-cells = <0>;
1281 reg = <0x07af5000 0x600>;
1287 pinctrl-0 = <&blsp2_spi0_default>;
1289 #size-cells = <0>;
1295 reg = <0x08600000 0x1000>;
1300 ranges = <0 0x08600000 0x1000>;
1304 reg = <0x94c 0xc8>;
1312 reg = <0x0b000000 0x1000>,
1313 <0x0b002000 0x1000>;
1319 reg = <0x0b011000 0x1000>;
1323 #clock-cells = <0>;
1328 reg = <0x0b016000 0x30>;
1329 #clock-cells = <0>;
1337 reg = <0x0b017000 0x1000>;
1343 reg = <0x0b018000 0x1000>;
1344 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1348 #power-domain-cells = <0>;
1385 reg = <0x0b120000 0x1000>;
1389 frame-number = <0>;
1392 reg = <0x0b121000 0x1000>,
1393 <0x0b122000 0x1000>;
1399 reg = <0x0b123000 0x1000>;
1406 reg = <0x0b124000 0x1000>;
1413 reg = <0x0b125000 0x1000>;
1420 reg = <0x0b126000 0x1000>;
1427 reg = <0xb127000 0x1000>;
1434 reg = <0x0b128000 0x1000>;
1441 reg = <0x0c700000 0x4040>;
1444 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1456 qcom,smem-states = <&adsp_smp2p_out 0>;
1473 reg = <0x10000000 0xf1d>,
1474 <0x10000f20 0xa8>,
1475 <0x07780000 0x2000>,
1476 <0x10001000 0x2000>;
1479 linux,pci-domain = <0>;
1480 bus-range = <0x00 0xff>;
1485 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
1486 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
1491 interrupt-map-mask = <0 0 0 0x7>;
1492 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1493 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1494 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1495 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1520 pcie@0 {
1522 reg = <0x0 0x0 0x0 0x0 0x0>;
1523 bus-range = <0x01 0xff>;
1545 qcom,local-pid = <0>;
1565 qcom,local-pid = <0>;
1585 qcom,local-pid = <0>;
1604 thermal-sensors = <&tsens 0>;