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/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dhdmi.txt20 numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
41 #size-cells = <0>;
43 reg = <0x00120000 0x9000>;
44 interrupts = <0 115 0x04>;
50 port@0 {
51 reg = <0>;
H A Dfsl,imx6-hdmi.yaml47 port@0:
65 - port@0
89 reg = <0x00120000 0x9000>;
90 interrupts = <0 115 0x04>;
98 #size-cells = <0>;
100 port@0 {
101 reg = <0>;
/freebsd/sys/dev/ath/ath_hal/ar9001/
H A Dar9160.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
28 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
[all …]
/freebsd/sys/fs/nfs/
H A Drpcv2.h47 #define RPCAUTH_NULL 0
70 #define RPCAUTHGSS_DATA 0
79 #define RPCAUTHGSS_MAXSEQ 0x80000000
90 #define GSS_KERBV_QOP 0
107 #define RPCPROG_GSSD 0x20101010
122 #define RPCPROG_NFSUSERD 0x21010101
133 #define GSS_S_COMPLETE 0x00000000
134 #define GSS_S_CONTINUE_NEEDED 0x00000001
135 #define GSS_S_DUPLICATE_TOKEN 0x00000002
136 #define GSS_S_OLD_TOKEN 0x00000004
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-381-netgear-gs110emx.dts24 pinctrl-0 = <&front_button_pins>;
36 reg = <0x00000000 0x08000000>; /* 128 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1
[all...]
H A Darmada-xp-lenovo-ix4-300d.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
40 pinctrl-0 = <&ge0_rgmii_pins>;
48 pinctrl-0 = <&ge1_rgmii_pins>;
69 reg = <0x2e>;
74 reg = <0x50>;
[all …]
/freebsd/sys/contrib/edk2/Include/Pi/
H A DPiFirmwareVolume.h23 #define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
24 #define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
25 #define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
35 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
36 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
37 #define EFI_FVB2_READ_STATUS 0x00000004
38 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
39 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
40 #define EFI_FVB2_WRITE_STATUS 0x00000020
41 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
H A DPiStatusCode.h33 #define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
34 #define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
35 #define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
44 #define EFI_PROGRESS_CODE 0x00000001
45 #define EFI_ERROR_CODE 0x00000002
46 #define EFI_DEBUG_CODE 0x00000003
59 #define EFI_ERROR_MINOR 0x40000000
60 #define EFI_ERROR_MAJOR 0x80000000
61 #define EFI_ERROR_UNRECOVERED 0x90000000
62 #define EFI_ERROR_UNCONTAINED 0xa0000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-sata.dtsi37 ranges = <0x0 0x0 0x67d00000 0x00800000>;
39 sata0: ahci@0 {
41 reg = <0x00000000 0x1000>;
45 #size-cells = <0>;
48 sata0_port0: sata-port@0 {
49 reg = <0>;
57 reg = <0x00002100 0x1000>;
60 #size-cells = <0>;
63 sata0_phy0: sata-phy@0 {
64 reg = <0>;
[all …]
H A Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam437x-idk-evm.dts104 pinctrl-0 = <&gpio_keys_pins_default>;
106 switch-0 {
115 #clock-cells = <0>;
125 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
176 AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
182 AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
183 AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
189 AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
190 AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
196 AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
[all …]
H A Dam437x-sk-evm.dts31 #clock-cells = <0>;
38 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 51 53 56 62 75 101 152 255>;
73 pinctrl-0 = <&matrix_keypad_pins>;
85 MATRIX_KEY(0, 0, KEY_DOWN)
86 MATRIX_KEY(0, 1, KEY_RIGHT)
87 MATRIX_KEY(1, 0, KEY_LEFT)
96 pinctrl-0 = <&leds_pins>;
100 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
131 pinctrl-0 = <&lcd_pins>;
[all …]
H A Dam43x-epos-evm.dts62 pinctrl-0 = <&matrix_keypad_default>;
76 linux,keymap = <0x00000201 /* P1 */
77 0x01000204 /* P4 */
78 0x02000207 /* P7 */
79 0x0300020a /* NUMERIC_STAR */
80 0x00010202 /* P2 */
81 0x01010205 /* P5 */
82 0x02010208 /* P8 */
83 0x03010200 /* P0 */
84 0x00020203 /* P3 */
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_log_sas.h46 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
47 #define SAS_LOGINFO_MASK 0xFFFF0000
50 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
53 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
55 /* Bits 15-0: LOGINFO_CODE Specific */
61 #define IOC_LOGINFO_ORIGINATOR_IOP (0x00000000)
62 #define IOC_LOGINFO_ORIGINATOR_PL (0x01000000)
63 #define IOC_LOGINFO_ORIGINATOR_IR (0x02000000)
65 #define IOC_LOGINFO_ORIGINATOR_MASK (0x0F000000)
70 #define IOC_LOGINFO_CODE_MASK (0x00FF0000)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/
H A Dbcm2712.dtsi16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x000>;
59 d-cache-size = <0x10000>;
62 i-cache-size = <0x10000>;
69 cache-size = <0x80000>;
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dmcp_public.h51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280v1.ini20 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
21 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
22 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
23 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
24 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
25 { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
26 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>,
35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>,
43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
[all …]
/freebsd/sys/dev/bce/
H A Dif_bcereg.h82 /* MII Control Register 0x0 */
102 /* MII Status Register 0x1 */
122 /* MII Autoneg Advertisement Register 0x4 */
142 /* MII Autoneg Link Partner Ability Register 0x5 */
162 /* 1000Base-T Control Register 0x09 */
182 /* MII 1000Base-T Status Register 0x0a */
194 /* MII Extended Status Register 0x0f */
214 /* MII Autoneg Link Partner Ability Register 0x19 */
245 #define BCE_CP_LOAD 0x00000001
246 #define BCE_CP_SEND 0x00000002
[all …]
/freebsd/sys/dev/ixl/
H A Di40e_register.h38 #define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
39 #define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
40 #define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
41 #define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
42 #define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
43 #define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
44 #define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
45 #define I40E_GL_ARQH_ARQH_SHIFT 0
46 #define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
47 #define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
[all …]

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