Lines Matching +full:0 +full:x00120000
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
109 CLUSTER0_L2: l2-cache@0 {
136 reg = <0x00000000 0x80000000 0 0x40000000>;
159 reg = <0 0x60401000 0 0x38c>;
166 ranges = <0x0 0x0 0x61000000 0x05000000>;
168 ccn: ccn@0 {
170 reg = <0x00000000 0x900000>;
181 reg = <0x02c00000 0x010000>, /* GICD */
182 <0x02e00000 0x600000>; /* GICR */
189 reg = <0x02c20000 0x10000>;
195 reg = <0x03000000 0x80000>;
270 ranges = <0x0 0x0 0x66400000 0x100000>;
276 reg = <0x0001c400 0x68>;
283 reg = <0x0001d000 0x400>;
288 reg = <0x00024800 0x4c>;
303 ranges = <0x0 0x0 0x68900000 0x17700000>;
309 reg = <0x00020000 0x250>;
311 #size-cells = <0>;
313 mdio@0 { /* PCIe serdes */
314 reg = <0x0>;
316 #size-cells = <0>;
320 reg = <0x3>;
322 #size-cells = <0>;
326 reg = <0x10>;
328 #size-cells = <0>;
334 reg = <0x00010000 0x1000>;
342 reg = <0x00030000 0x1000>;
353 reg = <0x00040000 0x1000>;
363 reg = <0x00050000 0x1000>;
374 reg = <0x00060000 0x1000>;
385 reg = <0x00070000 0x1000>;
396 reg = <0x00080000 0x1000>;
407 reg = <0x00090000 0x1000>;
418 reg = <0x000a0000 0x1000>;
429 reg = <0x000b0000 0x100>;
431 #size-cells = <0>;
439 reg = <0x000c0000 0x1000>;
448 reg = <0x000d0000 0x864>;
455 gpio-ranges = <&pinmux 0 0 16>,
474 reg = <0x000e0000 0x100>;
476 #size-cells = <0>;
484 reg = <0x00100000 0x1000>;
494 reg = <0x00110000 0x1000>;
504 reg = <0x00120000 0x1000>;
514 reg = <0x00130000 0x1000>;
524 reg = <0x00180000 0x1000>;
530 #size-cells = <0>;
536 reg = <0x00190000 0x1000>;
542 #size-cells = <0>;
548 reg = <0x00220000 0x28>;
553 reg = <0x00310000 0x1000>;
566 iommus = <&smmu 0x6000 0x0000>;
571 reg = <0x00340000 0x1000>;
580 reg = <0x00360000 0x600>,
581 <0x0050a408 0x600>,
582 <0x00360f00 0x20>;
586 #size-cells = <0>;
593 reg = <0x003f1000 0x100>;
597 iommus = <&smmu 0x6002 0x0000>;
603 reg = <0x003f2000 0x100>;
607 iommus = <&smmu 0x6003 0x0000>;
616 ranges = <0x0 0x0 0x8f100000 0x100>;
618 tmon: tmon@0 {
620 reg = <0x0 0x40>;
621 brcm,tmon-mask = <0x3f>;
628 polling-delay-passive = <0>;
630 thermal-sensors = <&tmon 0>;
634 hysteresis = <0>;
640 polling-delay-passive = <0>;
646 hysteresis = <0>;
652 polling-delay-passive = <0>;
658 hysteresis = <0>;
664 polling-delay-passive = <0>;
670 hysteresis = <0>;
676 polling-delay-passive = <0>;
682 hysteresis = <0>;
688 polling-delay-passive = <0>;
694 hysteresis = <0>;
705 ranges = <0x0 0x0 0x0 0x7fffffff>;
710 #size-cells = <0>;
711 reg = <0x60826100 0x100>,
712 <0x60e00408 0x1000>;
713 brcm,ape-hsls-addr-mask = <0x03400000>;