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/freebsd/sys/dev/pci/
H A Dfixup_pci.c58 { 0, 0 }
64 0,
67 DRIVER_MODULE(fixup_pci, pci, fixup_pci_driver, 0, 0);
73 case 0x12378086: /* Intel 82440FX (Natoma) */ in fixup_pci_probe()
76 case 0x01e010de: /* nVidia nForce2 */ in fixup_pci_probe()
88 pmccfg = pci_read_config(dev, 0x50, 2); in fixwsc_natoma()
90 if (pmccfg & 0x8000) { in fixwsc_natoma()
92 pmccfg &= ~0x8000; in fixwsc_natoma()
93 pci_write_config(dev, 0x50, pmccfg, 2); in fixwsc_natoma()
96 if ((pmccfg & 0x8000) == 0) { in fixwsc_natoma()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-lenovo-ix4-300d.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
40 pinctrl-0 = <&ge0_rgmii_pins>;
48 pinctrl-0 = <&ge1_rgmii_pins>;
69 reg = <0x2e>;
74 reg = <0x50>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9287an.h22 #define AR9287_AN_RF2G3_CH0 0x7808
23 #define AR9287_AN_RF2G3_CH1 0x785c
24 #define AR9287_AN_RF2G3_DB1 0xE0000000
26 #define AR9287_AN_RF2G3_DB2 0x1C000000
28 #define AR9287_AN_RF2G3_OB_CCK 0x03800000
30 #define AR9287_AN_RF2G3_OB_PSK 0x00700000
32 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000
34 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000
37 #define AR9287_AN_TXPC0 0x7898
38 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000
[all …]
H A Dar9285an.h25 #define AR9285_AN_RF2G1 0x7820
27 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
29 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
31 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
33 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
36 #define AR9285_AN_RF2G2 0x7824
38 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
41 #define AR9285_AN_RF2G3 0x7828
43 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
45 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dnvidia,tegra186-timer.yaml45 One per each timer channels 0 through 9.
57 One per each timer channels 0 through 15.
73 reg = <0x03010000 0x000e0000>;
74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x02080000 0x00121000>;
93 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq4018-jalapeno.dts34 spi_0_pins: spi-0-state {
67 pinctrl-0 = <&spi_0_pins>;
71 flash@0 {
75 reg = <0>;
83 partition@0 {
85 reg = <0x00000000 0x00040000>;
91 reg = <0x00040000 0x00020000>;
97 reg = <0x00060000 0x00060000>;
103 reg = <0x000c0000 0x00010000>;
109 reg = <0x000d0000 0x00010000>;
[all …]
H A Dqcom-ipq4018-ap120c-ac.dtsi98 pinctrl-0 = <&i2c0_pins>;
103 reg = <0x29>;
110 pinctrl-0 = <&spi0_pins>;
114 flash@0 {
116 reg = <0>;
124 partition@0 {
126 reg = <0x00000000 0x00040000>;
132 reg = <0x00040000 0x00020000>;
138 reg = <0x00060000 0x00060000>;
144 reg = <0x000c0000 0x00010000>;
[all …]
/freebsd/sys/dev/dc/
H A Dif_dcreg.h39 #define DC_BUSCTL 0x00 /* bus control */
40 #define DC_TXSTART 0x08 /* tx start demand */
41 #define DC_RXSTART 0x10 /* rx start demand */
42 #define DC_RXADDR 0x18 /* rx descriptor list start addr */
43 #define DC_TXADDR 0x20 /* tx descriptor list start addr */
44 #define DC_ISR 0x28 /* interrupt status register */
45 #define DC_NETCFG 0x30 /* network config register */
46 #define DC_IMR 0x38 /* interrupt mask */
47 #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
48 #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-nano.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
29 gpios = <&gpio1 5 0>;
37 pinctrl-0 = <&misc_pins>;
162 pinctrl-0 = <&uart0_pins>;
168 pinctrl-0 = <&uart1_pins>;
179 pinctrl-0 = <&uart2_pins>;
189 pinctrl-0 = <&uart3_pins>;
200 pinctrl-0 = <&uart4_pins>;
211 pinctrl-0 = <&uart5_pins>;
[all …]
/freebsd/sys/dev/mpt/
H A Dmpt_reg.h69 #define MPT_OFFSET_DOORBELL 0x00
70 #define MPT_OFFSET_SEQUENCE 0x04
71 #define MPT_OFFSET_DIAGNOSTIC 0x08
72 #define MPT_OFFSET_TEST 0x0C
73 #define MPT_OFFSET_DIAG_DATA 0x10
74 #define MPT_OFFSET_DIAG_ADDR 0x14
75 #define MPT_OFFSET_INTR_STATUS 0x30
76 #define MPT_OFFSET_INTR_MASK 0x34
77 #define MPT_OFFSET_REQUEST_Q 0x40
78 #define MPT_OFFSET_REPLY_Q 0x44
[all …]
/freebsd/sys/fs/nfs/
H A Drpcv2.h47 #define RPCAUTH_NULL 0
70 #define RPCAUTHGSS_DATA 0
79 #define RPCAUTHGSS_MAXSEQ 0x80000000
90 #define GSS_KERBV_QOP 0
107 #define RPCPROG_GSSD 0x20101010
122 #define RPCPROG_NFSUSERD 0x21010101
133 #define GSS_S_COMPLETE 0x00000000
134 #define GSS_S_CONTINUE_NEEDED 0x00000001
135 #define GSS_S_DUPLICATE_TOKEN 0x00000002
136 #define GSS_S_OLD_TOKEN 0x00000004
[all …]
/freebsd/sys/contrib/edk2/Include/Pi/
H A DPiFirmwareVolume.h23 #define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F
24 #define EFI_FV_FILE_ATTRIB_FIXED 0x00000100
25 #define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200
35 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
36 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
37 #define EFI_FVB2_READ_STATUS 0x00000004
38 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
39 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
40 #define EFI_FVB2_WRITE_STATUS 0x00000020
41 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
H A DPiStatusCode.h33 #define EFI_STATUS_CODE_TYPE_MASK 0x000000FF
34 #define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000
35 #define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00
44 #define EFI_PROGRESS_CODE 0x00000001
45 #define EFI_ERROR_CODE 0x00000002
46 #define EFI_DEBUG_CODE 0x00000003
59 #define EFI_ERROR_MINOR 0x40000000
60 #define EFI_ERROR_MAJOR 0x80000000
61 #define EFI_ERROR_UNRECOVERED 0x90000000
62 #define EFI_ERROR_UNCONTAINED 0xa0000000
[all …]
/freebsd/sys/dts/arm/
H A Dqcom-ipq4018-rt-ac58u.dts16 reg = <0x80000000 0x8000000>;
48 reg = <0x1949000 0x100>;
54 reg = <0x194b000 0x100>;
60 reg = <0x1953000 0x1000>;
66 reg = <0x1957000 0x100>;
75 #size-cells = <0>;
79 #trigger-source-cells = <0>;
84 #trigger-source-cells = <0>;
149 gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
197 pinctrl-0 = <&spi_0_pins>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416desc.h29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
68 uint32_t ds_ctl0; /* DMA control 0 */
104 #define AR_FrameLen 0x00000fff
105 #define AR_VirtMoreFrag 0x00001000
106 #define AR_TxCtlRsvd00 0x0000e000
107 #define AR_XmitPower 0x003f0000
109 #define AR_RTSEnable 0x00400000
110 #define AR_VEOL 0x00800000
111 #define AR_ClrDestMask 0x01000000
112 #define AR_TxCtlRsvd01 0x1e000000
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
[all...]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/dev/acpica/include/
H A Dacconfig.h235 #define ACPI_MAX_REFERENCE_COUNT 0x4000
295 #define ACPI_EBDA_PTR_LOCATION 0x0000040E /* Physical Address */
298 #define ACPI_HI_RSDP_WINDOW_BASE 0x000E0000 /* Physical Address */
299 #define ACPI_HI_RSDP_WINDOW_SIZE 0x00020000
304 #define ACPI_USER_REGION_BEGIN 0x80
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300desc.h94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_log_sas.h46 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
47 #define SAS_LOGINFO_MASK 0xFFFF0000
50 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
53 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
55 /* Bits 15-0: LOGINFO_CODE Specific */
61 #define IOC_LOGINFO_ORIGINATOR_IOP (0x00000000)
62 #define IOC_LOGINFO_ORIGINATOR_PL (0x01000000)
63 #define IOC_LOGINFO_ORIGINATOR_IR (0x02000000)
65 #define IOC_LOGINFO_ORIGINATOR_MASK (0x0F000000)
70 #define IOC_LOGINFO_CODE_MASK (0x00FF0000)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]

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