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12

/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dcom.fuc32 ctx_object: .b32 0
35 ctx_dma_query: .b32 0
36 ctx_dma_src: .b32 0
37 ctx_dma_dst: .b32 0
40 ctx_query_address_high: .b32 0
41 ctx_query_address_low: .b32 0
42 ctx_query_counter: .b32 0
43 ctx_src_address_high: .b32 0
44 ctx_src_address_low: .b32 0
45 ctx_src_pitch: .b32 0
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9g25.dtsi22 0xffffffff 0xffe0399f 0xc000001c /* pioA */
23 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
24 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
25 0x003fffff 0x003f8000 0x00000000 /* pioD */
H A Dat91sam9x25.dtsi23 0xffffffff 0xffe03fff 0xc000001c /* pioA */
24 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
25 0x80000000 0xfffd0000 0xb83fffff /* pioC */
26 0x003fffff 0x003f8000 0x00000000 /* pioD */
H A Dat91sam9263.dtsi40 #size-cells = <0>;
42 cpu@0 {
45 reg = <0>;
51 reg = <0x20000000 0x08000000>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
70 reg = <0x00300000 0x14000>;
73 ranges = <0 0x00300000 0x14000>;
[all …]
/linux/arch/m68k/include/asm/
H A Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/linux/drivers/mtd/maps/
H A Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
H A Dmmhub_2_0_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dtonga_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Diceland_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Dsdma_v6_0_0_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
61 #define SDMA_SUBOP_WRITE_LINEAR 0
64 #define SDMA_SUBOP_PTEPDE_GEN 0
76 #define SDMA_OP_AQL_COPY 0
77 #define SDMA_OP_AQL_BARRIER_OR 0
80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
H A Dgfx_v10_0.c60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
69 …R_CONFIG__NUM_PKRS__SHIFT 0x8
70 …__NUM_PKRS_MASK 0x00000700L
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
[all …]
H A Dgfx_v9_0.c63 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
64 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
66 #define mmGCEA_PROBE_MAP 0x070c
67 #define mmGCEA_PROBE_MAP_BASE_IDX 0
135 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03
136 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
137 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04
138 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0
139 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09
140 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c32 * @ini_mode: 0 to write 1 to read (and clear)
39 AR5K_INI_WRITE = 0, /* Default */
57 { AR5K_NOQCU_TXDP0, 0 },
58 { AR5K_NOQCU_TXDP1, 0 },
59 { AR5K_RXDP, 0 },
60 { AR5K_CR, 0 },
61 { AR5K_ISR, 0, AR5K_INI_READ },
62 { AR5K_IMR, 0 },
64 { AR5K_BSR, 0, AR5K_INI_READ },
70 { AR5K_RPGTO, 0 },
[all …]
H A Dpcu.c84 /* 1Mb -> 1Mb */ { 0,
286 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { in ath5k_hw_write_rate_duration()
294 rate = &ah->sbands[band].bitrates[0]; in ath5k_hw_write_rate_duration()
330 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) in ath5k_hw_set_ack_timeout()
337 return 0; in ath5k_hw_set_ack_timeout()
348 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) in ath5k_hw_set_cts_timeout()
355 return 0; in ath5k_hw_set_cts_timeout()
380 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; in ath5k_hw_set_lladdr()
388 return 0; in ath5k_hw_set_lladdr()
402 u16 tim_offset = 0; in ath5k_hw_set_bssid()
[all …]
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/linux/tools/testing/selftests/vfio/lib/drivers/igb/
H A De1000_defines.h13 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
16 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
17 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
18 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
19 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
20 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
23 #define E1000_WUS_EX 0x00000004 /* Directed Exact */
24 #define E1000_WUS_ARPD 0x00000020 /* Directed ARP Request */
25 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 */
26 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 */
[all …]
/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dsky2.h12 PCI_DEV_REG1 = 0x40,
13 PCI_DEV_REG2 = 0x44,
14 PCI_DEV_STATUS = 0x7c,
15 PCI_DEV_REG3 = 0x80,
16 PCI_DEV_REG4 = 0x84,
17 PCI_DEV_REG5 = 0x88,
18 PCI_CFG_REG_0 = 0x90,
19 PCI_CFG_REG_1 = 0x94,
21 PSM_CONFIG_REG0 = 0x98,
22 PSM_CONFIG_REG1 = 0x9C,
[all …]
H A Dskge.h10 #define PCI_DEV_REG1 0x40
11 #define PCI_PHY_COMA 0x8000000
12 #define PCI_VIO 0x2000000
14 #define PCI_DEV_REG2 0x44
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
19 B0_RAP = 0x0000,
20 B0_CTST = 0x0004,
21 B0_LED = 0x0006,
22 B0_POWER_CTRL = 0x0007,
23 B0_ISRC = 0x0008,
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
43 #define PLLC_OUT 0x84
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-dif.h23 {3000000, DIF_BPF_COEFF01, 0x00000002},
24 {3000000, DIF_BPF_COEFF23, 0x00080012},
25 {3000000, DIF_BPF_COEFF45, 0x001e0024},
26 {3000000, DIF_BPF_COEFF67, 0x001bfff8},
27 {3000000, DIF_BPF_COEFF89, 0xffb4ff50},
28 {3000000, DIF_BPF_COEFF1011, 0xfed8fe68},
29 {3000000, DIF_BPF_COEFF1213, 0xfe24fe34},
30 {3000000, DIF_BPF_COEFF1415, 0xfebaffc7},
31 {3000000, DIF_BPF_COEFF1617, 0x014d031f},
32 {3000000, DIF_BPF_COEFF1819, 0x04f0065d},
[all …]

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