Lines Matching +full:0 +full:x0007ffff
13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
75 #define RIO_TT_CODE_8 0x00000000
76 #define RIO_TT_CODE_16 0x00000001
86 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
96 #define TSI721_PCIECFG_MSIXTBL 0x0a4
97 #define TSI721_MSIXTBL_OFFSET 0x2c000
98 #define TSI721_PCIECFG_MSIXPBA 0x0a8
99 #define TSI721_MSIXPBA_OFFSET 0x2a000
100 #define TSI721_PCIECFG_EPCTL 0x400
106 #define TSI721_RIO_EM_INT_STAT 0x10910
107 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
109 #define TSI721_RIO_EM_INT_ENABLE 0x10914
110 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
112 #define TSI721_RIO_EM_DEV_INT_EN 0x10930
113 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
119 #define TSI721_RIO_PW_CTL 0x10a04
120 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
121 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
126 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
127 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
128 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
130 #define TSI721_RIO_PW_RX_STAT 0x10a10
131 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
132 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
133 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
134 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
135 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
136 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
138 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
146 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
147 #define TSI721_IDQ_SUSPEND 0x00000002
148 #define TSI721_IDQ_INIT 0x00000001
150 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
151 #define TSI721_IDQ_RUN 0x00200000
153 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
154 #define TSI721_IDQ_MASK_MASK 0xffff0000
155 #define TSI721_IDQ_MASK_PATT 0x0000ffff
157 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
158 #define TSI721_IDQ_RP_PTR 0x0007ffff
160 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
161 #define TSI721_IDQ_WP_PTR 0x0007ffff
163 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
164 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
165 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
166 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
171 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
172 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
173 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
174 #define TSI721_SR_CHINT_ODBOK 0x00000020
175 #define TSI721_SR_CHINT_IDBQRCV 0x00000010
176 #define TSI721_SR_CHINT_SUSP 0x00000008
177 #define TSI721_SR_CHINT_ODBTO 0x00000004
178 #define TSI721_SR_CHINT_ODBRTRY 0x00000002
179 #define TSI721_SR_CHINT_ODBERR 0x00000001
180 #define TSI721_SR_CHINT_ALL 0x0000003f
184 #define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20)
185 #define TSI721_IBWIN_LB_BA 0xfffff000
186 #define TSI721_IBWIN_LB_WEN 0x00000001
188 #define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20)
189 #define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20)
190 #define TSI721_IBWIN_SZ_SIZE 0x00001f00
193 #define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20)
194 #define TSI721_IBWIN_TLA_ADD 0xfffff000
195 #define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20)
197 #define TSI721_SR2PC_GEN_INTE 0x29800
198 #define TSI721_SR2PC_PWE 0x29804
199 #define TSI721_SR2PC_GEN_INT 0x29808
201 #define TSI721_DEV_INTE 0x29840
202 #define TSI721_DEV_INT 0x29844
203 #define TSI721_DEV_INTSET 0x29848
204 #define TSI721_DEV_INT_BDMA_CH 0x00002000
205 #define TSI721_DEV_INT_BDMA_NCH 0x00001000
206 #define TSI721_DEV_INT_SMSG_CH 0x00000800
207 #define TSI721_DEV_INT_SMSG_NCH 0x00000400
208 #define TSI721_DEV_INT_SR2PC_CH 0x00000200
209 #define TSI721_DEV_INT_SRIO 0x00000020
211 #define TSI721_DEV_CHAN_INTE 0x2984c
212 #define TSI721_DEV_CHAN_INT 0x29850
214 #define TSI721_INT_SR2PC_CHAN_M 0xff000000
216 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000
218 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00
220 #define TSI721_INT_BDMA_CHAN_M 0x000000ff
228 #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
229 #define TSI721_OBWINLB_BA 0xffff8000
230 #define TSI721_OBWINLB_WEN 0x00000001
232 #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
234 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
235 #define TSI721_OBWINSZ_SIZE 0x00001f00
238 #define TSI721_ZONE_SEL 0x41300
239 #define TSI721_ZONE_SEL_RD_WRB 0x00020000
240 #define TSI721_ZONE_SEL_GO 0x00010000
241 #define TSI721_ZONE_SEL_WIN 0x00000038
242 #define TSI721_ZONE_SEL_ZONE 0x00000007
244 #define TSI721_LUT_DATA0 0x41304
245 #define TSI721_LUT_DATA0_ADD 0xfffff000
246 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00
247 #define TSI721_LUT_DATA0_NREAD 0x00000100
248 #define TSI721_LUT_DATA0_MNTRD 0x00000200
249 #define TSI721_LUT_DATA0_RDCRF 0x00000020
250 #define TSI721_LUT_DATA0_WRCRF 0x00000010
251 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f
252 #define TSI721_LUT_DATA0_NWR 0x00000001
253 #define TSI721_LUT_DATA0_MNTWR 0x00000002
254 #define TSI721_LUT_DATA0_NWR_R 0x00000004
256 #define TSI721_LUT_DATA1 0x41308
258 #define TSI721_LUT_DATA2 0x4130c
259 #define TSI721_LUT_DATA2_HC 0xff000000
260 #define TSI721_LUT_DATA2_ADD65 0x000c0000
261 #define TSI721_LUT_DATA2_TT 0x00030000
262 #define TSI721_LUT_DATA2_DSTID 0x0000ffff
264 #define TSI721_PC2SR_INTE 0x41310
266 #define TSI721_DEVCTL 0x48004
267 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
269 #define TSI721_I2C_INT_ENABLE 0x49120
273 * x = 0..7
276 #define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
278 #define TSI721_DMAC_DWRCNT 0x000
279 #define TSI721_DMAC_DRDCNT 0x004
281 #define TSI721_DMAC_CTL 0x008
282 #define TSI721_DMAC_CTL_SUSP 0x00000002
283 #define TSI721_DMAC_CTL_INIT 0x00000001
285 #define TSI721_DMAC_INT 0x00c
286 #define TSI721_DMAC_INT_STFULL 0x00000010
287 #define TSI721_DMAC_INT_DONE 0x00000008
288 #define TSI721_DMAC_INT_SUSP 0x00000004
289 #define TSI721_DMAC_INT_ERR 0x00000002
290 #define TSI721_DMAC_INT_IOFDONE 0x00000001
291 #define TSI721_DMAC_INT_ALL 0x0000001f
293 #define TSI721_DMAC_INTSET 0x010
295 #define TSI721_DMAC_STS 0x014
296 #define TSI721_DMAC_STS_ABORT 0x00400000
297 #define TSI721_DMAC_STS_RUN 0x00200000
298 #define TSI721_DMAC_STS_CS 0x001f0000
300 #define TSI721_DMAC_INTE 0x018
302 #define TSI721_DMAC_DPTRL 0x024
303 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0
305 #define TSI721_DMAC_DPTRH 0x028
307 #define TSI721_DMAC_DSBL 0x02c
308 #define TSI721_DMAC_DSBL_MASK 0xffffffc0
310 #define TSI721_DMAC_DSBH 0x030
312 #define TSI721_DMAC_DSSZ 0x034
313 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
316 #define TSI721_DMAC_DSRP 0x038
317 #define TSI721_DMAC_DSRP_MASK 0x0007ffff
319 #define TSI721_DMAC_DSWP 0x03c
320 #define TSI721_DMAC_DSWP_MASK 0x0007ffff
322 #define TSI721_BDMA_INTE 0x5f000
340 * x = 0..7
343 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
345 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
347 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
348 #define TSI721_OBDMAC_CTL_MASK 0x00000007
349 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
350 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
351 #define TSI721_OBDMAC_CTL_INIT 0x00000001
353 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
354 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
355 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
356 #define TSI721_OBDMAC_INT_MASK 0x0000001F
357 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010
358 #define TSI721_OBDMAC_INT_DONE 0x00000008
359 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
360 #define TSI721_OBDMAC_INT_ERROR 0x00000002
361 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
364 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
365 #define TSI721_OBDMAC_STS_MASK 0x007f0000
366 #define TSI721_OBDMAC_STS_ABORT 0x00400000
367 #define TSI721_OBDMAC_STS_RUN 0x00200000
368 #define TSI721_OBDMAC_STS_CS 0x001f0000
370 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
371 #define TSI721_OBDMAC_PWE_MASK 0x00000002
372 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
374 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
375 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
377 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
378 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
380 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
381 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
383 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
384 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff
386 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
387 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
389 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
390 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
392 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
393 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
395 #define TSI721_RQRPTO 0x60010
396 #define TSI721_RQRPTO_MASK 0x00ffffff
401 * x = 0..7
404 #define TSI721_IB_DEVID_GLOBAL 0xffff
405 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
406 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
408 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
409 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff
412 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
413 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
415 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
416 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
418 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
419 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
421 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
422 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
424 #define TSI721_IB_DEVID 0x60020
425 #define TSI721_IB_DEVID_MASK 0x0000ffff
427 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
428 #define TSI721_IBDMAC_CTL_MASK 0x00000003
429 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
430 #define TSI721_IBDMAC_CTL_INIT 0x00000001
432 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
433 #define TSI721_IBDMAC_STS_MASK 0x007f0000
434 #define TSI721_IBSMAC_STS_ABORT 0x00400000
435 #define TSI721_IBSMAC_STS_RUN 0x00200000
436 #define TSI721_IBSMAC_STS_CS 0x001f0000
438 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
439 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
440 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
441 #define TSI721_IBDMAC_INT_MASK 0x0000100f
442 #define TSI721_IBDMAC_INT_SRTO 0x00001000
443 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
444 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
445 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
446 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
449 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
450 #define TSI721_IBDMAC_PWE_MASK 0x00001700
451 #define TSI721_IBDMAC_PWE_SRTO 0x00001000
452 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
453 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
454 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
456 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
457 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
458 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
460 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
461 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff
463 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
464 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
466 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
467 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
469 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
470 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
476 #define TSI721_SMSG_PWE 0x6a004
478 #define TSI721_SMSG_INTE 0x6a000
479 #define TSI721_SMSG_INT 0x6a008
480 #define TSI721_SMSG_INTSET 0x6a010
481 #define TSI721_SMSG_INT_MASK 0x0086ffff
482 #define TSI721_SMSG_INT_UNS_RSP 0x00800000
483 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000
484 #define TSI721_SMSG_INT_ECC_COR 0x00020000
485 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
486 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
488 #define TSI721_SMSG_ECC_LOG 0x6a014
489 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007
490 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
491 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
493 #define TSI721_RETRY_GEN_CNT 0x6a100
494 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
496 #define TSI721_RETRY_RX_CNT 0x6a104
497 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff
499 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
500 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
502 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
503 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
512 #define TSI721_DMAD_DEVID 0x0000ffff
513 #define TSI721_DMAD_CRF 0x00010000
514 #define TSI721_DMAD_PRIO 0x00060000
515 #define TSI721_DMAD_RTYPE 0x00780000
516 #define TSI721_DMAD_IOF 0x08000000
517 #define TSI721_DMAD_DTYPE 0xe0000000
521 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
522 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
523 #define TSI721_DMAD_TT 0x0c000000
524 #define TSI721_DMAD_RADDR0 0xc0000000
531 #define TSI721_DMAD_CFGOFF 0x00ffffff
532 #define TSI721_DMAD_HOPCNT 0xff000000
557 #define TSI721_IMD_DEVID 0x0000ffff
558 #define TSI721_IMD_CRF 0x00010000
559 #define TSI721_IMD_PRIO 0x00060000
560 #define TSI721_IMD_TT 0x00180000
561 #define TSI721_IMD_DTYPE 0xe0000000
565 #define TSI721_IMD_BCOUNT 0x00000ff8
566 #define TSI721_IMD_SSIZE 0x0000f000
567 #define TSI721_IMD_LETER 0x00030000
568 #define TSI721_IMD_XMBOX 0x003c0000
569 #define TSI721_IMD_MBOX 0x00c00000
570 #define TSI721_IMD_CS 0x78000000
571 #define TSI721_IMD_HO 0x80000000
585 #define TSI721_OMD_DEVID 0x0000ffff
586 #define TSI721_OMD_CRF 0x00010000
587 #define TSI721_OMD_PRIO 0x00060000
588 #define TSI721_OMD_IOF 0x08000000
589 #define TSI721_OMD_DTYPE 0xe0000000
590 #define TSI721_OMD_RSRVD 0x17f80000
594 #define TSI721_OMD_BCOUNT 0x00000ff8
595 #define TSI721_OMD_SSIZE 0x0000f000
596 #define TSI721_OMD_LETER 0x00030000
597 #define TSI721_OMD_XMBOX 0x003c0000
598 #define TSI721_OMD_MBOX 0x00c00000
599 #define TSI721_OMD_TT 0x0c000000
638 NREAD = 0,
656 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
659 SMSG_INT_NONE = 0x00000000,
660 SMSG_INT_ECC_COR_CH = 0x000000ff,
661 SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
662 SMSG_INT_ECC_COR = 0x00020000,
663 SMSG_INT_ECC_NCOR = 0x00040000,
664 SMSG_INT_UNS_RSP = 0x00800000,
665 SMSG_INT_ALL = 0x0006ffff
765 TSI721_USING_MSI = (1 << 0),
772 * MSI-X Table Entries (0 ... 69)
774 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
919 #define tsi721_dma_stop_all(priv) do {} while (0)
920 #define tsi721_unregister_dma(priv) do {} while (0)