Lines Matching +full:0 +full:x0007ffff
36 module_param_array(mtu, int, NULL, 0);
37 module_param_array(media, charp, NULL, 0);
38 module_param_array(vlan, int, NULL, 0);
39 module_param_array(jumbo, int, NULL, 0);
40 module_param(tx_flow, int, 0);
41 module_param(rx_flow, int, 0);
42 module_param(copy_thresh, int, 0);
43 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
60 static const int multicast_filter_limit = 0x40;
105 pdev->device == 0x4000 && in is_support_rmon_mmio()
106 pdev->revision == 0x0c; in is_support_rmon_mmio()
145 ioaddr = pci_iomap(pdev, 0, 0); in rio_probe1()
152 ioaddr = pci_iomap(pdev, 1, 0); in rio_probe1()
170 np->an_enable = 0; in rio_probe1()
171 if (strcmp (media[card_idx], "auto") == 0 || in rio_probe1()
172 strcmp (media[card_idx], "autosense") == 0 || in rio_probe1()
173 strcmp (media[card_idx], "0") == 0 ) { in rio_probe1()
175 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 || in rio_probe1()
176 strcmp (media[card_idx], "4") == 0) { in rio_probe1()
179 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 || in rio_probe1()
180 strcmp (media[card_idx], "3") == 0) { in rio_probe1()
182 np->full_duplex = 0; in rio_probe1()
183 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || in rio_probe1()
184 strcmp (media[card_idx], "2") == 0) { in rio_probe1()
187 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || in rio_probe1()
188 strcmp (media[card_idx], "1") == 0) { in rio_probe1()
190 np->full_duplex = 0; in rio_probe1()
191 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 || in rio_probe1()
192 strcmp (media[card_idx], "6") == 0) { in rio_probe1()
195 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 || in rio_probe1()
196 strcmp (media[card_idx], "5") == 0) { in rio_probe1()
198 np->full_duplex = 0; in rio_probe1()
203 if (jumbo[card_idx] != 0) { in rio_probe1()
207 np->jumbo = 0; in rio_probe1()
208 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE) in rio_probe1()
211 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ? in rio_probe1()
212 vlan[card_idx] : 0; in rio_probe1()
213 if (rx_coalesce > 0 && rx_timeout > 0) { in rio_probe1()
218 np->tx_flow = (tx_flow == 0) ? 0 : 1; in rio_probe1()
219 np->rx_flow = (rx_flow == 0) ? 0 : 1; in rio_probe1()
229 #if 0 in rio_probe1()
261 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0; in rio_probe1()
262 np->link_status = 0; in rio_probe1()
294 return 0; in rio_probe1()
319 int i, phy_found = 0; in find_miiphy()
323 for (i = 31; i >= 0; i--) { in find_miiphy()
325 if (mii_status != 0xffff && mii_status != 0x0000) { in find_miiphy()
334 return 0; in find_miiphy()
350 for (i = 0; i < 128; i++) in parse_eeprom()
368 return 0; in parse_eeprom()
372 return 0; in parse_eeprom()
376 i = 0x30; in parse_eeprom()
381 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) { in parse_eeprom()
386 case 0: /* Format version */ in parse_eeprom()
389 return 0; in parse_eeprom()
413 return 0; in parse_eeprom()
428 if (np->led_mode & 0x01) in rio_set_led_mode()
430 if (np->led_mode & 0x02) in rio_set_led_mode()
432 if (np->led_mode & 0x08) in rio_set_led_mode()
450 for (i = 0; i < RX_RING_SIZE; i++) { in free_list()
459 np->rx_ring[i].status = 0; in free_list()
460 np->rx_ring[i].fraginfo = 0; in free_list()
462 for (i = 0; i < TX_RING_SIZE; i++) { in free_list()
478 np->cur_rx = 0; in rio_reset_ring()
479 np->cur_tx = 0; in rio_reset_ring()
480 np->old_rx = 0; in rio_reset_ring()
481 np->old_tx = 0; in rio_reset_ring()
483 for (i = 0; i < TX_RING_SIZE; i++) in rio_reset_ring()
486 for (i = 0; i < RX_RING_SIZE; i++) in rio_reset_ring()
487 np->rx_ring[i].status = 0; in rio_reset_ring()
500 for (i = 0; i < TX_RING_SIZE; i++) { in alloc_list()
508 for (i = 0; i < RX_RING_SIZE; i++) { in alloc_list()
531 return 0; in alloc_list()
556 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230); in rio_hw_init()
559 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) { in rio_hw_init()
561 mii_write(dev, np->phy_addr, 31, 0x0001); in rio_hw_init()
562 mii_write(dev, np->phy_addr, 27, 0x01e0); in rio_hw_init()
563 mii_write(dev, np->phy_addr, 31, 0x0002); in rio_hw_init()
564 mii_write(dev, np->phy_addr, 27, 0xeb8e); in rio_hw_init()
565 mii_write(dev, np->phy_addr, 31, 0x0000); in rio_hw_init()
566 mii_write(dev, np->phy_addr, 30, 0x005e); in rio_hw_init()
568 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700); in rio_hw_init()
577 if (np->jumbo != 0) in rio_hw_init()
582 dw32(RFDListPtr1, 0); in rio_hw_init()
588 for (i = 0; i < 3; i++) in rio_hw_init()
596 dw8(RxDMAPollPeriod, 0x20); in rio_hw_init()
597 dw8(TxDMAPollPeriod, 0xff); in rio_hw_init()
598 dw8(RxDMABurstThresh, 0x30); in rio_hw_init()
599 dw8(RxDMAUrgentThresh, 0x30); in rio_hw_init()
601 dw32(RmonStatMask, 0x0007ffff); in rio_hw_init()
608 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10); in rio_hw_init()
611 /* Length/Type should be 0x8100 */ in rio_hw_init()
612 dw32(VLANTag, 0x8100 << 16 | np->vlan); in rio_hw_init()
621 macctrl = 0; in rio_hw_init()
622 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; in rio_hw_init()
623 macctrl |= (np->full_duplex) ? DuplexSelect : 0; in rio_hw_init()
624 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; in rio_hw_init()
625 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; in rio_hw_init()
635 dw16(IntEnable, 0); in rio_hw_stop()
660 timer_setup(&np->timer, rio_timer, 0); in rio_open()
667 return 0; in rio_open()
684 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) { in rio_timer()
692 np->rx_ring[entry].fraginfo = 0; in rio_timer()
705 np->rx_ring[entry].status = 0; in rio_timer()
721 rio_free_tx(dev, 0); in rio_tx_timeout()
722 dev->if_port = 0; in rio_tx_timeout()
733 u64 tfc_vlan_tag = 0; in start_xmit()
735 if (np->link_status == 0) { /* Link Down */ in start_xmit()
743 #if 0 in start_xmit()
761 if (entry % np->tx_coalesce == 0 || np->speed == 10) in start_xmit()
772 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000); in start_xmit()
787 dw32(TFDListPtr1, 0); in start_xmit()
801 int handled = 0; in rio_interrupt()
807 if (int_status == 0 || --cnt < 0) in rio_interrupt()
817 if (tx_status & 0x01) in rio_interrupt()
838 unsigned long flag = 0; in rio_free_tx()
887 frame_id = (tx_status & 0xffff0000); in tx_error()
891 if (tx_status & 0x10) { in tx_error()
893 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10); in tx_error()
898 for (i = 50; i > 0; i--) { in tx_error()
908 dw32(TFDListPtr1, 0); in tx_error()
913 if (tx_status & 0x04) { in tx_error()
918 for (i = 50; i > 0; i--) { in tx_error()
929 if (tx_status & 0x08) in tx_error()
959 pkt_len = frame_status & 0xffff; in receive_packet()
960 if (--cnt < 0) in receive_packet()
1002 #if 0 in receive_packet()
1004 if (np->pdev->pci_rev_id >= 0x0c && in receive_packet()
1023 np->rx_ring[entry].fraginfo = 0; in receive_packet()
1037 np->rx_ring[entry].status = 0; in receive_packet()
1042 return 0; in receive_packet()
1054 if (mii_wait_link (dev, 10) == 0) { in rio_error()
1064 macctrl = 0; in rio_error()
1065 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; in rio_error()
1066 macctrl |= (np->full_duplex) ? DuplexSelect : 0; in rio_error()
1068 TxFlowControlEnable : 0; in rio_error()
1070 RxFlowControlEnable : 0; in rio_error()
1076 np->link_status = 0; in rio_error()
1147 for (int i = 0x100; i <= 0x150; i += 4) in get_stats()
1202 for (int i = 0x100; i <= 0x150; i += 4) in clear_stats()
1209 return 0; in clear_stats()
1218 u16 rx_mode = 0; in set_multicast()
1220 hash_table[0] = hash_table[1] = 0; in set_multicast()
1221 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */ in set_multicast()
1222 hash_table[1] |= 0x02000000; in set_multicast()
1237 int bit, index = 0; in set_multicast()
1241 for (bit = 0; bit < 6; bit++) in set_multicast()
1254 dw32(HashTable0, hash_table[0]); in set_multicast()
1309 return 0; in rio_get_link_ksettings()
1322 return 0; in rio_set_link_ksettings()
1326 return 0; in rio_set_link_ksettings()
1329 np->an_enable = 0; in rio_set_link_ksettings()
1350 return 0; in rio_set_link_ksettings()
1389 return 0; in rio_ioctl()
1392 #define EEP_READ 0x0200
1393 #define EEP_BUSY 0x8000
1401 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff)); in read_eeprom()
1402 while (i-- > 0) { in read_eeprom()
1406 return 0; in read_eeprom()
1410 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1411 MII_DUPLEX = 0x08,
1421 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE; in mii_sendbit()
1435 data = (dr8(PhyCtrl) & 0xf8) | MII_READ; in mii_getbit()
1448 for (i = len - 1; i >= 0; i--) { in mii_send_bits()
1458 u32 retval = 0; in mii_read()
1461 mii_send_bits (dev, 0xffffffff, 32); in mii_read()
1464 cmd = (0x06 << 10 | phy_addr << 5 | reg_num); in mii_read()
1470 for (i = 0; i < 16; i++) { in mii_read()
1476 return (retval >> 1) & 0xffff; in mii_read()
1479 return 0; in mii_read()
1487 mii_send_bits (dev, 0xffffffff, 32); in mii_write()
1489 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ in mii_write()
1490 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; in mii_write()
1494 return 0; in mii_write()
1509 return 0; in mii_wait_link()
1511 } while (--wait > 0); in mii_wait_link()
1543 np->full_duplex = 0; in mii_get_media()
1551 np->full_duplex = 0; in mii_get_media()
1559 np->full_duplex = 0; in mii_get_media()
1566 np->tx_flow = 0; in mii_get_media()
1579 case 0: in mii_get_media()
1597 return 0; in mii_get_media()
1656 bmcr = 0x1940; /* must be 0x1940 */ in mii_set_media()
1661 mii_write (dev, phy_addr, MII_ADVERTISE, 0); in mii_set_media()
1677 #if 0 in mii_set_media()
1681 mscr &= ~MII_MSCR_CFG_VALUE = 0; in mii_set_media()
1686 return 0; in mii_set_media()
1714 np->full_duplex = 0; in mii_get_media_pcs()
1720 np->tx_flow = 0; in mii_get_media_pcs()
1742 return 0; in mii_get_media_pcs()
1785 bmcr = 0; in mii_set_media_pcs()
1792 mii_write (dev, phy_addr, MII_ADVERTISE, 0); in mii_set_media_pcs()
1794 return 0; in mii_set_media_pcs()
1813 return 0; in rio_close()
1845 return 0; in rio_suspend()
1851 return 0; in rio_suspend()
1860 return 0; in rio_resume()
1869 return 0; in rio_resume()