84 /* 1Mb	-> 1Mb	*/	{ 0,
286 	for (i = 0; i < ah->sbands[band].n_bitrates; i++) {  in ath5k_hw_write_rate_duration()
294 			rate = &ah->sbands[band].bitrates[0];  in ath5k_hw_write_rate_duration()
330 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))  in ath5k_hw_set_ack_timeout()
337 	return 0;  in ath5k_hw_set_ack_timeout()
348 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))  in ath5k_hw_set_cts_timeout()
355 	return 0;  in ath5k_hw_set_cts_timeout()
380 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;  in ath5k_hw_set_lladdr()
388 	return 0;  in ath5k_hw_set_lladdr()
402 	u16 tim_offset = 0;  in ath5k_hw_set_bssid()
418 			   ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),  in ath5k_hw_set_bssid()
421 	if (common->curaid == 0) {  in ath5k_hw_set_bssid()
427 			    tim_offset ? tim_offset + 4 : 0);  in ath5k_hw_set_bssid()
429 	ath5k_hw_enable_pspoll(ah, NULL, 0);  in ath5k_hw_set_bssid()
485 	u32 data, filter = 0;  in ath5k_hw_get_rx_filter()
514 	u32 data = 0;  in ath5k_hw_set_rx_filter()
540 	ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);  in ath5k_hw_set_rx_filter()
584 	for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {  in ath5k_hw_get_tsf64()
611 	ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);  in ath5k_hw_set_tsf64()
612 	ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);  in ath5k_hw_set_tsf64()
663 			timer1 = 0xffffffff;  in ath5k_hw_init_beacon_timers()
664 			timer2 = 0xffffffff;  in ath5k_hw_init_beacon_timers()
666 			timer1 = 0x0000ffff;  in ath5k_hw_init_beacon_timers()
667 			timer2 = 0x0007ffff;  in ath5k_hw_init_beacon_timers()
695 		ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);  in ath5k_hw_init_beacon_timers()
751 	    ((a | 0x10000) - b == intval - window) ||		/* 3.) */  in ath5k_check_timer_win()
752 	    ((b | 0x10000) - a == window))			/* 4.) */  in ath5k_check_timer_win()
885 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;  in ath5k_hw_set_opmode()
889 			(AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));  in ath5k_hw_set_opmode()
891 	beacon_reg = 0;  in ath5k_hw_set_opmode()
916 				AR5K_STA_ID1_PWR_SV : 0);  in ath5k_hw_set_opmode()
921 				AR5K_STA_ID1_NO_PSPOLL : 0);  in ath5k_hw_set_opmode()
942 	return 0;  in ath5k_hw_set_opmode()
974 	 * register is read it might return 0x40 if we haven't  in ath5k_hw_pcu_init()
985 		ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);  in ath5k_hw_pcu_init()
986 		ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);  in ath5k_hw_pcu_init()
994 			AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),  in ath5k_hw_pcu_init()
999 	if (ah->ah_coverage_class > 0)  in ath5k_hw_pcu_init()