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Searched +full:0 +full:x0003ffff (Results 1 – 25 of 32) sorted by relevance

12

/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd/sys/dev/sfxge/common/
H A Dsiena_nic.c60 if (req.emr_rc != 0) { in siena_nic_get_partn_mask()
72 return (0); in siena_nic_get_partn_mask()
104 &capabilities, mac_addr)) != 0) in siena_board_cfg()
167 if (rc != 0) { in siena_board_cfg()
188 encp->enc_fw_assisted_tso_v2_n_contexts = 0; in siena_board_cfg()
205 encp->enc_filter_action_mark_max = 0; in siena_board_cfg()
207 return (0); in siena_board_cfg()
227 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) in siena_phy_cfg()
236 return (0); in siena_phy_cfg()
244 #define SIENA_BIU_MAGIC0 0x01234567
[all …]
/freebsd/contrib/mknod/
H A Dpack_dev.c69 portdev_t dev = 0; in pack_native()
72 dev = makedev(numbers[0], numbers[1]); in pack_native()
73 if ((u_long)major(dev) != numbers[0]) in pack_native()
86 portdev_t dev = 0; in pack_netbsd()
89 dev = makedev_netbsd(numbers[0], numbers[1]); in pack_netbsd()
90 if ((u_long)major_netbsd(dev) != numbers[0]) in pack_netbsd()
100 #define major_freebsd(x) ((int32_t)(((x) & 0x0000ff00) >> 8))
101 #define minor_freebsd(x) ((int32_t)(((x) & 0xffff00ff) >> 0))
102 #define makedev_freebsd(x,y) ((portdev_t)((((x) << 8) & 0x0000ff00) | \
103 (((y) << 0) & 0xffff00ff)))
[all …]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x020000
[all...]
/freebsd/contrib/libarchive/libarchive/
H A Darchive_pack_dev.c83 #define major(x) ((int)(0x00ff & ((x) >> 8)))
84 #define minor(x) ((int)(0xffff00ff & (x)))
85 #define makedev(maj,min) ((0xff00 & ((maj)<<8)) | (0xffff00ff & (min)))
108 dev_t dev = 0;
111 dev = apd_makedev(numbers[0], numbers[1]);
112 if ((unsigned long)major(dev) != numbers[0])
125 dev_t dev = 0; in pack_native()
128 dev = makedev_netbsd(numbers[0], numbers[1]);
129 if ((unsigned long)major_netbsd(dev) != numbers[0])
[all...]
/freebsd/sys/arm/ti/
H A Dti_adcreg.h30 #define ADC_REVISION 0x000
31 #define ADC_REV_SCHEME_MSK 0xc0000000
33 #define ADC_REV_FUNC_MSK 0x0fff0000
35 #define ADC_REV_RTL_MSK 0x0000f800
37 #define ADC_REV_MAJOR_MSK 0x00000700
39 #define ADC_REV_CUSTOM_MSK 0x000000c0
41 #define ADC_REV_MINOR_MSK 0x0000003f
42 #define ADC_SYSCFG 0x010
43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0
45 #define ADC_IRQSTATUS_RAW 0x024
[all …]
/freebsd/sys/arm/allwinner/
H A Da10_dmac.h30 #define AWIN_DMA_IRQ_EN_REG 0x0000
31 #define AWIN_DMA_IRQ_PEND_STA_REG 0x0004
32 #define AWIN_NDMA_AUTO_GATE_REG 0x0008
33 #define AWIN_NDMA_REG(n) (0x100+0x20*(n))
34 #define AWIN_NDMA_CTL_REG 0x0000
35 #define AWIN_NDMA_SRC_ADDR_REG 0x0004
36 #define AWIN_NDMA_DEST_ADDR_REG 0x0008
37 #define AWIN_NDMA_BC_REG 0x000c
38 #define AWIN_DDMA_REG(n) (0x300+0x20*(n))
39 #define AWIN_DDMA_CTL_REG 0x0000
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dcoredump.c16 .start = 0x00800000,
17 .len = 0x0004ffff,
21 .start = 0x00900000,
22 .len = 0x00037fff,
26 .start = 0x02200000,
27 .len = 0x0003ffff,
31 .start = 0x00400000,
32 .len = 0x00067fff,
36 .start = 0xe0000000,
37 .len = 0x0015ffff,
[all …]
/freebsd/sys/dev/otus/
H A Dif_otusreg.h30 #define AR_FW_DOWNLOAD 0x30
31 #define AR_FW_DOWNLOAD_COMPLETE 0x31
36 #define AR_FW_INIT_ADDR 0x102800
37 #define AR_FW_MAIN_ADDR 0x200000
38 #define AR_USB_MODE_CTRL 0x1e1108
43 #define AR_MAC_REG_BASE 0x1c3000
44 #define AR_MAC_REG_DMA_TRIGGER (AR_MAC_REG_BASE + 0xd30)
45 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610)
46 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614)
47 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldELFMips.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
57 LLVM_DEBUG(dbgs() << "evaluateMIPS32Relocation, LocalAddress: 0x" in evaluateMIPS32Relocation()
59 << " FinalAddress: 0x" in evaluateMIPS32Relocation()
61 << " Value: 0x" << format("%llx", Value) << " Type: 0x" in evaluateMIPS32Relocation()
74 return (Value + 0x8000) >> 16; in evaluateMIPS32Relocation()
87 return (Value - (FinalAddress & ~0x3)) >> 2; in evaluateMIPS32Relocation()
99 return (Value - FinalAddress + 0x8000) >> 16; in evaluateMIPS32Relocation()
112 LLVM_DEBUG(dbgs() << "evaluateMIPS64Relocation, LocalAddress: 0x" in evaluateMIPS64Relocation()
114 << " FinalAddress: 0x" in evaluateMIPS64Relocation()
116 << " Value: 0x" << format("%llx", Value) << " Type: 0x" in evaluateMIPS64Relocation()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DARMWinEH.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
37 /// 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
38 /// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
64 /// register. If the R bit is set to 0, then only integer registers are
70 /// floating-point. 0 indicates integer, 1 indicates floating-point. The
79 /// allocated for this function. Only values between 0x000 and
80 /// 0x3f3 can be directly encoded. If the value is 0x3f4 or
82 /// - Bit 0-1
93 /// - IF Ret is 0:
109 : BeginAddress(Data[0]), UnwindData(Data[1]) {} in RuntimeFunction()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_kg.h81 uint32_t kgse_dv0; /**< KeyGen Scheme Entry Default Value 0 */
99 #define FM_KG_KGAR_GO 0x80000000
100 #define FM_KG_KGAR_READ 0x40000000
101 #define FM_KG_KGAR_WRITE 0x00000000
102 #define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
103 #define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
105 #define KG_SCH_PP_SHIFT_HIGH 0x80000000
106 #define KG_SCH_PP_NO_GEN 0x10000000
107 #define KG_SCH_PP_SHIFT_LOW 0x0000F000
108 #define KG_SCH_MODE_NIA_PLCR 0x40000000
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_misc.c37 *hangs = 0; in ar9300_get_hw_hangs()
39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) in ar9300_get_hw_hangs()
50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) in ar9300_get_hw_hangs()
69 #if 0 in ar9300_mac_to_usec()
84 #if 0 in ar9300_mac_to_clks()
145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { in ar9300_set_regulatory_domain()
151 #if 0 in ar9300_set_regulatory_domain()
[all …]
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dhw.h23 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
24 #define QCA988X_2_0_DEVICE_ID (0x003c)
25 #define QCA6164_2_1_DEVICE_ID (0x0041)
26 #define QCA6174_2_1_DEVICE_ID (0x003e)
27 #define QCA6174_3_2_DEVICE_ID (0x0042)
28 #define QCA99X0_2_0_DEVICE_ID (0x0040)
29 #define QCA9888_2_0_DEVICE_ID (0x0056)
30 #define QCA9984_1_0_DEVICE_ID (0x0046)
31 #define QCA9377_1_0_DEVICE_ID (0x0042)
32 #define QCA9887_1_0_DEVICE_ID (0x0050)
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
H A Dar5416.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
28 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9001/
H A Dar9160.ini21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
[all …]
/freebsd/crypto/openssl/crypto/bn/
H A Dbn_nist.c22 {0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFEULL, 0xFFFFFFFFFFFFFFFFULL},
23 {0xFFFFFFFFFFFFFFFEULL, 0xFFFFFFFFFFFFFFFDULL, 0xFFFFFFFFFFFFFFFFULL},
24 {0xFFFFFFFFFFFFFFFDULL, 0xFFFFFFFFFFFFFFFCULL, 0xFFFFFFFFFFFFFFFFULL}
28 0x0000000000000001ULL, 0x0000000000000002ULL, 0x0000000000000001ULL,
29 0xFFFFFFFFFFFFFFFEULL, 0xFFFFFFFFFFFFFFFDULL, 0xFFFFFFFFFFFFFFFFULL
33 {0x0000000000000001ULL, 0xFFFFFFFF00000000ULL,
34 0xFFFFFFFFFFFFFFFFULL, 0x00000000FFFFFFFFULL},
35 {0x0000000000000002ULL, 0xFFFFFFFE00000000ULL,
36 0xFFFFFFFFFFFFFFFFULL, 0x00000001FFFFFFFFULL} /* this one is
41 0x0000000000000001ULL, 0xFFFFFFFE00000000ULL,
[all …]

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