Lines Matching +full:0 +full:x0003ffff
55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
77 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
81 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
84 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
87 #if 0
89 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
91 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
92 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */
94 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
95 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
96 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
101 #if 0
102 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
103 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
104 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
106 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
112 #if 0
113 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00]
114 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
115 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07]
117 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14]
119 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21]
127 #define AR_PHY_RADAR_1_CF_BIN_THRESH 0x07000000
151 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
152 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
153 #define AR_PHY_TIMING2_HT_Fine_Timing_EN 0x80000000
154 #define AR_PHY_TIMING2_DC_OFFSET 0x08000000
158 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
160 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
163 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) …
165 #define AR_PHY_TIMING4_DO_CAL 0x10000 /* perform calibration */
166 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
168 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
171 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
173 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
177 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
178 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
180 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
181 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
183 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
185 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
188 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
189 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
190 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
192 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
195 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F // [06:00]
196 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
197 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 // [13:07]
199 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 // [20:14]
201 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 // [27:21]
203 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
207 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
209 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
211 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L // [15:09]
214 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
216 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
217 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
218 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
220 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
222 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
224 #define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */
225 #define AR_PHY_RADAR_0_ENA_S 0
226 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 /* Enable FFT data */
227 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
229 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
231 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
233 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */
235 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
238 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */
239 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power
242 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */
244 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak OFDM
248 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */
249 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */
250 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */
252 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */
253 #define AR_PHY_RADAR_1_MAXLEN_S 0
255 #define AR_PHY_RADAR_EXT_ENA 0x00004000 /* Enable extension channel radar detection */
256 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
258 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
261 #define AR_PHY_PERCHAIN_CSD_chn1_2chains 0x0000001f
262 #define AR_PHY_PERCHAIN_CSD_chn1_2chains_S 0
263 #define AR_PHY_PERCHAIN_CSD_chn1_3chains 0x000003e0
265 #define AR_PHY_PERCHAIN_CSD_chn2_3chains 0x00007c00
268 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
270 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
273 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
274 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
277 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
280 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F /* Mask for kcos_theta-1 for q correction…
281 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
282 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 /* Mask for sin_theta for i correction */
284 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 /* enable IQ correction */
285 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
287 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
307 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
309 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
310 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
313 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
315 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
316 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
321 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0
323 #define AR_PHY_SGI_DSC_EXP 0x0000000F
324 #define AR_PHY_SGI_DSC_EXP_S 0
356 #define AR_PHY_PEAK_DET_ENABLE 0x00000002
368 #define AR_PHY_DIG_DC_C1_RES 0x000001ff
369 #define AR_PHY_DIG_DC_C1_RES_S 0
370 #define AR_PHY_DIG_DC_C2_RES 0x0003fe00
372 #define AR_PHY_DIG_DC_C3_RES 0x07fc0000
376 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
378 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
380 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
381 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
382 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
386 #define AR_PHY_MRC_CCK_ENABLE 0x00000001
387 #define AR_PHY_MRC_CCK_ENABLE_S 0
388 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002
419 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
421 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
423 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
424 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
425 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
427 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
429 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
431 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
432 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
434 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
436 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
438 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
440 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
443 #define AR_PHY_SETTLING_SWITCH 0x00003F80
446 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
447 #define AR_PHY_DESIRED_SZ_ADC_S 0
448 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
450 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
453 #define AR_PHY_MINCCA_PWR 0x1FF00000
455 #define AR_PHY_CCA_THRESH62 0x0007F000
457 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
459 #define AR9280_PHY_CCA_THRESH62 0x000FF000
462 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
463 #define AR_PHY_EXT_CCA0_THRESH62_S 0
465 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
466 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
467 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna …
469 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
473 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
475 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
479 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
482 #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX 0x3f
483 #define AR_PHY_TPC_7_TX_GAIN_TABLE_MAX_S (0)
487 #define AR_PHY_AGC_QUICK_DROP (0xf << AR_PHY_AGC_QUICK_DROP_S)
488 #define AR_PHY_AGC_COARSE_LOW 0x00007F80
490 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000
492 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
493 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0
495 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
497 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
500 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
503 #define AR_PHY_FIND_SIG_RELSTEP 0x1f
504 #define AR_PHY_FIND_SIG_RELSTEP_S 0
507 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
509 #define AR_PHY_RESTART_ENA 0x01 /* enable restart */
510 #define AR_PHY_DC_RESTART_DIS 0x40000000 /* disable DC restart */
512 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 //Mask BIT[31:24]
514 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 //Mask BIT[23:16]
517 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 //Mask BIT[25:24]
604 #define AR_PHY_AIC_MON_ENABLE 0x80000000
606 #define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000
608 #define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000
610 #define AR_PHY_AIC_F_WLAN 0x0001FC00
612 #define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200
614 #define AR_PHY_AIC_CAL_ENABLE 0x00000100
616 #define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE
618 #define AR_PHY_AIC_ENABLE 0x00000001
619 #define AR_PHY_AIC_ENABLE_S 0
620 #define AR_PHY_AIC_CAL_BT_REF_DELAY 0x78000000
622 #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x07000000
624 #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00F00000
626 #define AR_PHY_AIC_BT_IDLE_CFG 0x00080000
628 #define AR_PHY_AIC_STDBY_COND 0x00060000
630 #define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800
632 #define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700
634 #define AR_PHY_AIC_RSSI_MAX 0x000000F0
636 #define AR_PHY_AIC_RSSI_MIN 0x0000000F
637 #define AR_PHY_AIC_RSSI_MIN_S 0
638 #define AR_PHY_AIC_RADIO_DELAY 0x7F000000
640 #define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000
642 #define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000
644 #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000
646 #define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00
648 #define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200
650 #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100
652 #define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF
653 #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0
654 #define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x0FE00000
656 #define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x001FC000
658 #define AR_PHY_AIC_MON_PWR_EST_LONG 0x00002000
660 #define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00001800
662 #define AR_PHY_AIC_MON_PERF_THR 0x000007C0
664 #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000020
666 #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018
668 #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006
670 #define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001
671 #define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0
672 #define AR_PHY_AIC_MON_DONE 0x80000000
674 #define AR_PHY_AIC_MON_ACTIVE 0x40000000
676 #define AR_PHY_AIC_MEAS_COUNT 0x3F000000
678 #define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000
680 #define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800
682 #define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0
684 #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008
686 #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004
688 #define AR_PHY_AIC_CAL_DONE 0x00000002
690 #define AR_PHY_AIC_CAL_ACTIVE 0x00000001
691 #define AR_PHY_AIC_CAL_ACTIVE_S 0
692 #define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000
694 #define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000
696 #define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00
698 #define AR_PHY_AIC_CAL_AIC_SM 0x000000F8
700 #define AR_PHY_AIC_SM 0x00000007
701 #define AR_PHY_AIC_SM_S 0
702 #define AR_PHY_AIC_SRAM_VALID 0x00000001
703 #define AR_PHY_AIC_SRAM_VALID_S 0
704 #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E
706 #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080
708 #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00
710 #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000
712 #define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000
716 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0
719 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_I 0x07FF0000
721 #define AR_PHY_CL_TAB_CARR_LK_DC_ADD_Q 0x0000FFE0
723 #define AR_PHY_CL_TAB_GAIN_MOD 0x0000001F
724 #define AR_PHY_CL_TAB_GAIN_MOD_S 0
727 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
729 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
730 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
733 #define AR_PHY_ENABLE_FLT_SVD 0x00001000
738 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000
744 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000
748 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
749 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 /*cf_tstdac_en, driver to tstdac bus, 0=disable, 1=enab…
750 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
752 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
754 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100
755 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 /*cf_tstadc_en, driver to tstadc bus, 0=disable, 1=enab…
756 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
758 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000
783 #define AR_PHY_PWRTX_MAX_TPC_ENABLE 0x00000040
785 #define AR_PHY_PER_PACKET_POWERTX_MAX 0x00000040
787 #define AR_PHY_POWER_TX_SUB_2_DISABLE 0xFFFFFFC0 /* 2 chain */
788 #define AR_PHY_POWER_TX_SUB_3_DISABLE 0xFFFFF000 /* 3 chain */
850 #define AR_PHY_65NM_CH0_TXRF2_DB2G 0x07000000
852 #define AR_PHY_65NM_CH0_TXRF2_OB2G_CCK 0x00E00000
854 #define AR_PHY_65NM_CH0_TXRF2_OB2G_PSK 0x001C0000
856 #define AR_PHY_65NM_CH0_TXRF2_OB2G_QAM 0x00038000
859 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001E
861 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE 0x00000001
862 #define AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE_S 0
871 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
879 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
883 #define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
888 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL 0x00000300
893 #define AR_OSPREY_CHO_XTAL_CAPINDAC 0x7F000000
895 #define AR_OSPREY_CHO_XTAL_CAPOUTDAC 0x00FE0000
901 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB 0x00000003
902 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S 0
903 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND 0x00000004
905 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
907 #define AR_PHY_65NM_CH0_THERM_START 0x20000000
909 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
914 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
916 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
934 #define AR_PHY_CH_BB3_SEL_OFST_READBK 0x00000300
936 #define AR_PHY_CH_BB3_OFSTCORRI2VQ 0x03e00000
938 #define AR_PHY_CH_BB3_OFSTCORRI2VI 0x7c000000
941 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
943 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
945 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
947 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
949 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
951 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
952 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
953 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
955 #define AR_PHY_MANTXGAIN_LONG_SHIFT 0x80000000
963 #define AR_PHY_CL_CAL_ENABLE 0x00000002 /* do carrier leak calibration after agc_calibr…
964 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
965 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
967 #define AR_PHY_CL_MAP_HW_GEN 0x80000000
971 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
974 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
978 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
980 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
982 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
983 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
984 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
985 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
986 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz…
989 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
990 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
991 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
992 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX…
993 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
994 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, no…
995 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
997 #define AR_PHY_MS_HALF_RATE 0x00000020
998 #define AR_PHY_MS_QUARTER_RATE 0x00000040
1001 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
1003 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
1004 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
1005 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
1006 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen…
1007 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
1008 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
1009 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
1010 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
1011 #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 /* allow peak deteter calibration */
1013 #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
1017 #define AR_PHY_CALMODE_IQ 0x00000000
1018 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
1019 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
1020 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
1022 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
1024 #define AR_PHY_MODE_OFDM 0x00000000 /* OFDM */
1025 #define AR_PHY_MODE_CCK 0x00000001 /* CCK */
1026 #define AR_PHY_MODE_DYNAMIC 0x00000004 /* dynamic CCK/OFDM mode */
1028 #define AR_PHY_MODE_HALF 0x00000020 /* enable half rate */
1029 #define AR_PHY_MODE_QUARTER 0x00000040 /* enable quarter rate */
1030 #define AR_PHY_MAC_CLK_MODE 0x00000080 /* MAC runs at 128/141MHz clock */
1031 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 /* Disable dynamic CCK detection */
1032 #define AR_PHY_MODE_SVD_HALF 0x00000200 /* enable svd half rate */
1033 #define AR_PHY_MODE_DISABLE_CCK 0x00000100
1036 #define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */
1037 #define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */
1039 #define AR_PHY_FORCE_XPA_CFG 0x000000001
1040 #define AR_PHY_FORCE_XPA_CFG_S 0
1042 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
1044 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
1046 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
1048 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
1049 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
1051 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
1054 #define AR_PHY_TX_END_DATA_START 0x000000FF
1055 #define AR_PHY_TX_END_DATA_START_S 0
1056 #define AR_PHY_TX_END_PA_ON 0x0000FF00
1060 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
1061 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
1062 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
1064 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
1066 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
1068 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
1071 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
1073 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
1075 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
1077 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
1079 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
1081 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
1084 #define AR_PHY_TXGAIN_FORCE 0x00000001
1085 #define AR_PHY_TXGAIN_FORCE_S 0
1086 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
1088 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
1090 #define AR_PHY_TXGAIN_FORCED_PADVGNRC 0x003c0000
1092 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
1094 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
1096 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
1098 #define AR_PHY_TXGAIN_FORCED_TXBB6DBGAIN 0x00000030
1102 #define AR_PHY_POWER_TX_RATE1 0x9934
1103 #define AR_PHY_POWER_TX_RATE2 0x9938
1105 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
1107 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
1108 #define RFSILENT_BB 0x00002000 /* shush bb */
1110 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF /* PPM value is 12-bit signed integer…
1111 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 /* Sign bit */
1114 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
1116 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
1118 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
1120 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 /* Enable spectral scan */
1121 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
1122 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan */
1124 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports */
1126 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports */
1128 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000 /* Number of reports */
1130 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000 /* Short repeat */
1132 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_HI 0x20000000 /* high priority */
1135 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
1137 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
1138 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
1139 #define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
1141 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
1144 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0 0x00000001
1145 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_0_S 0
1146 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_0 0x00000002
1148 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_0 0x0000001C
1151 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_0 0xFFFFFFF0
1154 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
1157 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
1160 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
1161 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
1163 #define AR_PHY_TX_IQCAL_START_DO_CAL_POSEIDON 0x80000000
1168 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
1170 #define AR_PHY_CALIBRATED_GAINS_0 (0x1f<<AR_PHY_CALIBRATED_GAINS_0_S)
1172 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
1173 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
1175 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE (0x00003fff<<AR_PHY_TX_IQCAL_CORR_COEFF_01_C…
1179 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff //Mask bits 7:0
1180 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
1182 #define AR_PHY_TPC_19_ALPHA_THERM 0xff //Mask bits 7:0
1183 #define AR_PHY_TPC_19_ALPHA_THERM_S 0
1186 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
1190 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
1191 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
1194 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM 0x000000ff
1195 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S 0
1198 #define AR_PHY_SWITCH_TABLE_R0 0x00000010
1200 #define AR_PHY_SWITCH_TABLE_R1 0x00000040
1202 #define AR_PHY_SWITCH_TABLE_R12 0x00000100
1230 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
1265 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
1305 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1 0x00000001
1306 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_1_S 0
1307 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_1 0x00000002
1309 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_1 0x0000001C
1312 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_1 0xFFFFFFF0
1348 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
1368 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
1403 #define AR_PHY_PAPRD_VALID_OBDB_0 0x3f
1404 #define AR_PHY_PAPRD_VALID_OBDB_0_S 0
1405 #define AR_PHY_PAPRD_VALID_OBDB_1 0x3f
1407 #define AR_PHY_PAPRD_VALID_OBDB_2 0x3f
1409 #define AR_PHY_PAPRD_VALID_OBDB_3 0x3f
1411 #define AR_PHY_PAPRD_VALID_OBDB_4 0x3f
1415 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
1443 #define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */
1444 #define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
1445 #define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
1446 #define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */
1449 #define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
1450 #define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
1451 #define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
1452 #define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
1454 #define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
1455 #define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
1456 #define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
1458 #define AR_PHY_BB_WD_STATUS 0x00000007 /* snapshot of r_panic_watchdog_sm */
1459 #define AR_PHY_BB_WD_STATUS_S 0
1460 #define AR_PHY_BB_WD_DET_HANG 0x00000008 /* panic_watchdog_det_hang */
1462 #define AR_PHY_BB_WD_RADAR_SM 0x000000F0 /* snapshot of radar state machine r_rdr_sm */
1464 #define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00 /* snapshot of rx state machine (OFDM) r_rx_sm */
1466 #define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000 /* snapshot of rx state machine (CCK) r_rx_sm_cc…
1468 #define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000 /* snapshot of tx state machine (OFDM) r_tx_sm */
1470 #define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000 /* snapshot of tx state machine (CCK) r_tx_sm_cc…
1472 #define AR_PHY_BB_WD_AGC_SM 0x0F000000 /* snapshot of AGC state machine r_agc_sm */
1474 #define AR_PHY_BB_WD_SRCH_SM 0xF0000000 /* snapshot of agc search state machine r_srch_s…
1477 #define AR_PHY_BB_WD_STATUS_CLR 0x00000008 /* write 0 to reset watchdog */
1482 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
1483 #define AR_PHY_PAPRD_AM2AM_MASK_S 0
1486 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
1487 #define AR_PHY_PAPRD_AM2PM_MASK_S 0
1490 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
1491 #define AR_PHY_PAPRD_HT40_MASK_S 0
1495 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_ENABLE_0_S 0
1496 #define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK 0x00000001
1497 #define AR_PHY_PAPRD_CTRL0_B0_USE_SINGLE_TABLE_MASK_S 0x00000001
1498 #define AR_PHY_PAPRD_CTRL0_B0_PAPRD_MAG_THRSH_0 0x1F
1502 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0 0x3f
1509 #define AR_PHY_PAPRD_CTRL1_B0_ADAPTIVE_SCALING_ENA_S 0
1510 #define AR_PHY_PAPRD_CTRL1_B0_PA_GAIN_SCALE_FACT_0_MASK 0xFF
1512 #define AR_PHY_PAPRD_CTRL1_B0_PAPRD_MAG_SCALE_FACT_0 0x7FF
1516 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_MAG_THRSH_1 0x1F
1521 #define AR_PHY_PAPRD_CTRL0_B1_PAPRD_ENABLE_1_S 0
1524 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_POWER_AT_AM2AM_CAL_1 0x3f
1531 #define AR_PHY_PAPRD_CTRL1_B1_ADAPTIVE_SCALING_ENA_S 0
1532 #define AR_PHY_PAPRD_CTRL1_B1_PA_GAIN_SCALE_FACT_1_MASK 0xFF
1534 #define AR_PHY_PAPRD_CTRL1_B1_PAPRD_MAG_SCALE_FACT_1 0x7FF
1538 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_MAG_THRSH_2 0x1F
1543 #define AR_PHY_PAPRD_CTRL0_B2_PAPRD_ENABLE_2_S 0
1547 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_POWER_AT_AM2AM_CAL_2 0x3f
1554 #define AR_PHY_PAPRD_CTRL1_B2_ADAPTIVE_SCALING_ENA_S 0
1555 #define AR_PHY_PAPRD_CTRL1_B2_PA_GAIN_SCALE_FACT_2_MASK 0xFF
1557 #define AR_PHY_PAPRD_CTRL1_B2_PAPRD_MAG_SCALE_FACT_2 0x7FF
1562 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x3f
1572 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x3F
1575 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
1579 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
1580 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
1586 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0xF
1588 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF
1590 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0xF
1592 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x7
1594 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x1F
1596 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x3F
1598 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x3F
1599 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
1603 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x3FF
1605 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0xF
1607 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0xFFF
1608 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
1611 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0 0x3FFFF
1612 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0_PAPRD_PRE_POST_SCALING_0_0_S 0
1615 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0 0x3FFFF
1616 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0_PAPRD_PRE_POST_SCALING_1_0_S 0
1619 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0 0x3FFFF
1620 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0_PAPRD_PRE_POST_SCALING_2_0_S 0
1623 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0 0x3FFFF
1624 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0_PAPRD_PRE_POST_SCALING_3_0_S 0
1627 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0 0x3FFFF
1628 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0_PAPRD_PRE_POST_SCALING_4_0_S 0
1631 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0 0x3FFFF
1632 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0_PAPRD_PRE_POST_SCALING_5_0_S 0
1635 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0 0x3FFFF
1636 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0_PAPRD_PRE_POST_SCALING_6_0_S 0
1639 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0 0x3FFFF
1640 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0_PAPRD_PRE_POST_SCALING_7_0_S 0
1644 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0xff
1646 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x1f
1648 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x1
1650 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x1
1652 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x1
1655 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
1659 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x3
1661 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x1F
1663 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0xffff
1664 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
1668 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0xfffff
1669 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
1672 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x1F
1675 #define AR_PHY_TPC_19_ALT_ALPHA_VOLT 0x1f
1678 #define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE 0xff
1679 #define AR_PHY_TPC_18_ALT_THERM_CAL_VALUE_S 0
1681 #define AR_PHY_TPC_18_ALT_VOLT_CAL_VALUE 0xff
1685 #define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE 0xFF
1686 #define AR_PHY_THERM_ADC_4_LATEST_THERM_VALUE_S 0
1687 #define AR_PHY_THERM_ADC_4_LATEST_VOLT_VALUE 0xFF
1692 #define AR_PHY_TPC_11_B0_OLPC_GAIN_DELTA_0 0xFF
1696 #define AR_PHY_TPC_11_B1_OLPC_GAIN_DELTA_1 0xFF
1700 #define AR_PHY_TPC_11_B2_OLPC_GAIN_DELTA_2 0xFF
1704 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x7
1706 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x3
1708 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0xf
1710 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0xf
1712 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0xf
1714 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0xf
1716 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x3
1721 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
1724 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x1f
1727 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
1737 #define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0 0x3FF
1738 #define AR_PHY_PA_GAIN123_B0_PA_GAIN1_0_S 0
1741 #define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1 0x3FF
1742 #define AR_PHY_PA_GAIN123_B1_PA_GAIN1_1_S 0
1745 #define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2 0x3FF
1746 #define AR_PHY_PA_GAIN123_B2_PA_GAIN1_2_S 0
1750 #define AR_PHY_POWERTX_RATE2_POWERTX54M_7 0x3F
1754 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1755 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1757 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_3 0x3F
1762 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F
1765 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_4 0x3F
1766 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_4_S 0
1770 #define AR_PHY_POWERTX_RATE7_POWERTXHT40_3 0x3F
1775 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F
1778 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_4 0x3F
1779 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_4_S 0
1783 #define AR_PHY_POWERTX_RATE10_POWERTXHT20_9 0x3F
1788 #define AR_PHY_POWERTX_RATE11_POWERTXHT20_13 0x3F
1791 #define AR_PHY_CL_TAB_0_CL_GAIN_MOD 0x1F
1792 #define AR_PHY_CL_TAB_0_CL_GAIN_MOD_S 0
1794 #define AR_PHY_CL_TAB_1_CL_GAIN_MOD 0x1F
1795 #define AR_PHY_CL_TAB_1_CL_GAIN_MOD_S 0
1797 #define AR_PHY_CL_TAB_2_CL_GAIN_MOD 0x1F
1798 #define AR_PHY_CL_TAB_2_CL_GAIN_MOD_S 0
1805 #define AR_HORNET_CH0_TOP2_XPABIASLVL 0xf000
1809 #define AR_SCORPION_CH0_TOP_XPABIASLVL 0x3c0
1817 #define AR_HORNET_CHO_XTAL_CAPINDAC 0x7F000000
1819 #define AR_HORNET_CHO_XTAL_CAPOUTDAC 0x00FE0000
1827 #define AR_PHY_BB_DPLL1_REFDIV 0xF8000000
1829 #define AR_PHY_BB_DPLL1_NINI 0x07FC0000
1831 #define AR_PHY_BB_DPLL1_NFRAC 0x0003FFFF
1832 #define AR_PHY_BB_DPLL1_NFRAC_S 0
1835 #define AR_PHY_BB_DPLL2_RANGE 0x80000000
1837 #define AR_PHY_BB_DPLL2_LOCAL_PLL 0x40000000
1839 #define AR_PHY_BB_DPLL2_KI 0x3C000000
1841 #define AR_PHY_BB_DPLL2_KD 0x03F80000
1843 #define AR_PHY_BB_DPLL2_EN_NEGTRIG 0x00040000
1845 #define AR_PHY_BB_DPLL2_SEL_1SDM 0x00020000
1847 #define AR_PHY_BB_DPLL2_PLL_PWD 0x00010000
1849 #define AR_PHY_BB_DPLL2_OUTDIV 0x0000E000
1851 #define AR_PHY_BB_DPLL2_DELTA 0x00001F80
1853 #define AR_PHY_BB_DPLL2_SPARE 0x0000007F
1854 #define AR_PHY_BB_DPLL2_SPARE_S 0
1857 #define AR_PHY_BB_DPLL3_MEAS_AT_TXON 0x80000000
1859 #define AR_PHY_BB_DPLL3_DO_MEAS 0x40000000
1861 #define AR_PHY_BB_DPLL3_PHASE_SHIFT 0x3F800000
1863 #define AR_PHY_BB_DPLL3_SQSUM_DVC 0x007FFFF8
1865 #define AR_PHY_BB_DPLL3_SPARE 0x00000007
1866 #define AR_PHY_BB_DPLL3_SPARE_S 0x0
1869 #define AR_PHY_BB_DPLL4_MEAN_DVC 0xFFE00000
1871 #define AR_PHY_BB_DPLL4_VC_MEAS0 0x001FFFF0
1873 #define AR_PHY_BB_DPLL4_MEAS_DONE 0x00000008
1875 #define AR_PHY_BB_DPLL4_SPARE 0x00000007
1876 #define AR_PHY_BB_DPLL4_SPARE_S 0
1889 #define AR_PHY_USB_CTRL1 0x16c84
1890 #define AR_PHY_USB_CTRL2 0x16c88
1912 #define AR_PHY_PMU1_PWD 0x00000001 /* power down switch regulator */
1913 #define AR_PHY_PMU1_PWD_S 0
1916 #define AR_PHY_PMU2_PGM 0x00200000
1920 #define AR_PHY_CTRL2_TX_MAN_CAL 0x03C00000
1922 #define AR_PHY_CTRL2_TX_CAL_SEL 0x00200000
1924 #define AR_PHY_CTRL2_TX_CAL_EN 0x00100000
1927 #define PCIE_CO_ERR_CTR_CTRL 0x40e8
1928 #define PCIE_CO_ERR_CTR_CTR0 0x40e0
1929 #define PCIE_CO_ERR_CTR_CTR1 0x40e4
1932 #define RCVD_ERR_CTR_RUN 0x0001
1933 #define RCVD_ERR_CTR_AUTO_STOP 0x0002
1934 #define BAD_TLP_ERR_CTR_RUN 0x0004
1935 #define BAD_TLP_ERR_CTR_AUTO_STOP 0x0008
1936 #define BAD_DLLP_ERR_CTR_RUN 0x0010
1937 #define BAD_DLLP_ERR_CTR_AUTO_STOP 0x0020
1938 #define RPLY_TO_ERR_CTR_RUN 0x0040
1939 #define RPLY_TO_ERR_CTR_AUTO_STOP 0x0080
1940 #define RPLY_NUM_RO_ERR_CTR_RUN 0x0100
1941 #define RPLY_NUM_RO_ERR_CTR_AUTO_STOP 0x0200
1943 #define RCVD_ERR_MASK 0x000000ff
1944 #define RCVD_ERR_MASK_S 0
1945 #define BAD_TLP_ERR_MASK 0x0000ff00
1947 #define BAD_DLLP_ERR_MASK 0x00ff0000
1950 #define RPLY_TO_ERR_MASK 0x000000ff
1951 #define RPLY_TO_ERR_MASK_S 0
1952 #define RPLY_NUM_RO_ERR_MASK 0x0000ff00