Lines Matching +full:0 +full:x0003ffff

30 #define	AWIN_DMA_IRQ_EN_REG		0x0000
31 #define	AWIN_DMA_IRQ_PEND_STA_REG	0x0004
32 #define	AWIN_NDMA_AUTO_GATE_REG		0x0008
33 #define	AWIN_NDMA_REG(n)		(0x100+0x20*(n))
34 #define	AWIN_NDMA_CTL_REG		0x0000
35 #define	AWIN_NDMA_SRC_ADDR_REG		0x0004
36 #define	AWIN_NDMA_DEST_ADDR_REG		0x0008
37 #define	AWIN_NDMA_BC_REG		0x000c
38 #define	AWIN_DDMA_REG(n)		(0x300+0x20*(n))
39 #define	AWIN_DDMA_CTL_REG		0x0000
40 #define	AWIN_DDMA_SRC_START_ADDR_REG	0x0004
41 #define	AWIN_DDMA_DEST_START_ADDR_REG	0x0008
42 #define	AWIN_DDMA_BC_REG		0x000c
43 #define	AWIN_DDMA_PARA_REG		0x0018
44 #define	AWIN_DMA_IRQ_END_MASK		0xaaaaaaaa
45 #define	AWIN_DMA_IRQ_HF_MASK		0x55555555
46 #define	AWIN_DMA_IRQ_DDMA		0xffff0000
49 #define	AWIN_DMA_IRQ_NDMA		0x0000ffff
51 #define	AWIN_DMA_IRQ_NDMA_HF(n)		(1U << (0+2*(n)))
55 #define	AWIN_DMA_CTL_DATA_WIDTH_8	0
60 #define	AWIN_DMA_CTL_BURST_LEN_1	0
64 #define	AWIN_DMA_CTL_DST_DRQ_TYPE_MASK	(0x1f << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT)
70 #define	AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT	0
71 #define	AWIN_DMA_CTL_SRC_DRQ_TYPE_MASK	(0x1f << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT)
78 #define	AWIN_NDMA_CTL_DRQ_IRO		0
109 #define	AWIN_NDMA_BC_COUNT		0x0003ffff
116 #define	AWIN_DDMA_CTL_DMA_ADDR_LINEAR	0
121 #define	AWIN_DDMA_CTL_DST_DRQ_TYPE_MASK	(0x1f << AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT)
122 #define	AWIN_DDMA_CTL_DRQ_SRAM		0
146 #define	AWIN_DDMA_BC_COUNT		0x00003fff
148 #define	AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT)
150 #define	AWIN_DDMA_PARA_DST_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT)
152 #define	AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT)
153 #define	AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT 0
154 #define	AWIN_DDMA_PARA_SRC_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT)