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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_11_0_cdr_table.h36 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0…
37 0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x0…
38 0x0f0f0f0f, 0xf0f00f0f, 0x0f0ff0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf…
39 0xf0f00f0f, 0x0f0ff0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0…
46 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0xf…
47 0xffffffff, 0x0000ffff, 0x00000000, 0xffffffff, 0x00000000, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xf…
48 0xffffffff, 0x0000ffff, 0xffff0000, 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x0000ffff, 0x0…
49 0x0000ffff, 0xffff0000, 0xffff0000, 0x00000000, 0xffff0000, 0x00000000, 0xffffffff, 0x00000000, 0xf…
56 …0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x…
57 …0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x…
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsi_dpm.c40 #define MC_CG_ARB_FREQ_F0 0x0a
41 #define MC_CG_ARB_FREQ_F1 0x0b
42 #define MC_CG_ARB_FREQ_F2 0x0c
43 #define MC_CG_ARB_FREQ_F3 0x0d
45 #define SMC_RAM_END 0x20000
50 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
51 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
53 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
54 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
[all …]
/linux/drivers/scsi/lpfc/
H A Dlpfc_hw4.h36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
79 #define lpfc_sli_intf_valid_MASK 0x00000007
83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
93 #define lpfc_sli_intf_if_type_MASK 0x0000000F
[all …]
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c43 #define MC_CG_ARB_FREQ_F0 0x0a
44 #define MC_CG_ARB_FREQ_F1 0x0b
45 #define MC_CG_ARB_FREQ_F2 0x0c
46 #define MC_CG_ARB_FREQ_F3 0x0d
48 #define SMC_RAM_END 0x20000
61 #define BIOS_SCRATCH_4 0x5cd
107 SI_DPM_EVENT_SRC_ANALOG = 0,
154 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
155 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
156 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_diag.c8 { IGC_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9 { IGC_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
10 { IGC_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
11 { IGC_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
12 { IGC_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
13 { IGC_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
14 { IGC_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
15 { IGC_FCRTH, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
16 { IGC_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
17 { IGC_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
[all …]
/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.h20 } while (0)
22 __CSKY_INSN_FUNCS(br16, 0xfc00, 0x0400)
23 __CSKY_INSN_FUNCS(bt16, 0xfc00, 0x0800)
24 __CSKY_INSN_FUNCS(bf16, 0xfc00, 0x0c00)
25 __CSKY_INSN_FUNCS(jmp16, 0xffc3, 0x7800)
26 __CSKY_INSN_FUNCS(jsr16, 0xffc3, 0x7801)
27 __CSKY_INSN_FUNCS(lrw16, 0xfc00, 0x1000)
28 __CSKY_INSN_FUNCS(pop16, 0xffe0, 0x1480)
30 __CSKY_INSN_FUNCS(br32, 0x0000ffff, 0x0000e800)
31 __CSKY_INSN_FUNCS(bt32, 0x0000ffff, 0x0000e860)
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/drivers/staging/rtl8712/
H A Dusb_ops.c33 __le32 data = 0; in usb_read8()
36 request = 0x05; in usb_read8()
37 requesttype = 0x01; /* read_in */ in usb_read8()
38 index = 0; in usb_read8()
39 wvalue = (u16)(addr & 0x0000ffff); in usb_read8()
43 if (status < 0) in usb_read8()
44 return 0; in usb_read8()
45 return (u8)(le32_to_cpu(data) & 0x0ff); in usb_read8()
56 __le32 data = 0; in usb_read16()
59 request = 0x05; in usb_read16()
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dnv04.c33 nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000000); in nv04_head_vblank_put()
40 nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000001); in nv04_head_vblank_get()
47 u32 data = nvkm_rd32(device, 0x600868 + (head->id * 0x2000)); in nv04_head_rgpos()
48 *hline = (data & 0xffff0000) >> 16; in nv04_head_rgpos()
49 *vline = (data & 0x0000ffff); in nv04_head_rgpos()
56 const u32 hoff = head->id * 0x0200; in nv04_head_state()
57 state->vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0x0000ffff; in nv04_head_state()
58 state->vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0x0000ffff; in nv04_head_state()
60 state->hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0x0000ffff; in nv04_head_state()
61 state->htotal = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff; in nv04_head_state()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
H A Dmdp_reg_wrot.h10 #define VIDO_CTRL 0x000
11 #define VIDO_MAIN_BUF_SIZE 0x008
12 #define VIDO_SOFT_RST 0x010
13 #define VIDO_SOFT_RST_STAT 0x014
14 #define VIDO_CROP_OFST 0x020
15 #define VIDO_TAR_SIZE 0x024
16 #define VIDO_OFST_ADDR 0x02c
17 #define VIDO_STRIDE 0x030
18 #define VIDO_OFST_ADDR_C 0x038
19 #define VIDO_STRIDE_C 0x03c
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c112 TEST_REG = 0,
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in igb_get_link_ksettings()
257 return 0; in igb_get_link_ksettings()
338 /* fix up the value for auto (3 => 0) as zero is mapped in igb_set_link_ksettings()
355 return 0; in igb_set_link_ksettings()
399 int retval = 0; in igb_set_pauseparam()
435 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_pauseparam()
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); in igb_get_regs()
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxgpt.h20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
29 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_mfw_hsi.h9 #define MFW_TRACE_SIGNATURE 0x25071946
12 #define MFW_TRACE_EVENTID_MASK 0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
22 * 0 - just errors will be written to the buffer
24 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
53 #define OFFSIZE_OFFSET_SHIFT 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
57 #define OFFSIZE_SIZE_MASK 0xffff0000
77 #define ETH_SPEED_AUTONEG 0x0
78 #define ETH_SPEED_SMARTLINQ 0x8
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
[all …]
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/linux/sound/pci/
H A Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dhal.h43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
57 #define HAL_WLAON_REG_BASE 0x01f80000
60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
[all …]
/linux/drivers/mtd/lpddr/
H A Dlpddr2_nvm.c28 #define ERASE_BLOCKSIZE (0x00020000/2) /* in Word */
29 #define WRITE_BUFFSIZE (0x00000400/2) /* in Word */
30 #define OW_BASE_ADDRESS 0x00000000 /* OW offset */
31 #define BUS_WIDTH 0x00000020 /* x32 devices */
34 #define PFOW_QUERY_STRING_P (0x0000/2) /* in Word */
35 #define PFOW_QUERY_STRING_F (0x0002/2) /* in Word */
36 #define PFOW_QUERY_STRING_O (0x0004/2) /* in Word */
37 #define PFOW_QUERY_STRING_W (0x0006/2) /* in Word */
40 #define CMD_CODE_OFS (0x0080/2) /* in Word */
41 #define CMD_DATA_OFS (0x0084/2) /* in Word */
[all …]
/linux/arch/mips/include/asm/mach-rc32434/
H A Deth.h33 #define ETH0_BASE_ADDR 0x18060000
84 #define ETH_INT_FC_EN (1 << 0)
90 #define ETH_INT_FC_IOC 0x000000c0
93 #define ETH_FIFI_TT_TTH_BIT 0
94 #define ETH_FIFO_TT_TTH 0x0000007f
97 #define ETH_ARC_PRO (1 << 0)
103 #define ETH_SAL_BYTE_5 0x000000ff
104 #define ETH_SAL_BYTE_4 0x0000ff00
105 #define ETH_SAL_BYTE_3 0x00ff0000
106 #define ETH_SAL_BYTE_2 0xff000000
[all …]

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