33 	nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000000);  in nv04_head_vblank_put()
40 	nvkm_wr32(device, 0x600140 + (head->id * 0x2000) , 0x00000001);  in nv04_head_vblank_get()
47 	u32 data = nvkm_rd32(device, 0x600868 + (head->id * 0x2000));  in nv04_head_rgpos()
48 	*hline = (data & 0xffff0000) >> 16;  in nv04_head_rgpos()
49 	*vline = (data & 0x0000ffff);  in nv04_head_rgpos()
56 	const u32 hoff = head->id * 0x0200;  in nv04_head_state()
57 	state->vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0x0000ffff;  in nv04_head_state()
58 	state->vtotal  = nvkm_rd32(device, 0x680804 + hoff) & 0x0000ffff;  in nv04_head_state()
60 	state->hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0x0000ffff;  in nv04_head_state()
61 	state->htotal  = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff;  in nv04_head_state()
84 	u32 crtc0 = nvkm_rd32(device, 0x600100);  in nv04_disp_intr()
85 	u32 crtc1 = nvkm_rd32(device, 0x602100);  in nv04_disp_intr()
88 	if (crtc0 & 0x00000001) {  in nv04_disp_intr()
89 		nvkm_disp_vblank(disp, 0);  in nv04_disp_intr()
90 		nvkm_wr32(device, 0x600100, 0x00000001);  in nv04_disp_intr()
93 	if (crtc1 & 0x00000001) {  in nv04_disp_intr()
95 		nvkm_wr32(device, 0x602100, 0x00000001);  in nv04_disp_intr()
98 	if (device->chipset >= 0x10 && device->chipset <= 0x40) {  in nv04_disp_intr()
99 		pvideo = nvkm_rd32(device, 0x8100);  in nv04_disp_intr()
100 		if (pvideo & ~0x11)  in nv04_disp_intr()
102 		nvkm_wr32(device, 0x8100, pvideo);  in nv04_disp_intr()
109 	.root = { 0, 0, NV04_DISP },
123 	for (i = 0; i < 2; i++) {  in nv04_disp_new()
129 	return 0;  in nv04_disp_new()