1*f026d8caSVitaly Lifshits // SPDX-License-Identifier: GPL-2.0
2*f026d8caSVitaly Lifshits /* Copyright (c) 2020 Intel Corporation */
3*f026d8caSVitaly Lifshits
4*f026d8caSVitaly Lifshits #include "igc.h"
5*f026d8caSVitaly Lifshits #include "igc_diag.h"
6*f026d8caSVitaly Lifshits
7*f026d8caSVitaly Lifshits static struct igc_reg_test reg_test[] = {
8*f026d8caSVitaly Lifshits { IGC_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9*f026d8caSVitaly Lifshits { IGC_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
10*f026d8caSVitaly Lifshits { IGC_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
11*f026d8caSVitaly Lifshits { IGC_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
12*f026d8caSVitaly Lifshits { IGC_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
13*f026d8caSVitaly Lifshits { IGC_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
14*f026d8caSVitaly Lifshits { IGC_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
15*f026d8caSVitaly Lifshits { IGC_FCRTH, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
16*f026d8caSVitaly Lifshits { IGC_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
17*f026d8caSVitaly Lifshits { IGC_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
18*f026d8caSVitaly Lifshits { IGC_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
19*f026d8caSVitaly Lifshits { IGC_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
20*f026d8caSVitaly Lifshits { IGC_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
21*f026d8caSVitaly Lifshits { IGC_TDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
22*f026d8caSVitaly Lifshits { IGC_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
23*f026d8caSVitaly Lifshits { IGC_RCTL, 1, SET_READ_TEST, 0x04CFB2FE, 0x003FFFFB },
24*f026d8caSVitaly Lifshits { IGC_RCTL, 1, SET_READ_TEST, 0x04CFB2FE, 0xFFFFFFFF },
25*f026d8caSVitaly Lifshits { IGC_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
26*f026d8caSVitaly Lifshits { IGC_RA, 16, TABLE64_TEST_LO,
27*f026d8caSVitaly Lifshits 0xFFFFFFFF, 0xFFFFFFFF },
28*f026d8caSVitaly Lifshits { IGC_RA, 16, TABLE64_TEST_HI,
29*f026d8caSVitaly Lifshits 0x900FFFFF, 0xFFFFFFFF },
30*f026d8caSVitaly Lifshits { IGC_MTA, 128, TABLE32_TEST,
31*f026d8caSVitaly Lifshits 0xFFFFFFFF, 0xFFFFFFFF },
32*f026d8caSVitaly Lifshits { 0, 0, 0, 0}
33*f026d8caSVitaly Lifshits };
34*f026d8caSVitaly Lifshits
reg_pattern_test(struct igc_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)35*f026d8caSVitaly Lifshits static bool reg_pattern_test(struct igc_adapter *adapter, u64 *data, int reg,
36*f026d8caSVitaly Lifshits u32 mask, u32 write)
37*f026d8caSVitaly Lifshits {
38*f026d8caSVitaly Lifshits struct igc_hw *hw = &adapter->hw;
39*f026d8caSVitaly Lifshits u32 pat, val, before;
40*f026d8caSVitaly Lifshits static const u32 test_pattern[] = {
41*f026d8caSVitaly Lifshits 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
42*f026d8caSVitaly Lifshits };
43*f026d8caSVitaly Lifshits
44*f026d8caSVitaly Lifshits for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
45*f026d8caSVitaly Lifshits before = rd32(reg);
46*f026d8caSVitaly Lifshits wr32(reg, test_pattern[pat] & write);
47*f026d8caSVitaly Lifshits val = rd32(reg);
48*f026d8caSVitaly Lifshits if (val != (test_pattern[pat] & write & mask)) {
49*f026d8caSVitaly Lifshits netdev_err(adapter->netdev,
50*f026d8caSVitaly Lifshits "pattern test reg %04X failed: got 0x%08X expected 0x%08X",
51*f026d8caSVitaly Lifshits reg, val, test_pattern[pat] & write & mask);
52*f026d8caSVitaly Lifshits *data = reg;
53*f026d8caSVitaly Lifshits wr32(reg, before);
54*f026d8caSVitaly Lifshits return false;
55*f026d8caSVitaly Lifshits }
56*f026d8caSVitaly Lifshits wr32(reg, before);
57*f026d8caSVitaly Lifshits }
58*f026d8caSVitaly Lifshits return true;
59*f026d8caSVitaly Lifshits }
60*f026d8caSVitaly Lifshits
reg_set_and_check(struct igc_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)61*f026d8caSVitaly Lifshits static bool reg_set_and_check(struct igc_adapter *adapter, u64 *data, int reg,
62*f026d8caSVitaly Lifshits u32 mask, u32 write)
63*f026d8caSVitaly Lifshits {
64*f026d8caSVitaly Lifshits struct igc_hw *hw = &adapter->hw;
65*f026d8caSVitaly Lifshits u32 val, before;
66*f026d8caSVitaly Lifshits
67*f026d8caSVitaly Lifshits before = rd32(reg);
68*f026d8caSVitaly Lifshits wr32(reg, write & mask);
69*f026d8caSVitaly Lifshits val = rd32(reg);
70*f026d8caSVitaly Lifshits if ((write & mask) != (val & mask)) {
71*f026d8caSVitaly Lifshits netdev_err(adapter->netdev,
72*f026d8caSVitaly Lifshits "set/check reg %04X test failed: got 0x%08X expected 0x%08X",
73*f026d8caSVitaly Lifshits reg, (val & mask), (write & mask));
74*f026d8caSVitaly Lifshits *data = reg;
75*f026d8caSVitaly Lifshits wr32(reg, before);
76*f026d8caSVitaly Lifshits return false;
77*f026d8caSVitaly Lifshits }
78*f026d8caSVitaly Lifshits wr32(reg, before);
79*f026d8caSVitaly Lifshits return true;
80*f026d8caSVitaly Lifshits }
81*f026d8caSVitaly Lifshits
igc_reg_test(struct igc_adapter * adapter,u64 * data)82*f026d8caSVitaly Lifshits bool igc_reg_test(struct igc_adapter *adapter, u64 *data)
83*f026d8caSVitaly Lifshits {
84*f026d8caSVitaly Lifshits struct igc_reg_test *test = reg_test;
85*f026d8caSVitaly Lifshits struct igc_hw *hw = &adapter->hw;
86*f026d8caSVitaly Lifshits u32 value, before, after;
87*f026d8caSVitaly Lifshits u32 i, toggle, b = false;
88*f026d8caSVitaly Lifshits
89*f026d8caSVitaly Lifshits /* Because the status register is such a special case,
90*f026d8caSVitaly Lifshits * we handle it separately from the rest of the register
91*f026d8caSVitaly Lifshits * tests. Some bits are read-only, some toggle, and some
92*f026d8caSVitaly Lifshits * are writeable.
93*f026d8caSVitaly Lifshits */
94*f026d8caSVitaly Lifshits toggle = 0x6800D3;
95*f026d8caSVitaly Lifshits before = rd32(IGC_STATUS);
96*f026d8caSVitaly Lifshits value = before & toggle;
97*f026d8caSVitaly Lifshits wr32(IGC_STATUS, toggle);
98*f026d8caSVitaly Lifshits after = rd32(IGC_STATUS) & toggle;
99*f026d8caSVitaly Lifshits if (value != after) {
100*f026d8caSVitaly Lifshits netdev_err(adapter->netdev,
101*f026d8caSVitaly Lifshits "failed STATUS register test got: 0x%08X expected: 0x%08X",
102*f026d8caSVitaly Lifshits after, value);
103*f026d8caSVitaly Lifshits *data = 1;
104*f026d8caSVitaly Lifshits return false;
105*f026d8caSVitaly Lifshits }
106*f026d8caSVitaly Lifshits /* restore previous status */
107*f026d8caSVitaly Lifshits wr32(IGC_STATUS, before);
108*f026d8caSVitaly Lifshits
109*f026d8caSVitaly Lifshits /* Perform the remainder of the register test, looping through
110*f026d8caSVitaly Lifshits * the test table until we either fail or reach the null entry.
111*f026d8caSVitaly Lifshits */
112*f026d8caSVitaly Lifshits while (test->reg) {
113*f026d8caSVitaly Lifshits for (i = 0; i < test->array_len; i++) {
114*f026d8caSVitaly Lifshits switch (test->test_type) {
115*f026d8caSVitaly Lifshits case PATTERN_TEST:
116*f026d8caSVitaly Lifshits b = reg_pattern_test(adapter, data,
117*f026d8caSVitaly Lifshits test->reg + (i * 0x40),
118*f026d8caSVitaly Lifshits test->mask,
119*f026d8caSVitaly Lifshits test->write);
120*f026d8caSVitaly Lifshits break;
121*f026d8caSVitaly Lifshits case SET_READ_TEST:
122*f026d8caSVitaly Lifshits b = reg_set_and_check(adapter, data,
123*f026d8caSVitaly Lifshits test->reg + (i * 0x40),
124*f026d8caSVitaly Lifshits test->mask,
125*f026d8caSVitaly Lifshits test->write);
126*f026d8caSVitaly Lifshits break;
127*f026d8caSVitaly Lifshits case TABLE64_TEST_LO:
128*f026d8caSVitaly Lifshits b = reg_pattern_test(adapter, data,
129*f026d8caSVitaly Lifshits test->reg + (i * 8),
130*f026d8caSVitaly Lifshits test->mask,
131*f026d8caSVitaly Lifshits test->write);
132*f026d8caSVitaly Lifshits break;
133*f026d8caSVitaly Lifshits case TABLE64_TEST_HI:
134*f026d8caSVitaly Lifshits b = reg_pattern_test(adapter, data,
135*f026d8caSVitaly Lifshits test->reg + 4 + (i * 8),
136*f026d8caSVitaly Lifshits test->mask,
137*f026d8caSVitaly Lifshits test->write);
138*f026d8caSVitaly Lifshits break;
139*f026d8caSVitaly Lifshits case TABLE32_TEST:
140*f026d8caSVitaly Lifshits b = reg_pattern_test(adapter, data,
141*f026d8caSVitaly Lifshits test->reg + (i * 4),
142*f026d8caSVitaly Lifshits test->mask,
143*f026d8caSVitaly Lifshits test->write);
144*f026d8caSVitaly Lifshits break;
145*f026d8caSVitaly Lifshits }
146*f026d8caSVitaly Lifshits if (!b)
147*f026d8caSVitaly Lifshits return false;
148*f026d8caSVitaly Lifshits }
149*f026d8caSVitaly Lifshits test++;
150*f026d8caSVitaly Lifshits }
151*f026d8caSVitaly Lifshits *data = 0;
152*f026d8caSVitaly Lifshits return true;
153*f026d8caSVitaly Lifshits }
154*f026d8caSVitaly Lifshits
igc_eeprom_test(struct igc_adapter * adapter,u64 * data)155*f026d8caSVitaly Lifshits bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data)
156*f026d8caSVitaly Lifshits {
157*f026d8caSVitaly Lifshits struct igc_hw *hw = &adapter->hw;
158*f026d8caSVitaly Lifshits
159*f026d8caSVitaly Lifshits *data = 0;
160*f026d8caSVitaly Lifshits
161*f026d8caSVitaly Lifshits if (hw->nvm.ops.validate(hw) != IGC_SUCCESS) {
162*f026d8caSVitaly Lifshits *data = 1;
163*f026d8caSVitaly Lifshits return false;
164*f026d8caSVitaly Lifshits }
165*f026d8caSVitaly Lifshits
166*f026d8caSVitaly Lifshits return true;
167*f026d8caSVitaly Lifshits }
168*f026d8caSVitaly Lifshits
igc_link_test(struct igc_adapter * adapter,u64 * data)169*f026d8caSVitaly Lifshits bool igc_link_test(struct igc_adapter *adapter, u64 *data)
170*f026d8caSVitaly Lifshits {
171*f026d8caSVitaly Lifshits bool link_up;
172*f026d8caSVitaly Lifshits
173*f026d8caSVitaly Lifshits *data = 0;
174*f026d8caSVitaly Lifshits
175*f026d8caSVitaly Lifshits /* add delay to give enough time for autonegotioation to finish */
176*f026d8caSVitaly Lifshits if (adapter->hw.mac.autoneg)
177*f026d8caSVitaly Lifshits ssleep(5);
178*f026d8caSVitaly Lifshits
179*f026d8caSVitaly Lifshits link_up = igc_has_link(adapter);
180*f026d8caSVitaly Lifshits if (!link_up) {
181*f026d8caSVitaly Lifshits *data = 1;
182*f026d8caSVitaly Lifshits return false;
183*f026d8caSVitaly Lifshits }
184*f026d8caSVitaly Lifshits
185*f026d8caSVitaly Lifshits return true;
186*f026d8caSVitaly Lifshits }
187