1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 25b2e6555SGreg Ungerer /* 35b2e6555SGreg Ungerer * File: m54xxgpt.h 45b2e6555SGreg Ungerer * Purpose: Register and bit definitions for the MCF54XX 55b2e6555SGreg Ungerer * 65b2e6555SGreg Ungerer * Notes: 75b2e6555SGreg Ungerer * 85b2e6555SGreg Ungerer */ 95b2e6555SGreg Ungerer 105b2e6555SGreg Ungerer #ifndef m54xxgpt_h 115b2e6555SGreg Ungerer #define m54xxgpt_h 125b2e6555SGreg Ungerer 135b2e6555SGreg Ungerer /********************************************************************* 145b2e6555SGreg Ungerer * 155b2e6555SGreg Ungerer * General Purpose Timers (GPT) 165b2e6555SGreg Ungerer * 175b2e6555SGreg Ungerer *********************************************************************/ 185b2e6555SGreg Ungerer 195b2e6555SGreg Ungerer /* Register read/write macros */ 20944c3d81SGreg Ungerer #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800) 21944c3d81SGreg Ungerer #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804) 22944c3d81SGreg Ungerer #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808) 23944c3d81SGreg Ungerer #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C) 24944c3d81SGreg Ungerer #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810) 25944c3d81SGreg Ungerer #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814) 26944c3d81SGreg Ungerer #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818) 27944c3d81SGreg Ungerer #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C) 28944c3d81SGreg Ungerer #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820) 29944c3d81SGreg Ungerer #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824) 30944c3d81SGreg Ungerer #define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828) 31944c3d81SGreg Ungerer #define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C) 32944c3d81SGreg Ungerer #define MCF_GPT_GMS3 (MCF_MBAR + 0x000830) 33944c3d81SGreg Ungerer #define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834) 34944c3d81SGreg Ungerer #define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838) 35944c3d81SGreg Ungerer #define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C) 36944c3d81SGreg Ungerer #define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010)) 37944c3d81SGreg Ungerer #define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010)) 38944c3d81SGreg Ungerer #define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010)) 39944c3d81SGreg Ungerer #define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010)) 405b2e6555SGreg Ungerer 415b2e6555SGreg Ungerer /* Bit definitions and macros for MCF_GPT_GMS */ 425b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) 435b2e6555SGreg Ungerer #define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) 445b2e6555SGreg Ungerer #define MCF_GPT_GMS_IEN (0x00000100) 455b2e6555SGreg Ungerer #define MCF_GPT_GMS_OD (0x00000200) 465b2e6555SGreg Ungerer #define MCF_GPT_GMS_SC (0x00000400) 475b2e6555SGreg Ungerer #define MCF_GPT_GMS_CE (0x00001000) 485b2e6555SGreg Ungerer #define MCF_GPT_GMS_WDEN (0x00008000) 495b2e6555SGreg Ungerer #define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) 505b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) 515b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) 525b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) 535b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) 545b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCT_PULSELO (0x00200000) 555b2e6555SGreg Ungerer #define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) 565b2e6555SGreg Ungerer #define MCF_GPT_GMS_ICT_ANY (0x00000000) 575b2e6555SGreg Ungerer #define MCF_GPT_GMS_ICT_RISE (0x00010000) 585b2e6555SGreg Ungerer #define MCF_GPT_GMS_ICT_FALL (0x00020000) 595b2e6555SGreg Ungerer #define MCF_GPT_GMS_ICT_PULSE (0x00030000) 605b2e6555SGreg Ungerer #define MCF_GPT_GMS_GPIO_INPUT (0x00000000) 615b2e6555SGreg Ungerer #define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) 625b2e6555SGreg Ungerer #define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) 636a7f6ec9SLinus Torvalds #define MCF_GPT_GMS_GPIO_MASK (0x00000030) 645b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS_DISABLE (0x00000000) 655b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS_INCAPT (0x00000001) 665b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) 675b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS_PWM (0x00000003) 685b2e6555SGreg Ungerer #define MCF_GPT_GMS_TMS_GPIO (0x00000004) 696a7f6ec9SLinus Torvalds #define MCF_GPT_GMS_TMS_MASK (0x00000007) 705b2e6555SGreg Ungerer 715b2e6555SGreg Ungerer /* Bit definitions and macros for MCF_GPT_GCIR */ 725b2e6555SGreg Ungerer #define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) 735b2e6555SGreg Ungerer #define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) 745b2e6555SGreg Ungerer 755b2e6555SGreg Ungerer /* Bit definitions and macros for MCF_GPT_GPWM */ 765b2e6555SGreg Ungerer #define MCF_GPT_GPWM_LOAD (0x00000001) 775b2e6555SGreg Ungerer #define MCF_GPT_GPWM_PWMOP (0x00000100) 785b2e6555SGreg Ungerer #define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) 795b2e6555SGreg Ungerer 805b2e6555SGreg Ungerer /* Bit definitions and macros for MCF_GPT_GSR */ 815b2e6555SGreg Ungerer #define MCF_GPT_GSR_CAPT (0x00000001) 825b2e6555SGreg Ungerer #define MCF_GPT_GSR_COMP (0x00000002) 835b2e6555SGreg Ungerer #define MCF_GPT_GSR_PWMP (0x00000004) 845b2e6555SGreg Ungerer #define MCF_GPT_GSR_TEXP (0x00000008) 855b2e6555SGreg Ungerer #define MCF_GPT_GSR_PIN (0x00000100) 865b2e6555SGreg Ungerer #define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) 875b2e6555SGreg Ungerer #define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) 885b2e6555SGreg Ungerer 895b2e6555SGreg Ungerer /********************************************************************/ 905b2e6555SGreg Ungerer 915b2e6555SGreg Ungerer #endif /* m54xxgpt_h */ 92