Lines Matching +full:0 +full:x0000ffff
9 #define MFW_TRACE_SIGNATURE 0x25071946
12 #define MFW_TRACE_EVENTID_MASK 0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
22 * 0 - just errors will be written to the buffer
24 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
53 #define OFFSIZE_OFFSET_SHIFT 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
57 #define OFFSIZE_SIZE_MASK 0xffff0000
77 #define ETH_SPEED_AUTONEG 0x0
78 #define ETH_SPEED_SMARTLINQ 0x8
81 #define ETH_PAUSE_NONE 0x0
82 #define ETH_PAUSE_AUTONEG 0x1
83 #define ETH_PAUSE_RX 0x2
84 #define ETH_PAUSE_TX 0x4
89 #define ETH_LOOPBACK_NONE 0x0
90 #define ETH_LOOPBACK_INT_PHY 0x1
91 #define ETH_LOOPBACK_EXT_PHY 0x2
92 #define ETH_LOOPBACK_EXT 0x3
93 #define ETH_LOOPBACK_MAC 0x4
94 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 0x5
95 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 0x6
96 #define ETH_LOOPBACK_PCS_AH_ONLY 0x7
97 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY 0x8
98 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY 0x9
101 #define EEE_CFG_EEE_ENABLED BIT(0)
105 #define EEE_TX_TIMER_USEC_MASK 0xfffffff0
107 #define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00
108 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100
109 #define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000
114 #define FEC_FORCE_MODE_MASK 0x000000ff
115 #define FEC_FORCE_MODE_OFFSET 0
116 #define FEC_FORCE_MODE_NONE 0x00
117 #define FEC_FORCE_MODE_FIRECODE 0x01
118 #define FEC_FORCE_MODE_RS 0x02
119 #define FEC_FORCE_MODE_AUTO 0x07
120 #define FEC_EXTENDED_MODE_MASK 0xffffff00
122 #define ETH_EXT_FEC_NONE 0x00000000
123 #define ETH_EXT_FEC_10G_NONE 0x00000100
124 #define ETH_EXT_FEC_10G_BASE_R 0x00000200
125 #define ETH_EXT_FEC_25G_NONE 0x00000400
126 #define ETH_EXT_FEC_25G_BASE_R 0x00000800
127 #define ETH_EXT_FEC_25G_RS528 0x00001000
128 #define ETH_EXT_FEC_40G_NONE 0x00002000
129 #define ETH_EXT_FEC_40G_BASE_R 0x00004000
130 #define ETH_EXT_FEC_50G_NONE 0x00008000
131 #define ETH_EXT_FEC_50G_BASE_R 0x00010000
132 #define ETH_EXT_FEC_50G_RS528 0x00020000
133 #define ETH_EXT_FEC_50G_RS544 0x00040000
134 #define ETH_EXT_FEC_100G_NONE 0x00080000
135 #define ETH_EXT_FEC_100G_BASE_R 0x00100000
136 #define ETH_EXT_FEC_100G_RS528 0x00200000
137 #define ETH_EXT_FEC_100G_RS544 0x00400000
140 #define ETH_EXT_SPEED_MASK 0x0000ffff
141 #define ETH_EXT_SPEED_OFFSET 0
142 #define ETH_EXT_SPEED_NONE 0x00000001
143 #define ETH_EXT_SPEED_1G 0x00000002
144 #define ETH_EXT_SPEED_10G 0x00000004
145 #define ETH_EXT_SPEED_25G 0x00000008
146 #define ETH_EXT_SPEED_40G 0x00000010
147 #define ETH_EXT_SPEED_50G_BASE_R 0x00000020
148 #define ETH_EXT_SPEED_50G_BASE_R2 0x00000040
149 #define ETH_EXT_SPEED_100G_BASE_R2 0x00000080
150 #define ETH_EXT_SPEED_100G_BASE_R4 0x00000100
151 #define ETH_EXT_SPEED_100G_BASE_P4 0x00000200
152 #define ETH_EXT_ADV_SPEED_MASK 0xFFFF0000
154 #define ETH_EXT_ADV_SPEED_1G 0x00010000
155 #define ETH_EXT_ADV_SPEED_10G 0x00020000
156 #define ETH_EXT_ADV_SPEED_25G 0x00040000
157 #define ETH_EXT_ADV_SPEED_40G 0x00080000
158 #define ETH_EXT_ADV_SPEED_50G_BASE_R 0x00100000
159 #define ETH_EXT_ADV_SPEED_50G_BASE_R2 0x00200000
160 #define ETH_EXT_ADV_SPEED_100G_BASE_R2 0x00400000
161 #define ETH_EXT_ADV_SPEED_100G_BASE_R4 0x00800000
162 #define ETH_EXT_ADV_SPEED_100G_BASE_P4 0x01000000
167 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
168 #define PORT_MF_CFG_OV_TAG_SHIFT 0
276 #define PORT_CMT_IN_TEAM BIT(0)
279 #define PORT_CMT_PORT_INACTIVE (0 << 1)
283 #define PORT_CMT_TEAM0 (0 << 2)
294 LLDP_NEAREST_BRIDGE = 0,
302 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
303 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
304 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
306 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
308 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
310 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
326 #define DCBX_ETS_ENABLED_MASK 0x00000001
327 #define DCBX_ETS_ENABLED_SHIFT 0
328 #define DCBX_ETS_WILLING_MASK 0x00000002
330 #define DCBX_ETS_ERROR_MASK 0x00000004
332 #define DCBX_ETS_CBS_MASK 0x00000008
334 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
336 #define DCBX_OOO_TC_MASK 0x00000f00
343 #define DCBX_CEE_STRICT_PRIORITY 0xf
346 #define DCBX_ETS_TSA_STRICT 0
356 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
357 #define DCBX_APP_PRI_MAP_SHIFT 0
358 #define DCBX_APP_PRI_0 0x01
359 #define DCBX_APP_PRI_1 0x02
360 #define DCBX_APP_PRI_2 0x04
361 #define DCBX_APP_PRI_3 0x08
362 #define DCBX_APP_PRI_4 0x10
363 #define DCBX_APP_PRI_5 0x20
364 #define DCBX_APP_PRI_6 0x40
365 #define DCBX_APP_PRI_7 0x80
366 #define DCBX_APP_SF_MASK 0x00000300
368 #define DCBX_APP_SF_ETHTYPE 0
370 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
372 #define DCBX_APP_SF_IEEE_RESERVED 0
378 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
384 #define DCBX_APP_ENABLED_MASK 0x00000001
385 #define DCBX_APP_ENABLED_SHIFT 0
386 #define DCBX_APP_WILLING_MASK 0x00000002
388 #define DCBX_APP_ERROR_MASK 0x00000004
390 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
392 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
400 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
401 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
402 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
403 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
404 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
405 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
406 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
407 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
408 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
409 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
411 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
413 #define DCBX_PFC_CAPS_MASK 0x00000f00
415 #define DCBX_PFC_MBC_MASK 0x00004000
417 #define DCBX_PFC_WILLING_MASK 0x00008000
419 #define DCBX_PFC_ENABLED_MASK 0x00010000
421 #define DCBX_PFC_ERROR_MASK 0x00020000
429 #define DCBX_CONFIG_VERSION_MASK 0x00000007
430 #define DCBX_CONFIG_VERSION_SHIFT 0
431 #define DCBX_CONFIG_VERSION_DISABLED 0
449 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1
450 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0
451 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2
453 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000
467 #define DCB_DSCP_ENABLE_MASK 0x1
468 #define DCB_DSCP_ENABLE_SHIFT 0
493 ATTRIBUTE_CMD_READ = 0,
544 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
545 #define PROCESS_KILL_COUNTER_SHIFT 0
546 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
582 #define LINK_STATUS_LINK_UP 0x00000001
583 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
592 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
593 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
594 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
595 #define LINK_STATUS_PFC_ENABLED 0x00000100
596 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
597 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
598 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
599 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
600 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
601 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
602 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
603 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
604 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000
605 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
609 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
610 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
611 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
612 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
613 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
614 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
615 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
617 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
618 #define LINK_STATUS_FEC_MODE_NONE (0 << 27)
635 #define MEDIA_UNSPECIFIED 0x0
636 #define MEDIA_SFPP_10G_FIBER 0x1
637 #define MEDIA_XFP_FIBER 0x2
638 #define MEDIA_DA_TWINAX 0x3
639 #define MEDIA_BASE_T 0x4
640 #define MEDIA_SFP_1G_FIBER 0x5
641 #define MEDIA_MODULE_FIBER 0x6
642 #define MEDIA_KR 0xf0
643 #define MEDIA_NOT_PRESENT 0xff
661 #define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
662 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
663 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
664 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
665 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
666 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
667 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
668 #define ETH_TRANSCEIVER_STATE_IN_SETUP 0x10
669 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
670 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
671 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
672 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
673 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
674 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
675 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
676 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
677 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
678 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
679 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
680 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
681 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
682 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
683 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
684 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
685 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
686 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
687 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
688 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
689 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
690 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
691 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
692 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
693 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
694 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
695 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
696 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
697 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
698 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
699 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
700 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
701 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
702 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
703 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
704 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
705 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
706 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
707 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
708 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
709 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
710 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
711 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
712 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
713 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
714 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37
715 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38
716 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39
717 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a
725 #define EEE_ACTIVE_BIT BIT(0)
726 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
730 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
732 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
738 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
739 #define EEE_REMOTE_TW_TX_OFFSET 0
740 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
746 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
747 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
748 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
749 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
750 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
752 #define OEM_CFG_SCHED_TYPE_ETS 0x1
753 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
789 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
790 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
791 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
793 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
795 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
796 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
797 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
798 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
799 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
801 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
803 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
804 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
806 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
809 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
812 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
813 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
816 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
825 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
826 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
838 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
839 #define DRV_ID_PDA_COMP_VER_SHIFT 0
842 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
847 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
849 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
852 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
857 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
858 #define OEM_CFG_FUNC_TC_OFFSET 0
859 #define OEM_CFG_FUNC_TC_0 0x0
860 #define OEM_CFG_FUNC_TC_1 0x1
861 #define OEM_CFG_FUNC_TC_2 0x2
862 #define OEM_CFG_FUNC_TC_3 0x3
863 #define OEM_CFG_FUNC_TC_4 0x4
864 #define OEM_CFG_FUNC_TC_5 0x5
865 #define OEM_CFG_FUNC_TC_6 0x6
866 #define OEM_CFG_FUNC_TC_7 0x7
868 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
870 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
871 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
952 RESOURCE_NUM_SB_E = 0,
976 RESOURCE_NUM_INVALID = 0xFFFFFFFF
989 #define RESOURCE_ELEMENT_STRICT BIT(0)
997 #define DRV_ROLE_NONE 0
1007 #define LOAD_REQ_ROLE_MASK 0x000000FF
1008 #define LOAD_REQ_ROLE_SHIFT 0
1009 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
1011 #define LOAD_REQ_LOCK_TO_DEFAULT 0
1013 #define LOAD_REQ_FORCE_MASK 0x000F0000
1015 #define LOAD_REQ_FORCE_NONE 0
1018 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
1020 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
1028 #define LOAD_RSP_ROLE_MASK 0x000000FF
1029 #define LOAD_RSP_ROLE_SHIFT 0
1030 #define LOAD_RSP_HSI_MASK 0x0000FF00
1032 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
1034 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
1109 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1110 #define DRV_MSG_SEQ_NUMBER_OFFSET 0
1111 #define DRV_MSG_CODE_MASK 0xffff0000
1117 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1118 #define FW_MSG_SEQ_NUMBER_OFFSET 0
1119 #define FW_MSG_CODE_MASK 0xffff0000
1125 #define DRV_PULSE_SEQ_MASK 0x00007fff
1126 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1127 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1130 #define MCP_PULSE_SEQ_MASK 0x00007fff
1131 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1132 #define MCP_EVENT_MASK 0xffff0000
1133 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1140 DRV_MSG_CODE_NVM_PUT_FILE_BEGIN = DRV_MSG_CODE(0x0001),
1141 DRV_MSG_CODE_NVM_PUT_FILE_DATA = DRV_MSG_CODE(0x0002),
1142 DRV_MSG_CODE_NVM_GET_FILE_ATT = DRV_MSG_CODE(0x0003),
1143 DRV_MSG_CODE_NVM_READ_NVRAM = DRV_MSG_CODE(0x0005),
1144 DRV_MSG_CODE_NVM_WRITE_NVRAM = DRV_MSG_CODE(0x0006),
1145 DRV_MSG_CODE_MCP_RESET = DRV_MSG_CODE(0x0009),
1146 DRV_MSG_CODE_SET_VERSION = DRV_MSG_CODE(0x000f),
1147 DRV_MSG_CODE_MCP_HALT = DRV_MSG_CODE(0x0010),
1148 DRV_MSG_CODE_SET_VMAC = DRV_MSG_CODE(0x0011),
1149 DRV_MSG_CODE_GET_VMAC = DRV_MSG_CODE(0x0012),
1150 DRV_MSG_CODE_GET_STATS = DRV_MSG_CODE(0x0013),
1151 DRV_MSG_CODE_TRANSCEIVER_READ = DRV_MSG_CODE(0x0016),
1152 DRV_MSG_CODE_MASK_PARITIES = DRV_MSG_CODE(0x001a),
1153 DRV_MSG_CODE_BIST_TEST = DRV_MSG_CODE(0x001e),
1154 DRV_MSG_CODE_SET_LED_MODE = DRV_MSG_CODE(0x0020),
1155 DRV_MSG_CODE_RESOURCE_CMD = DRV_MSG_CODE(0x0023),
1156 DRV_MSG_CODE_MDUMP_CMD = DRV_MSG_CODE(0x0025),
1157 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL = DRV_MSG_CODE(0x002b),
1158 DRV_MSG_CODE_OS_WOL = DRV_MSG_CODE(0x002e),
1159 DRV_MSG_CODE_GET_TLV_DONE = DRV_MSG_CODE(0x002f),
1160 DRV_MSG_CODE_FEATURE_SUPPORT = DRV_MSG_CODE(0x0030),
1161 DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT = DRV_MSG_CODE(0x0031),
1162 DRV_MSG_CODE_GET_ENGINE_CONFIG = DRV_MSG_CODE(0x0037),
1163 DRV_MSG_CODE_GET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003e),
1164 DRV_MSG_CODE_SET_NVM_CFG_OPTION = DRV_MSG_CODE(0x003f),
1165 DRV_MSG_CODE_INITIATE_PF_FLR = DRV_MSG_CODE(0x0201),
1166 DRV_MSG_CODE_LOAD_REQ = DRV_MSG_CODE(0x1000),
1167 DRV_MSG_CODE_LOAD_DONE = DRV_MSG_CODE(0x1100),
1168 DRV_MSG_CODE_INIT_HW = DRV_MSG_CODE(0x1200),
1169 DRV_MSG_CODE_CANCEL_LOAD_REQ = DRV_MSG_CODE(0x1300),
1170 DRV_MSG_CODE_UNLOAD_REQ = DRV_MSG_CODE(0x2000),
1171 DRV_MSG_CODE_UNLOAD_DONE = DRV_MSG_CODE(0x2100),
1172 DRV_MSG_CODE_INIT_PHY = DRV_MSG_CODE(0x2200),
1173 DRV_MSG_CODE_LINK_RESET = DRV_MSG_CODE(0x2300),
1174 DRV_MSG_CODE_SET_DCBX = DRV_MSG_CODE(0x2500),
1175 DRV_MSG_CODE_OV_UPDATE_CURR_CFG = DRV_MSG_CODE(0x2600),
1176 DRV_MSG_CODE_OV_UPDATE_BUS_NUM = DRV_MSG_CODE(0x2700),
1177 DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS = DRV_MSG_CODE(0x2800),
1178 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER = DRV_MSG_CODE(0x2900),
1179 DRV_MSG_CODE_NIG_DRAIN = DRV_MSG_CODE(0x3000),
1180 DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE = DRV_MSG_CODE(0x3100),
1181 DRV_MSG_CODE_BW_UPDATE_ACK = DRV_MSG_CODE(0x3200),
1182 DRV_MSG_CODE_OV_UPDATE_MTU = DRV_MSG_CODE(0x3300),
1183 DRV_MSG_GET_RESOURCE_ALLOC_MSG = DRV_MSG_CODE(0x3400),
1184 DRV_MSG_SET_RESOURCE_VALUE_MSG = DRV_MSG_CODE(0x3500),
1185 DRV_MSG_CODE_OV_UPDATE_WOL = DRV_MSG_CODE(0x3800),
1186 DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE = DRV_MSG_CODE(0x3900),
1187 DRV_MSG_CODE_S_TAG_UPDATE_ACK = DRV_MSG_CODE(0x3b00),
1188 DRV_MSG_CODE_GET_OEM_UPDATES = DRV_MSG_CODE(0x4100),
1189 DRV_MSG_CODE_GET_PPFID_BITMAP = DRV_MSG_CODE(0x4300),
1190 DRV_MSG_CODE_VF_DISABLED_DONE = DRV_MSG_CODE(0xc000),
1191 DRV_MSG_CODE_CFG_VF_MSIX = DRV_MSG_CODE(0xc001),
1192 DRV_MSG_CODE_CFG_PF_VFS_MSIX = DRV_MSG_CODE(0xc002),
1193 DRV_MSG_CODE_DEBUG_DATA_SEND = DRV_MSG_CODE(0xc004),
1194 DRV_MSG_CODE_GET_MANAGEMENT_STATUS = DRV_MSG_CODE(0xc007),
1198 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
1204 #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_SHIFT 0
1205 #define DRV_MSG_CODE_RETAIN_VMAC_FUNC_MASK 0xf
1208 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_MASK 0x70
1209 #define DRV_MSG_CODE_RETAIN_VMAC_TYPE_L2 0
1215 #define DRV_MSG_CODE_MCP_RESET_FORCE 0xf04ce
1222 #define BW_MAX_MASK 0x000000ff
1223 #define BW_MAX_OFFSET 0
1224 #define BW_MIN_MASK 0x0000ff00
1227 #define DRV_MSG_FAN_FAILURE_TYPE BIT(0)
1230 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
1231 #define RESOURCE_CMD_REQ_RESC_SHIFT 0
1232 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
1239 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
1242 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
1243 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0
1244 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
1253 #define RESOURCE_DUMP 0
1256 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x000000ff
1257 #define DRV_MSG_CODE_MDUMP_ACK 0x01
1258 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
1259 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
1260 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
1261 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
1262 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06
1263 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07
1264 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08
1266 #define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a
1268 #define DRV_MSG_CODE_MDUMP_FREE_DRIVER_BUF 0x0b
1269 #define DRV_MSG_CODE_MDUMP_GEN_LINK_DUMP 0x0c
1270 #define DRV_MSG_CODE_MDUMP_GEN_IDLE_CHK 0x0d
1273 #define MDUMP_DRV_PARAM_OPTION_MASK 0x00000f00
1275 #define DRV_MSG_CODE_MDUMP_USE_DRIVER_BUF_MASK 0x100
1278 #define DRV_MB_PARAM_ADDR_SHIFT 0
1279 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF
1281 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000
1283 #define DRV_MB_PARAM_PORT_MASK 0x00600000
1286 #define DRV_MB_PARAM_PMBUS_CMD_SHIFT 0
1287 #define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF
1289 #define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300
1291 #define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000
1294 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
1295 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
1296 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
1297 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
1300 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
1303 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
1304 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
1307 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
1308 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
1309 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
1311 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001
1312 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_SHIFT 0
1313 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0
1315 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
1317 #define DRV_MB_PARAM_DCBX_ADMIN_CFG_NOTIFY_MASK 0x00000010
1320 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
1321 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
1323 #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_MASK 0x000000ff
1324 #define DRV_MB_PARAM_NVM_PUT_FILE_TYPE_SHIFT 0
1325 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
1326 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
1328 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
1329 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
1330 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
1332 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
1334 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
1335 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
1337 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
1339 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
1340 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
1341 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
1346 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
1347 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
1348 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
1349 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
1350 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
1351 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
1353 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
1354 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
1355 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
1356 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
1357 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
1358 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
1359 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
1361 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
1362 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
1374 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
1375 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
1376 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
1378 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
1379 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
1381 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
1382 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
1383 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
1385 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
1386 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
1388 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc
1390 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00
1392 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000
1395 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
1397 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
1398 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
1400 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
1406 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
1411 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
1412 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff
1414 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00
1416 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff
1417 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
1418 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001
1419 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
1420 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004
1421 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL 0x00000008
1422 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
1425 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
1426 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff
1429 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
1430 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff
1432 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000
1434 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
1435 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff
1436 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_IGNORE 0x0000ffff
1437 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
1439 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
1441 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
1443 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
1445 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
1447 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
1449 #define DRV_MB_PARAM_NVM_CFG_OPTION_DEFAULT_RESTORE_ALL_MASK 0x00200000
1451 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
1454 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_SHIFT 0
1455 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_MASK 0xF
1456 #define DRV_MSG_CODE_GET_PERM_MAC_TYPE_PF 0
1462 #define DRV_MSG_CODE_GET_PERM_MAC_INDEX_MASK 0xFFFF00
1466 FW_MSG_CODE_UNSUPPORTED = FW_MSG_CODE(0x0000),
1467 FW_MSG_CODE_NVM_OK = FW_MSG_CODE(0x0001),
1468 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK = FW_MSG_CODE(0x0040),
1469 FW_MSG_CODE_PHY_OK = FW_MSG_CODE(0x0011),
1470 FW_MSG_CODE_OK = FW_MSG_CODE(0x0016),
1471 FW_MSG_CODE_ERROR = FW_MSG_CODE(0x0017),
1472 FW_MSG_CODE_TRANSCEIVER_DIAG_OK = FW_MSG_CODE(0x0016),
1473 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT = FW_MSG_CODE(0x0002),
1474 FW_MSG_CODE_MDUMP_INVALID_CMD = FW_MSG_CODE(0x0003),
1475 FW_MSG_CODE_OS_WOL_SUPPORTED = FW_MSG_CODE(0x0080),
1476 FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE = FW_MSG_CODE(0x0087),
1477 FW_MSG_CODE_DRV_LOAD_ENGINE = FW_MSG_CODE(0x1010),
1478 FW_MSG_CODE_DRV_LOAD_PORT = FW_MSG_CODE(0x1011),
1479 FW_MSG_CODE_DRV_LOAD_FUNCTION = FW_MSG_CODE(0x1012),
1480 FW_MSG_CODE_DRV_LOAD_REFUSED_PDA = FW_MSG_CODE(0x1020),
1481 FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 = FW_MSG_CODE(0x1021),
1482 FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG = FW_MSG_CODE(0x1022),
1483 FW_MSG_CODE_DRV_LOAD_REFUSED_HSI = FW_MSG_CODE(0x1023),
1484 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE = FW_MSG_CODE(0x1030),
1485 FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT = FW_MSG_CODE(0x1031),
1486 FW_MSG_CODE_DRV_LOAD_DONE = FW_MSG_CODE(0x1110),
1487 FW_MSG_CODE_DRV_UNLOAD_ENGINE = FW_MSG_CODE(0x2011),
1488 FW_MSG_CODE_DRV_UNLOAD_PORT = FW_MSG_CODE(0x2012),
1489 FW_MSG_CODE_DRV_UNLOAD_FUNCTION = FW_MSG_CODE(0x2013),
1490 FW_MSG_CODE_DRV_UNLOAD_DONE = FW_MSG_CODE(0x2110),
1491 FW_MSG_CODE_RESOURCE_ALLOC_OK = FW_MSG_CODE(0x3400),
1492 FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN = FW_MSG_CODE(0x3500),
1493 FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE = FW_MSG_CODE(0x3b00),
1494 FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE = FW_MSG_CODE(0xb001),
1495 FW_MSG_CODE_DEBUG_NOT_ENABLED = FW_MSG_CODE(0xb00a),
1496 FW_MSG_CODE_DEBUG_DATA_SEND_OK = FW_MSG_CODE(0xb00b),
1499 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
1501 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
1502 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
1505 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
1506 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
1507 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
1508 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
1511 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0)
1526 #define FW_MB_PARAM_MANAGEMENT_STATUS_LOCKDOWN_ENABLED 0x00000001
1528 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
1530 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
1531 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
1532 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
1534 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
1536 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
1539 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
1540 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
1542 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
1543 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
1544 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
1580 #define MFW_DRV_MSG_OFFSET(msg_id) (((msg_id) & 0x3) << 3)
1581 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
1624 #define I2C_TRANSCEIVER_ADDR 0xa0
1856 #define I2C_DEV_ADDR_A2 0xa2
1857 #define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60
1859 #define SFP_EEPROM_A2_VCC_ADDR 0x62
1861 #define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64
1863 #define SFP_EEPROM_A2_TX_POWER_ADDR 0x66
1865 #define SFP_EEPROM_A2_RX_POWER_ADDR 0x68
1868 #define I2C_DEV_ADDR_A0 0xa0
1869 #define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16
1871 #define QSFP_EEPROM_A0_VCC_ADDR 0x1a
1873 #define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a
1875 #define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32
1877 #define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22
1882 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
1883 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
1890 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
1892 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
1893 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
1894 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
1895 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
1896 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
1897 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
1898 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
1899 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
1908 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
1909 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
1910 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
1911 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
1912 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
1913 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
1914 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
1915 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
1916 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
1917 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
1918 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
1919 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
1920 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
1921 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11
1922 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12
1923 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13
1924 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14
1925 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15
1948 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
1949 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
1950 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
1952 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
1959 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
1960 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
1961 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
1962 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
1963 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
2019 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
2021 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
2022 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
2023 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
2024 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
2025 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
2027 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
2028 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
2029 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
2035 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
2036 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
2037 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
2038 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
2039 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
2040 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
2041 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
2042 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
2043 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
2046 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
2047 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
2048 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
2049 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
2050 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
2051 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
2052 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
2053 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
2054 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
2055 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
2056 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
2057 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
2059 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
2060 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
2061 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
2062 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000
2064 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
2065 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
2066 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
2067 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
2074 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
2076 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
2077 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
2078 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
2079 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
2090 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
2091 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
2092 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
2093 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
2094 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
2095 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
2096 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
2118 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff
2119 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
2120 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1
2121 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
2122 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
2123 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8
2124 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10
2125 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20
2126 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40
2127 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80
2128 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100
2129 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200
2130 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400
2131 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000
2133 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1
2134 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
2135 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
2136 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8
2137 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10
2138 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20
2139 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40
2140 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80
2141 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100
2142 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200
2143 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400
2200 #define PORT_0 0
2211 #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
2253 #define CRC_MAGIC_VALUE 0xDEBB20E3
2254 #define CRC32_POLYNOMIAL 0xEDB88320
2267 #define NVM_MAGIC_VALUE 0x669955aa
2283 NVM_TYPE_TIM1 = 0x01,
2284 NVM_TYPE_TIM2 = 0x02,
2285 NVM_TYPE_MIM1 = 0x03,
2286 NVM_TYPE_MIM2 = 0x04,
2287 NVM_TYPE_MBA = 0x05,
2288 NVM_TYPE_MODULES_PN = 0x06,
2289 NVM_TYPE_VPD = 0x07,
2290 NVM_TYPE_MFW_TRACE1 = 0x08,
2291 NVM_TYPE_MFW_TRACE2 = 0x09,
2292 NVM_TYPE_NVM_CFG1 = 0x0a,
2293 NVM_TYPE_L2B = 0x0b,
2294 NVM_TYPE_DIR1 = 0x0c,
2295 NVM_TYPE_EAGLE_FW1 = 0x0d,
2296 NVM_TYPE_FALCON_FW1 = 0x0e,
2297 NVM_TYPE_PCIE_FW1 = 0x0f,
2298 NVM_TYPE_HW_SET = 0x10,
2299 NVM_TYPE_LIM = 0x11,
2300 NVM_TYPE_AVS_FW1 = 0x12,
2301 NVM_TYPE_DIR2 = 0x13,
2302 NVM_TYPE_CCM = 0x14,
2303 NVM_TYPE_EAGLE_FW2 = 0x15,
2304 NVM_TYPE_FALCON_FW2 = 0x16,
2305 NVM_TYPE_PCIE_FW2 = 0x17,
2306 NVM_TYPE_AVS_FW2 = 0x18,
2307 NVM_TYPE_INIT_HW = 0x19,
2308 NVM_TYPE_DEFAULT_CFG = 0x1a,
2309 NVM_TYPE_MDUMP = 0x1b,
2310 NVM_TYPE_NVM_META = 0x1c,
2311 NVM_TYPE_ISCSI_CFG = 0x1d,
2312 NVM_TYPE_FCOE_CFG = 0x1f,
2313 NVM_TYPE_ETH_PHY_FW1 = 0x20,
2314 NVM_TYPE_ETH_PHY_FW2 = 0x21,
2315 NVM_TYPE_BDN = 0x22,
2316 NVM_TYPE_8485X_PHY_FW = 0x23,
2317 NVM_TYPE_PUB_KEY = 0x24,
2318 NVM_TYPE_RECOVERY = 0x25,
2319 NVM_TYPE_PLDM = 0x26,
2320 NVM_TYPE_UPK1 = 0x27,
2321 NVM_TYPE_UPK2 = 0x28,
2322 NVM_TYPE_MASTER_KC = 0x29,
2323 NVM_TYPE_BACKUP_KC = 0x2a,
2324 NVM_TYPE_HW_DUMP = 0x2b,
2325 NVM_TYPE_HW_DUMP_OUT = 0x2c,
2326 NVM_TYPE_BIN_NVM_META = 0x30,
2327 NVM_TYPE_ROM_TEST = 0xf0,
2328 NVM_TYPE_88X33X0_PHY_FW = 0x31,
2329 NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
2330 NVM_TYPE_IDLE_CHK = 0x33,
2345 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
2346 #define NVM_DIR_SEQ_MASK 0xfffffffe
2375 #define DIR_ID_1 (0)
2379 #define MFW_BUNDLE_1 (0)
2383 #define FLASH_PAGE_SIZE 0x1000
2387 #define FPGA_MIM_MAX_SIZE (0x40000)
2398 : 0))
2415 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->(f)))))
2435 #define POR_RESET_TYPE BIT(0)
2452 #define NVM_META_BIN_OPTION_OFFSET_MASK 0x0000ffff
2453 #define NVM_META_BIN_OPTION_OFFSET_SHIFT 0
2454 #define NVM_META_BIN_OPTION_LEN_MASK 0x00ff0000
2456 #define NVM_META_BIN_OPTION_ENTITY_MASK 0x03000000
2458 #define NVM_META_BIN_OPTION_ENTITY_GLOB 0
2461 #define NVM_META_BIN_OPTION_CONFIG_TYPE_MASK 0x0c000000
2463 #define NVM_META_BIN_OPTION_CONFIG_TYPE_USER 0
2469 #define NVM_META_BIN_MAGIC 0x669955bb