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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h58 /* [0x0] Reserved register for the interrupt controller */
60 /* [0x4] Revision register */
62 /* [0x8] Reserved for future use */
64 /* [0xc] Reserved for future use */
66 /* [0x10] Reserved for future use */
68 /* [0x14] Reserved for future use */
70 /* [0x18] General timer configuration */
76 * [0x0] Mailbox interrupt generator.
80 /* [0x4] Mailbox message data out */
82 /* [0x8] Mailbox message data in */
[all …]
H A Dal_hal_udma_regs_m2s.h59 /* [0x0] Completion write master configuration */
61 /* [0x4] Completion write master configuration */
63 /* [0x8] Data read master configuration */
65 /* [0xc] Data read master configuration */
67 /* [0x10] Descriptor read master configuration */
69 /* [0x14] Descriptor read master configuration */
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Descriptors write master configuration (completion) */
77 /* [0x24] AXI outstanding configuration */
[all …]
H A Dal_hal_udma_regs_s2m.h59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
63 /* [0x8] Descriptor read master configuration */
65 /* [0xc] Descriptor read master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
73 /* [0x1c] Descriptors read master configuration */
75 /* [0x20] Completion descriptors write master configuration */
77 /* [0x24] AXI outstanding read configuration */
[all …]
/freebsd/sys/dev/alc/
H A Dif_alcreg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
47 #define DEVICEID_ATHEROS_AR8161 0x1091
48 #define DEVICEID_ATHEROS_AR8162 0x1090
49 #define DEVICEID_ATHEROS_AR8171 0x10A1
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd/sys/dev/ale/
H A Dif_alereg.h36 #define VENDORID_ATHEROS 0x1969
41 #define DEVICEID_ATHEROS_AR81XX 0x1026
43 #define ALE_SPI_CTRL 0x200
44 #define SPI_VPD_ENB 0x00002000
46 #define ALE_SPI_ADDR 0x204 /* 16bits */
48 #define ALE_SPI_DATA 0x208
50 #define ALE_SPI_CONFIG 0x20C
52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */
54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */
56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal.h43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
57 #define HAL_WLAON_REG_BASE 0x01f80000
60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h59 uint32_t aFramesTransmittedOK; /* 0x68 */
60 uint32_t aFramesReceivedOK; /* 0x6c */
61 uint32_t aFrameCheckSequenceErrors; /* 0x70 */
62 uint32_t aAlignmentErrors; /* 0x74 */
63 uint32_t aOctetsTransmittedOK; /* 0x78 */
64 uint32_t aOctetsReceivedOK; /* 0x7c */
65 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0x80 */
66 uint32_t aPAUSEMACCtrlFramesReceived; /* 0x84 */
67 uint32_t ifInErrors ; /* 0x88 */
68 uint32_t ifOutErrors; /* 0x8c */
[all …]
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dnvm_cfg.h43 #define NVM_CFG_version 0x83306
54 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
55 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
64 u32 generic_cont0; /* 0x0 */
65 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
66 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
67 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
68 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
69 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
70 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300radar.h20 #define HAL_RADAR_SMASK 0x0000FFFF /* Sequence number mask */
23 #define HAL_RADAR_IMASK 0x0000FFFF /* Index number mask */
32 #define HAL_RADAR_TSMASK 0x7FFF /* Mask for time stamp from descriptor */
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal.h36 #define HAL_SHADOW_BASE_ADDR 0x000008fc
44 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
45 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000
48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000
49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000
50 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000
51 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
53 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
[all …]
/freebsd/sys/amd64/acpica/
H A Dacpi_wakecode.S42 * (FirmwareWakingVector >> 4) and IP set to (FirmwareWakingVector & 0xf).
71 testb $~0, resume_beep - wakeup_start
73 movb $0, resume_beep - wakeup_start
85 movw $0x4c0, %ax
92 testb $~0, reset_video - wakeup_start
94 movb $0, reset_video - wakeup_start
95 lcall $0xc000, $3
97 /* When we reach here, int 0x10 should be ready. Hide cursor. */
98 movb $0x01, %ah
99 movb $0x20, %ch
[all …]
/freebsd/sys/dev/age/
H A Dif_agereg.h36 #define VENDORID_ATTANSIC 0x1969
41 #define DEVICEID_ATTANSIC_L1 0x1048
43 #define AGE_VPD_REG_CONF_START 0x0100
44 #define AGE_VPD_REG_CONF_END 0x01FF
45 #define AGE_VPD_REG_CONF_SIG 0x5A
47 #define AGE_SPI_CTRL 0x200
48 #define SPI_STAT_NOT_READY 0x00000001
49 #define SPI_STAT_WR_ENB 0x00000002
50 #define SPI_STAT_WRP_ENB 0x00000080
51 #define SPI_INST_MASK 0x000000FF
[all …]
/freebsd/sys/dev/bxe/
H A Decore_mfw_req.h35 #define PORT_0 0
44 #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
45 #define FCOE_IOS_PER_CONNECTION_SHIFT 0
47 #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
52 #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
53 #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
55 #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
60 #define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff
61 #define FCOE_TARGETS_SUPPORTED_SHIFT 0
63 #define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dgnu15 0 string \336\22\4\225 GNU message catalog (little endian),
16 #0 ulelong 0x950412DE GNU-format message catalog data
18 #>0 use gettext-object
19 #0 name gettext-object
27 >4 ulelong/0xFFff x %u.
29 >4 ulelong&0x0000FFff x \b%u
37 # for revision x.0 offset of table with originals is 1Ch if directly after header
38 >4 ulelong&0x0000FFff =0
39 >>12 ulelong !0x1C \b, at %#x string table
41 >4 ulelong&0x0000FFff >0
[all …]
/freebsd/sys/dev/malo/
H A Dif_malohal.c56 #define MALO_NOWAIT 0
59 pCmd = (_type *)&mh->mh_cmdbuf[0]; \
60 memset(pCmd, 0, sizeof(_type)); \
63 } while (0)
82 KASSERT(error == 0, ("error %u on bus_dma callback", error)); in malo_hal_load_cb()
119 PAGE_SIZE, 0, /* alignment, bounds */ in malo_hal_attach()
130 if (error != 0) { in malo_hal_attach()
140 if (error != 0) { in malo_hal_attach()
150 if (error != 0) { in malo_hal_attach()
193 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { in malo_hal_waitforcmd()
[all …]
/freebsd/sys/contrib/ncsw/inc/
H A Dtypes_freebsd.h42 #define FALSE 0
70 #define QE_32_BIT_ADDR(_arg) (uint32_t)((uint32_t)&(_arg) & 0xFFFFFFFC)
71 #define QE_32_BIT_SHIFT8(__arg) (uint32_t)((3 - ((uint32_t)&(__arg) & 0x3)) * 8)
72 #define QE_32_BIT_SHIFT16(__arg) (uint32_t)((2 - ((uint32_t)&(__arg) & 0x3)) * 8)
83 … tmp = (uint32_t)((tmp & ~(0x000000FF << shift)) | ((uint32_t)(data & 0x000000FF) << shift)); \
85 } while (0)
93 … tmp = (uint32_t)((tmp & ~(0x0000FFFF << shift)) | ((uint32_t)(data & 0x0000FFFF) << shift)); \
95 } while (0)
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
/freebsd/sys/dev/sge/
H A Dif_sgereg.h44 #define SIS_VENDORID 0x1039
49 #define SIS_DEVICEID_190 0x0190
50 #define SIS_DEVICEID_191 0x0191
52 #define TX_CTL 0x00
53 #define TX_DESC 0x04
54 #define Reserved0 0x08
55 #define TX_NEXT 0x0c
57 #define RX_CTL 0x10
58 #define RX_DESC 0x14
59 #define Reserved1 0x18
[all …]
/freebsd/sys/netinet/
H A Din_cksum.c65 sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
70 l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
71 sum = l_util.s[0] + l_util.s[1]; \
77 /*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/
78 0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF, /* offset 0 */
79 0x00000000, 0x0000FF00, 0x00FFFF00, 0xFFFFFF00, /* offset 1 */
80 0x00000000, 0x00FF0000, 0xFFFF0000, 0xFFFF0000, /* offset 2 */
81 0x00000000, 0xFF000000, 0xFF000000, 0xFF000000, /* offset 3 */
83 /*0 bytes*/ /*1 byte*/ /*2 bytes*/ /*3 bytes*/
84 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00, /* offset 0 */
[all …]
/freebsd/sys/dev/uart/
H A Duart_dev_imx.h32 #define IMXUART_URXD_REG 0x0000 /* UART Receiver Register */
39 #define IMXUART_URXD_RX_DATA_MASK 0xff
41 #define IMXUART_UTXD_REG 0x0040 /* UART Transmitter Register */
42 #define IMXUART_UTXD_TX_DATA_MASK 0xff
44 #define IMXUART_UCR1_REG 0x0080 /* UART Control Register 1 */
50 #define IMXUART_UCR1_ICD_IDLE4 (0 << 10)
63 #define IMXUART_UCR1_UARTEN (1 << 0)
65 #define IMXUART_UCR2_REG 0x0084 /* UART Control Register 2 */
72 #define IMXUART_UCR2_RTEC_REDGE (0 << 9)
83 #define IMXUART_UCR2_N_SRST (1 << 0)
[all …]
/freebsd/sys/compat/linuxkpi/common/include/net/
H A Dipv6.h56 scope = broadcast[5] & 0xF; in ipv6_ib_mc_map()
57 buf[0] = 0; in ipv6_ib_mc_map()
58 buf[1] = 0xff; in ipv6_ib_mc_map()
59 buf[2] = 0xff; in ipv6_ib_mc_map()
60 buf[3] = 0xff; in ipv6_ib_mc_map()
61 buf[4] = 0xff; in ipv6_ib_mc_map()
62 buf[5] = 0x10 | scope; in ipv6_ib_mc_map()
63 buf[6] = 0x60; in ipv6_ib_mc_map()
64 buf[7] = 0x1b; in ipv6_ib_mc_map()
85 addr[0] = wh; in __ipv6_addr_set_half()
[all …]

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