sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

Mechanically convert sge(4) to IfAPI

Sponsored by: Juniper Networks, Inc.
Differential Revision: https://reviews.freebsd.org/D37816

Merge ^/head r325842 through r325998.

spdx: initial adoption of licensing ID tags.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensou

spdx: initial adoption of licensing ID tags.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.

Initially, only tag files that use BSD 4-Clause "Original" license.

RelNotes: yes
Differential Revision: https://reviews.freebsd.org/D13133

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MFC @ r266724

An SVM update will follow this.

Merge head

IFC @264767

Increase the number of TX DMA segments from 32 to 35. It turned
out 32 is not enough to support a full sized TSO packet.
While I'm here fix a long standing bug introduced in r169632 in
bce(4) where

Increase the number of TX DMA segments from 32 to 35. It turned
out 32 is not enough to support a full sized TSO packet.
While I'm here fix a long standing bug introduced in r169632 in
bce(4) where it didn't include L2 header length of TSO packet in
the maximum DMA segment size calculation.

In collaboration with: rmacklem
MFC after: 2 weeks

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Merge svn+ssh://svn.freebsd.org/base/head@211344

Remove enabling RX checksum offloading in RX filter setup. RX
checksum is enabled in sge_init_locked().
While I'm here do not set RX checksum bits in RX descriptor
initialization. It is controller's

Remove enabling RX checksum offloading in RX filter setup. RX
checksum is enabled in sge_init_locked().
While I'm here do not set RX checksum bits in RX descriptor
initialization. It is controller's job to set these bits.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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Merge svn+ssh://svn.freebsd.org/base/head@208557

MFC r207851:
Implement TSO and TSO over VLAN. Increase number of allowed
fragmentation of mbuf chain to 32 from 16 because TSO can send 64KB
sized packet which in turn requires long list of mbu

MFC r207851:
Implement TSO and TSO over VLAN. Increase number of allowed
fragmentation of mbuf chain to 32 from 16 because TSO can send 64KB
sized packet which in turn requires long list of mbuf chain. Due to
lack of documentation, I'm not sure whether driver have to pull up
ethernet/IP/TCP header with options to make controller work but
driver have to parse TCP header to update pseudo TCP checksum
anyway. The controller expects pseudo TCP checksum computed by
upper stack and the checksum should follow the MS NDIS
specification to make TSO work.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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MFC r207628,207635:
r207628:
Enable multi-descriptor transmisstion for fragmented mbufs. There
is no more need to defragment mbufs. After transmitting the
multi-fragmented frame, the controller

MFC r207628,207635:
r207628:
Enable multi-descriptor transmisstion for fragmented mbufs. There
is no more need to defragment mbufs. After transmitting the
multi-fragmented frame, the controller updates only the first
descriptor of multi-descriptor transmission so it's driver's
responsibility to clear OWN bits of remaining descriptor of
multi-descriptor transmission. It seems the controller behaves much
like jme(4) controllers in descriptor handling.

r207635:
Free entire mbuf chain instead of the first mbuf.

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Implement TSO and TSO over VLAN. Increase number of allowed
fragmentation of mbuf chain to 32 from 16 because TSO can send 64KB
sized packet which in turn requires long list of mbuf chain. Due to
lac

Implement TSO and TSO over VLAN. Increase number of allowed
fragmentation of mbuf chain to 32 from 16 because TSO can send 64KB
sized packet which in turn requires long list of mbuf chain. Due to
lack of documentation, I'm not sure whether driver have to pull up
ethernet/IP/TCP header with options to make controller work but
driver have to parse TCP header to update pseudo TCP checksum
anyway. The controller expects pseudo TCP checksum computed by
upper stack and the checksum should follow the MS NDIS
specification to make TSO work.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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Merge svn+ssh://svn.freebsd.org/base/head@207793

MFC r207380:
Enable VLAN hardware tag insertion/stripping. Due to lack of SiS190
controller, I'm not sure whether this is also applicable to SiS190
so this feature is only activated on SiS191 c

MFC r207380:
Enable VLAN hardware tag insertion/stripping. Due to lack of SiS190
controller, I'm not sure whether this is also applicable to SiS190
so this feature is only activated on SiS191 controller.
In theory, controller reinitialization is not needed when VLAN tag
configuration is changed, but xclin said controller was not stable
whenever toggling VLAN tag bit. To address that, sge(4)
reinitialize controller for VLAN configuration which seems to work
as expected. VLAN tag information for TX/RX descriptor and
configure bit of RxMacControl register was found by xclin.

Submitted by: xclin <xclin <> cs dot nctu dot edu dot tw > (initial version)
Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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MFC r207379:
Enable FCS stripping and padding 10 bytes bit of RX MAC control
register. Due to lack of SiS190 controller, I'm not sure whether
this is also applicable to SiS190 so this feature i

MFC r207379:
Enable FCS stripping and padding 10 bytes bit of RX MAC control
register. Due to lack of SiS190 controller, I'm not sure whether
this is also applicable to SiS190 so this feature is only activated
on SiS191 controller.
The controller can pad 10 bytes before DMAing a received frame to
RX buffer and received bytes include the padded bytes. This padding
is very useful on strict-alignment architectures because driver
does not have to copy received frame to align IP header on 4 bytes
boundary. It also gives better RX performance on non-strict
alignment architectures. Special thanks to xclin to give me
valuable register information. Without his enthusiastic trial and
errors this wouldn't be even possible.

While I'm here tighten validity check of received frame. Controller
clears RDS_CRCOK bit when it received bad CRC frames. xclin found
that using loop back testing.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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MFC r207375-207377.
r207375:
Preserve unknown bits of RX MAC control register when driver
programs RX filter configuration. It seems RX MAC control register
is one of key registers to get vario

MFC r207375-207377.
r207375:
Preserve unknown bits of RX MAC control register when driver
programs RX filter configuration. It seems RX MAC control register
is one of key registers to get various offloading features as well
as performance. Blindly clearing unrelated bits can result in
unexpected results.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

r207376:
Remove wrong link state chage.

r207377:
Explicitly marks SiS190 to differentiate it from SiS191.

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Final update to current version of head in preparation for reintegration.

Enable multi-descriptor transmisstion for fragmented mbufs. There
is no more need to defragment mbufs. After transmitting the
multi-fragmented frame, the controller updates only the first
descriptor

Enable multi-descriptor transmisstion for fragmented mbufs. There
is no more need to defragment mbufs. After transmitting the
multi-fragmented frame, the controller updates only the first
descriptor of multi-descriptor transmission so it's driver's
responsibility to clear OWN bits of remaining descriptor of
multi-descriptor transmission. It seems the controller behaves much
like jme(4) controllers in descriptor handling.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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Enable VLAN hardware tag insertion/stripping. Due to lack of SiS190
controller, I'm not sure whether this is also applicable to SiS190
so this feature is only activated on SiS191 controller.
In theor

Enable VLAN hardware tag insertion/stripping. Due to lack of SiS190
controller, I'm not sure whether this is also applicable to SiS190
so this feature is only activated on SiS191 controller.
In theory, controller reinitialization is not needed when VLAN tag
configuration is changed, but xclin said controller was not stable
whenever toggling VLAN tag bit. To address that, sge(4)
reinitialize controller for VLAN configuration which seems to work
as expected. VLAN tag information for TX/RX descriptor and
configure bit of RxMacControl register was found by xclin.

Submitted by: xclin <xclin <> cs dot nctu dot edu dot tw > (initial version)
Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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Enable FCS stripping and padding 10 bytes bit of RX MAC control
register. Due to lack of SiS190 controller, I'm not sure whether
this is also applicable to SiS190 so this feature is only activated
on

Enable FCS stripping and padding 10 bytes bit of RX MAC control
register. Due to lack of SiS190 controller, I'm not sure whether
this is also applicable to SiS190 so this feature is only activated
on SiS191 controller.
The controller can pad 10 bytes before DMAing a received frame to
RX buffer and received bytes include the padded bytes. This padding
is very useful on strict-alignment architectures because driver
does not have to copy received frame to align IP header on 4 bytes
boundary. It also gives better RX performance on non-strict
alignment architectures. Special thanks to xclin to give me
valuable register information. Without his enthusiastic trial and
errors this wouldn't be even possible.

While I'm here tighten validity check of received frame. Controller
clears RDS_CRCOK bit when it received bad CRC frames. xclin found
that using loop back testing.

Tested by: xclin <xclin <> cs dot nctu dot edu dot tw >

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Explicitly marks SiS190 to differentiate it from SiS191.

Update to current version of head.

MFC r206625:
Add driver for Silicon Integrated Systems SiS190/191 Fast/Gigabit Ethernet.
This driver was written by Alexander Pohoyda and greatly enhanced
by Nikolay Denev. I don't have these h

MFC r206625:
Add driver for Silicon Integrated Systems SiS190/191 Fast/Gigabit Ethernet.
This driver was written by Alexander Pohoyda and greatly enhanced
by Nikolay Denev. I don't have these hardwares but this driver was
tested by Nikolay Denev and xclin.

Because SiS didn't release data sheet for this controller, programming
information came from Linux driver and OpenSolaris. Unlike other open
source driver for SiS190/191, sge(4) takes full advantage of TX/RX
checksum offloading and does not require additional copy operation in
RX handler.
The controller seems to have advanced offloading features like VLAN
hardware tag insertion/stripping, TCP segmentation offload(TSO) as
well as jumbo frame support but these features are not available
yet. Special thanks to xclin <xclin<> cs dot nctu dot edu dot tw>
who sent fix for receiving VLAN oversized frames.

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