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/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dnvreg.h29 #define NV_PMC_OFFSET 0x00000000
30 #define NV_PMC_SIZE 0x00001000
32 #define NV_PBUS_OFFSET 0x00001000
33 #define NV_PBUS_SIZE 0x00001000
35 #define NV_PFIFO_OFFSET 0x00002000
36 #define NV_PFIFO_SIZE 0x00002000
38 #define NV_HDIAG_OFFSET 0x00005000
39 #define NV_HDIAG_SIZE 0x00001000
41 #define NV_PRAM_OFFSET 0x00006000
42 #define NV_PRAM_SIZE 0x00001000
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
H A Dintel,keembay-pcie-ep.yaml57 reg = <0x37000000 0x00001000>,
58 <0x37100000 0x00001000>,
59 <0x37300000 0x00001000>,
60 <0x36000000 0x01000000>,
61 <0x37800000 0x00000200>;
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x67800000 0x00 0x00080000>,
12 <0x00 0x67e00000 0x00 0x0000c000>;
18 ti,sci-proc-ids = <0x33 0xff>;
24 reg = <0x00 0x02920000 0x00 0x1000>,
25 <0x00 0x02927000 0x00 0x400>,
26 <0x00 0x0e000000 0x00 0x00800000>,
27 <0x44 0x00000000 0x00 0x00001000>;
28 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
29 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
37 clocks = <&k3_clks 334 0>;
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
H A Dsmsc95xx.h12 #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) /* Data Start Offset */
13 #define TX_CMD_A_FIRST_SEG_ (0x00002000) /* First Segment */
14 #define TX_CMD_A_LAST_SEG_ (0x00001000) /* Last Segment */
15 #define TX_CMD_A_BUF_SIZE_ (0x000007FF) /* Buffer Size */
17 #define TX_CMD_B_CSUM_ENABLE (0x00004000) /* TX Checksum Enable */
18 #define TX_CMD_B_ADD_CRC_DIS_ (0x00002000) /* Add CRC Disable */
19 #define TX_CMD_B_DIS_PADDING_ (0x00001000) /* Disable Frame Padding */
20 #define TX_CMD_B_FRAME_LENGTH_ (0x000007FF) /* Frame Length (bytes) */
23 #define RX_STS_FF_ (0x40000000) /* Filter Fail */
24 #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */
[all …]
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4460.dtsi12 cpu0: cpu@0 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
39 #thermal-sensor-cells = <0>;
45 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
46 <0x4A002268 0x4>;
52 1025000 0 0 0 0 0
53 1200000 0 0 0 0 0
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/linux/arch/powerpc/include/asm/
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/linux/Documentation/devicetree/bindings/pmem/
H A Dpmem-region.txt48 * 0x5000 to 0x5fff that is backed by non-volatile memory.
52 reg = <0x00005000 0x00001000>;
61 reg = < 0x00006000 0x00001000
62 0x00008000 0x00001000 >;
/linux/drivers/net/ethernet/renesas/
H A Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dmc.h18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
19 #define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
20 #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
21 #define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
23 #define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
24 #define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
25 #define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
26 #define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
27 #define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgk110.c39 { 0x020520, 0xfffffffc }, in gk110_pmu_pgob()
40 { 0x020524, 0xfffffffe }, in gk110_pmu_pgob()
41 { 0x020524, 0xfffffffc }, in gk110_pmu_pgob()
42 { 0x020524, 0xfffffff8 }, in gk110_pmu_pgob()
43 { 0x020524, 0xffffffe0 }, in gk110_pmu_pgob()
44 { 0x020530, 0xfffffffe }, in gk110_pmu_pgob()
45 { 0x02052c, 0xfffffffa }, in gk110_pmu_pgob()
46 { 0x02052c, 0xfffffff0 }, in gk110_pmu_pgob()
47 { 0x02052c, 0xffffffc0 }, in gk110_pmu_pgob()
48 { 0x02052c, 0xffffff00 }, in gk110_pmu_pgob()
[all …]
H A Dgk104.c36 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
37 nvkm_wr32(device, 0x00c808, 0x00000000); in magic_()
38 nvkm_wr32(device, 0x00c800, ctrl); in magic_()
40 if (nvkm_rd32(device, 0x00c800) & 0x40000000) { in magic_()
42 nvkm_wr32(device, 0x00c804, 0x00000000); in magic_()
46 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
52 magic_(device, 0x8000a41f | ctrl, 6); in magic()
53 magic_(device, 0x80000421 | ctrl, 1); in magic()
61 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) in gk104_pmu_pgob()
64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob()
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex_n6000.dts26 reg = <0 0x80000000 0 0>;
29 soc@0 {
32 reg = <0x80000000 0x60000000>,
33 <0xf9000000 0x00100000>;
37 ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
39 dma-controller@0 {
41 reg = <0x00000000 0x00000000 0x00001000>;
/linux/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,hps-copy-engine.yaml39 reg = <0x80000000 0x60000000>,
40 <0xf9000000 0x00100000>;
44 ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
46 dma-controller@0 {
48 reg = <0x00000000 0x00000000 0x00001000>;
/linux/Documentation/devicetree/bindings/
H A Dresource-names.txt27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
28 <1 0 0x49000000 0x00001000>; /* L3 path */
31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
49 reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
50 <0x4a064c00 0x200>;
/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dnv17.c28 { 0x00001000, NVKM_ENGINE_GR },
29 { 0x00000100, NVKM_ENGINE_FIFO },
30 { 0x00000002, NVKM_ENGINE_MPEG },
36 { NVKM_ENGINE_DISP , 0, 0, 0x03010000, true },
37 { NVKM_ENGINE_GR , 0, 0, 0x00001000, true },
38 { NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
39 { NVKM_ENGINE_MPEG , 0, 0, 0x00000001, true },
40 { NVKM_SUBDEV_BUS , 0, 0, 0x10000000, true },
41 { NVKM_SUBDEV_TIMER, 0, 0, 0x00100000, true },
/linux/drivers/media/platform/imagination/
H A De5010-mmu-regs.h14 #define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)
18 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)
19 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)
21 #define MMU_MMU_TILE_CFG_OFFSET (0x0040)
25 #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)
28 #define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)
31 #define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)
32 #define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)
34 #define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)
38 #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFFF)
[all …]

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