1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2adfc5217SJeff Kirsher /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 3adfc5217SJeff Kirsher * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 4adfc5217SJeff Kirsher * 5adfc5217SJeff Kirsher * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 6adfc5217SJeff Kirsher * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 7adfc5217SJeff Kirsher * Copyright (C) 2004 Sun Microsystems Inc. 85a8bae97SSiva Reddy Kallam * Copyright (C) 2007-2016 Broadcom Corporation. 95a8bae97SSiva Reddy Kallam * Copyright (C) 2016-2017 Broadcom Limited. 100f2605fbSSiva Reddy Kallam * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" 110f2605fbSSiva Reddy Kallam * refers to Broadcom Inc. and/or its subsidiaries. 12adfc5217SJeff Kirsher */ 13adfc5217SJeff Kirsher 14adfc5217SJeff Kirsher #ifndef _T3_H 15adfc5217SJeff Kirsher #define _T3_H 16adfc5217SJeff Kirsher 17adfc5217SJeff Kirsher #define TG3_64BIT_REG_HIGH 0x00UL 18adfc5217SJeff Kirsher #define TG3_64BIT_REG_LOW 0x04UL 19adfc5217SJeff Kirsher 20adfc5217SJeff Kirsher /* Descriptor block info. */ 21adfc5217SJeff Kirsher #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 22adfc5217SJeff Kirsher #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 23adfc5217SJeff Kirsher #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 24adfc5217SJeff Kirsher #define BDINFO_FLAGS_DISABLED 0x00000002 25adfc5217SJeff Kirsher #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 26adfc5217SJeff Kirsher #define BDINFO_FLAGS_MAXLEN_SHIFT 16 27adfc5217SJeff Kirsher #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 28adfc5217SJeff Kirsher #define TG3_BDINFO_SIZE 0x10UL 29adfc5217SJeff Kirsher 30adfc5217SJeff Kirsher #define TG3_RX_STD_MAX_SIZE_5700 512 31adfc5217SJeff Kirsher #define TG3_RX_STD_MAX_SIZE_5717 2048 32adfc5217SJeff Kirsher #define TG3_RX_JMB_MAX_SIZE_5700 256 33adfc5217SJeff Kirsher #define TG3_RX_JMB_MAX_SIZE_5717 1024 34adfc5217SJeff Kirsher #define TG3_RX_RET_MAX_SIZE_5700 1024 35adfc5217SJeff Kirsher #define TG3_RX_RET_MAX_SIZE_5705 512 36adfc5217SJeff Kirsher #define TG3_RX_RET_MAX_SIZE_5717 4096 37adfc5217SJeff Kirsher 38bcebcc46SMatt Carlson #define TG3_RSS_INDIR_TBL_SIZE 128 39bcebcc46SMatt Carlson 40adfc5217SJeff Kirsher /* First 256 bytes are a mirror of PCI config space. */ 41adfc5217SJeff Kirsher #define TG3PCI_VENDOR 0x00000000 42adfc5217SJeff Kirsher #define TG3PCI_VENDOR_BROADCOM 0x14e4 43adfc5217SJeff Kirsher #define TG3PCI_DEVICE 0x00000002 44adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 45adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 46adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 47adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 48adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 49adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 50adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57780 0x1692 513d567e0eSNithin Nayak Sujir #define TG3PCI_DEVICE_TIGON3_5787M 0x1693 52adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57760 0x1690 53adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57790 0x1694 54adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57788 0x1691 55adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 56adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 57adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5717 0x1655 5879d49695SMichael Chan #define TG3PCI_DEVICE_TIGON3_5717_C 0x1665 59adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5718 0x1656 60adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57781 0x16b1 61adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57785 0x16b5 62adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57761 0x16b0 63adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57765 0x16b4 64adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57791 0x16b2 65adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_57795 0x16b6 66adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5719 0x1657 67adfc5217SJeff Kirsher #define TG3PCI_DEVICE_TIGON3_5720 0x165f 6855086ad9SMatt Carlson #define TG3PCI_DEVICE_TIGON3_57762 0x1682 6955086ad9SMatt Carlson #define TG3PCI_DEVICE_TIGON3_57766 0x1686 7055086ad9SMatt Carlson #define TG3PCI_DEVICE_TIGON3_57786 0x16b3 7155086ad9SMatt Carlson #define TG3PCI_DEVICE_TIGON3_57782 0x16b7 72c65a17f4SMichael Chan #define TG3PCI_DEVICE_TIGON3_5762 0x1687 73c65a17f4SMichael Chan #define TG3PCI_DEVICE_TIGON3_5725 0x1643 74c65a17f4SMichael Chan #define TG3PCI_DEVICE_TIGON3_5727 0x16f3 7568273712SNithin Sujir #define TG3PCI_DEVICE_TIGON3_57764 0x1642 7668273712SNithin Sujir #define TG3PCI_DEVICE_TIGON3_57767 0x1683 7768273712SNithin Sujir #define TG3PCI_DEVICE_TIGON3_57787 0x1641 78adfc5217SJeff Kirsher /* 0x04 --> 0x2c unused */ 79adfc5217SJeff Kirsher #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 80adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 81adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 82adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 83adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 84adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 85adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 86adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 87adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 88adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 89adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 90adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 91adfc5217SJeff Kirsher #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 92adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 93adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 94adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 95adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 96adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 97adfc5217SJeff Kirsher #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 98adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 99adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 100adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 101adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 1024419bb1cSSiva Reddy Kallam #define TG3PCI_SUBDEVICE_ID_DELL_5762 0x07f0 103adfc5217SJeff Kirsher #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 104adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 105adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 106adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 107adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 108adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 109adfc5217SJeff Kirsher #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 110adfc5217SJeff Kirsher #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 1113d567e0eSNithin Nayak Sujir #define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601 1123d567e0eSNithin Nayak Sujir #define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612 1133d567e0eSNithin Nayak Sujir #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056 1143d567e0eSNithin Nayak Sujir 115adfc5217SJeff Kirsher /* 0x30 --> 0x64 unused */ 116adfc5217SJeff Kirsher #define TG3PCI_MSI_DATA 0x00000064 117adfc5217SJeff Kirsher /* 0x66 --> 0x68 unused */ 118adfc5217SJeff Kirsher #define TG3PCI_MISC_HOST_CTRL 0x00000068 119adfc5217SJeff Kirsher #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 120adfc5217SJeff Kirsher #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 121adfc5217SJeff Kirsher #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 122adfc5217SJeff Kirsher #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 123adfc5217SJeff Kirsher #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 124adfc5217SJeff Kirsher #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 125adfc5217SJeff Kirsher #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 126adfc5217SJeff Kirsher #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 127adfc5217SJeff Kirsher #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 128adfc5217SJeff Kirsher #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 129adfc5217SJeff Kirsher #define MISC_HOST_CTRL_CHIPREV 0xffff0000 130adfc5217SJeff Kirsher #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 131717ff727SJoe Perches 132adfc5217SJeff Kirsher #define CHIPREV_ID_5700_A0 0x7000 133adfc5217SJeff Kirsher #define CHIPREV_ID_5700_A1 0x7001 134adfc5217SJeff Kirsher #define CHIPREV_ID_5700_B0 0x7100 135adfc5217SJeff Kirsher #define CHIPREV_ID_5700_B1 0x7101 136adfc5217SJeff Kirsher #define CHIPREV_ID_5700_B3 0x7102 137adfc5217SJeff Kirsher #define CHIPREV_ID_5700_ALTIMA 0x7104 138adfc5217SJeff Kirsher #define CHIPREV_ID_5700_C0 0x7200 139adfc5217SJeff Kirsher #define CHIPREV_ID_5701_A0 0x0000 140adfc5217SJeff Kirsher #define CHIPREV_ID_5701_B0 0x0100 141adfc5217SJeff Kirsher #define CHIPREV_ID_5701_B2 0x0102 142adfc5217SJeff Kirsher #define CHIPREV_ID_5701_B5 0x0105 143adfc5217SJeff Kirsher #define CHIPREV_ID_5703_A0 0x1000 144adfc5217SJeff Kirsher #define CHIPREV_ID_5703_A1 0x1001 145adfc5217SJeff Kirsher #define CHIPREV_ID_5703_A2 0x1002 146adfc5217SJeff Kirsher #define CHIPREV_ID_5703_A3 0x1003 147adfc5217SJeff Kirsher #define CHIPREV_ID_5704_A0 0x2000 148adfc5217SJeff Kirsher #define CHIPREV_ID_5704_A1 0x2001 149adfc5217SJeff Kirsher #define CHIPREV_ID_5704_A2 0x2002 150adfc5217SJeff Kirsher #define CHIPREV_ID_5704_A3 0x2003 151adfc5217SJeff Kirsher #define CHIPREV_ID_5705_A0 0x3000 152adfc5217SJeff Kirsher #define CHIPREV_ID_5705_A1 0x3001 153adfc5217SJeff Kirsher #define CHIPREV_ID_5705_A2 0x3002 154adfc5217SJeff Kirsher #define CHIPREV_ID_5705_A3 0x3003 155adfc5217SJeff Kirsher #define CHIPREV_ID_5750_A0 0x4000 156adfc5217SJeff Kirsher #define CHIPREV_ID_5750_A1 0x4001 157adfc5217SJeff Kirsher #define CHIPREV_ID_5750_A3 0x4003 158adfc5217SJeff Kirsher #define CHIPREV_ID_5750_C2 0x4202 159adfc5217SJeff Kirsher #define CHIPREV_ID_5752_A0_HW 0x5000 160adfc5217SJeff Kirsher #define CHIPREV_ID_5752_A0 0x6000 161adfc5217SJeff Kirsher #define CHIPREV_ID_5752_A1 0x6001 162adfc5217SJeff Kirsher #define CHIPREV_ID_5714_A2 0x9002 163adfc5217SJeff Kirsher #define CHIPREV_ID_5906_A1 0xc001 164adfc5217SJeff Kirsher #define CHIPREV_ID_57780_A0 0x57780000 165adfc5217SJeff Kirsher #define CHIPREV_ID_57780_A1 0x57780001 166adfc5217SJeff Kirsher #define CHIPREV_ID_5717_A0 0x05717000 16779d49695SMichael Chan #define CHIPREV_ID_5717_C0 0x05717200 168adfc5217SJeff Kirsher #define CHIPREV_ID_57765_A0 0x57785000 169adfc5217SJeff Kirsher #define CHIPREV_ID_5719_A0 0x05719000 170adfc5217SJeff Kirsher #define CHIPREV_ID_5720_A0 0x05720000 171c65a17f4SMichael Chan #define CHIPREV_ID_5762_A0 0x05762000 1724153577aSJoe Perches 173adfc5217SJeff Kirsher #define ASIC_REV_5700 0x07 174adfc5217SJeff Kirsher #define ASIC_REV_5701 0x00 175adfc5217SJeff Kirsher #define ASIC_REV_5703 0x01 176adfc5217SJeff Kirsher #define ASIC_REV_5704 0x02 177adfc5217SJeff Kirsher #define ASIC_REV_5705 0x03 178adfc5217SJeff Kirsher #define ASIC_REV_5750 0x04 179adfc5217SJeff Kirsher #define ASIC_REV_5752 0x06 180adfc5217SJeff Kirsher #define ASIC_REV_5780 0x08 181adfc5217SJeff Kirsher #define ASIC_REV_5714 0x09 182adfc5217SJeff Kirsher #define ASIC_REV_5755 0x0a 183adfc5217SJeff Kirsher #define ASIC_REV_5787 0x0b 184adfc5217SJeff Kirsher #define ASIC_REV_5906 0x0c 185adfc5217SJeff Kirsher #define ASIC_REV_USE_PROD_ID_REG 0x0f 186adfc5217SJeff Kirsher #define ASIC_REV_5784 0x5784 187adfc5217SJeff Kirsher #define ASIC_REV_5761 0x5761 188adfc5217SJeff Kirsher #define ASIC_REV_5785 0x5785 189adfc5217SJeff Kirsher #define ASIC_REV_57780 0x57780 190adfc5217SJeff Kirsher #define ASIC_REV_5717 0x5717 191adfc5217SJeff Kirsher #define ASIC_REV_57765 0x57785 192adfc5217SJeff Kirsher #define ASIC_REV_5719 0x5719 193adfc5217SJeff Kirsher #define ASIC_REV_5720 0x5720 19455086ad9SMatt Carlson #define ASIC_REV_57766 0x57766 195c65a17f4SMichael Chan #define ASIC_REV_5762 0x5762 196adfc5217SJeff Kirsher #define CHIPREV_5700_AX 0x70 197adfc5217SJeff Kirsher #define CHIPREV_5700_BX 0x71 198adfc5217SJeff Kirsher #define CHIPREV_5700_CX 0x72 199adfc5217SJeff Kirsher #define CHIPREV_5701_AX 0x00 200adfc5217SJeff Kirsher #define CHIPREV_5703_AX 0x10 201adfc5217SJeff Kirsher #define CHIPREV_5704_AX 0x20 202adfc5217SJeff Kirsher #define CHIPREV_5704_BX 0x21 203adfc5217SJeff Kirsher #define CHIPREV_5750_AX 0x40 204adfc5217SJeff Kirsher #define CHIPREV_5750_BX 0x41 205adfc5217SJeff Kirsher #define CHIPREV_5784_AX 0x57840 206adfc5217SJeff Kirsher #define CHIPREV_5761_AX 0x57610 207adfc5217SJeff Kirsher #define CHIPREV_57765_AX 0x577650 208adfc5217SJeff Kirsher #define METAL_REV_A0 0x00 209adfc5217SJeff Kirsher #define METAL_REV_A1 0x01 210adfc5217SJeff Kirsher #define METAL_REV_B0 0x00 211adfc5217SJeff Kirsher #define METAL_REV_B1 0x01 212adfc5217SJeff Kirsher #define METAL_REV_B2 0x02 213adfc5217SJeff Kirsher #define TG3PCI_DMA_RW_CTRL 0x0000006c 214adfc5217SJeff Kirsher #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 215adfc5217SJeff Kirsher #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 216adfc5217SJeff Kirsher #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 217adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 218adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 219adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 220adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 221adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 222adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 223adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 224adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 225adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 226adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 227adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 228adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 229adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 230adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 231adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 232adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 233adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 234adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 235adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 236adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 237adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 238adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 239adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 240adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 241adfc5217SJeff Kirsher #define DMA_RWCTRL_ONE_DMA 0x00004000 242adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_WATER 0x00070000 243adfc5217SJeff Kirsher #define DMA_RWCTRL_READ_WATER_SHIFT 16 244adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_WATER 0x00380000 245adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 246adfc5217SJeff Kirsher #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 247adfc5217SJeff Kirsher #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 248adfc5217SJeff Kirsher #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 249adfc5217SJeff Kirsher #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 250adfc5217SJeff Kirsher #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 251adfc5217SJeff Kirsher #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 252adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 253adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 254adfc5217SJeff Kirsher #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 255adfc5217SJeff Kirsher #define TG3PCI_PCISTATE 0x00000070 256adfc5217SJeff Kirsher #define PCISTATE_FORCE_RESET 0x00000001 257adfc5217SJeff Kirsher #define PCISTATE_INT_NOT_ACTIVE 0x00000002 258adfc5217SJeff Kirsher #define PCISTATE_CONV_PCI_MODE 0x00000004 259adfc5217SJeff Kirsher #define PCISTATE_BUS_SPEED_HIGH 0x00000008 260adfc5217SJeff Kirsher #define PCISTATE_BUS_32BIT 0x00000010 261adfc5217SJeff Kirsher #define PCISTATE_ROM_ENABLE 0x00000020 262adfc5217SJeff Kirsher #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 263adfc5217SJeff Kirsher #define PCISTATE_FLAT_VIEW 0x00000100 264adfc5217SJeff Kirsher #define PCISTATE_RETRY_SAME_DMA 0x00002000 265adfc5217SJeff Kirsher #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 266adfc5217SJeff Kirsher #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 267adfc5217SJeff Kirsher #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 268adfc5217SJeff Kirsher #define TG3PCI_CLOCK_CTRL 0x00000074 269adfc5217SJeff Kirsher #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 270adfc5217SJeff Kirsher #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 271adfc5217SJeff Kirsher #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 272adfc5217SJeff Kirsher #define CLOCK_CTRL_ALTCLK 0x00001000 273adfc5217SJeff Kirsher #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 274adfc5217SJeff Kirsher #define CLOCK_CTRL_44MHZ_CORE 0x00040000 275adfc5217SJeff Kirsher #define CLOCK_CTRL_625_CORE 0x00100000 276adfc5217SJeff Kirsher #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 277adfc5217SJeff Kirsher #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 278adfc5217SJeff Kirsher #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 279adfc5217SJeff Kirsher #define TG3PCI_REG_BASE_ADDR 0x00000078 280adfc5217SJeff Kirsher #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 281adfc5217SJeff Kirsher #define TG3PCI_REG_DATA 0x00000080 282adfc5217SJeff Kirsher #define TG3PCI_MEM_WIN_DATA 0x00000084 283adfc5217SJeff Kirsher #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 284adfc5217SJeff Kirsher /* 0x94 --> 0x98 unused */ 285adfc5217SJeff Kirsher #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 286adfc5217SJeff Kirsher #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 287adfc5217SJeff Kirsher /* 0xa8 --> 0xb8 unused */ 2884419bb1cSSiva Reddy Kallam #define TG3PCI_DEV_STATUS_CTRL 0x000000b4 2894419bb1cSSiva Reddy Kallam #define MAX_READ_REQ_SIZE_2048 0x00004000 2904419bb1cSSiva Reddy Kallam #define MAX_READ_REQ_MASK 0x00007000 291adfc5217SJeff Kirsher #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 292adfc5217SJeff Kirsher #define DUAL_MAC_CTRL_CH_MASK 0x00000003 293adfc5217SJeff Kirsher #define DUAL_MAC_CTRL_ID 0x00000004 294adfc5217SJeff Kirsher #define TG3PCI_PRODID_ASICREV 0x000000bc 295adfc5217SJeff Kirsher #define PROD_ID_ASIC_REV_MASK 0x0fffffff 296adfc5217SJeff Kirsher /* 0xc0 --> 0xf4 unused */ 297adfc5217SJeff Kirsher 298adfc5217SJeff Kirsher #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 299adfc5217SJeff Kirsher #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 300adfc5217SJeff Kirsher /* 0xf8 --> 0x200 unused */ 301adfc5217SJeff Kirsher 302adfc5217SJeff Kirsher #define TG3_CORR_ERR_STAT 0x00000110 303adfc5217SJeff Kirsher #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 304adfc5217SJeff Kirsher /* 0x114 --> 0x200 unused */ 305adfc5217SJeff Kirsher 306adfc5217SJeff Kirsher /* Mailbox registers */ 307adfc5217SJeff Kirsher #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 308adfc5217SJeff Kirsher #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 309adfc5217SJeff Kirsher #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 310adfc5217SJeff Kirsher #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 311adfc5217SJeff Kirsher #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 312adfc5217SJeff Kirsher #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 313adfc5217SJeff Kirsher #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 314adfc5217SJeff Kirsher #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 315adfc5217SJeff Kirsher #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 316adfc5217SJeff Kirsher #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 317adfc5217SJeff Kirsher #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 318adfc5217SJeff Kirsher #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 319adfc5217SJeff Kirsher #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 320adfc5217SJeff Kirsher #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 321adfc5217SJeff Kirsher #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 322adfc5217SJeff Kirsher TG3_64BIT_REG_LOW) 323adfc5217SJeff Kirsher #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 324adfc5217SJeff Kirsher #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 325adfc5217SJeff Kirsher TG3_64BIT_REG_LOW) 326adfc5217SJeff Kirsher #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 327adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 328adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 329adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 330adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 331adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 332adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 333adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 334adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 335adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 336adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 337adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 338adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 339adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 340adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 341adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 342adfc5217SJeff Kirsher #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 343adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 344adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 345adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 346adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 347adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 348adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 349adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 350adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 351adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 352adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 353adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 354adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 355adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 356adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 357adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 358adfc5217SJeff Kirsher #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 359adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 360adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 361adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 362adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 363adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 364adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 365adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 366adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 367adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 368adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 369adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 370adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 371adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 372adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 373adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 374adfc5217SJeff Kirsher #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 375adfc5217SJeff Kirsher 376adfc5217SJeff Kirsher /* MAC control registers */ 377adfc5217SJeff Kirsher #define MAC_MODE 0x00000400 378adfc5217SJeff Kirsher #define MAC_MODE_RESET 0x00000001 379adfc5217SJeff Kirsher #define MAC_MODE_HALF_DUPLEX 0x00000002 380adfc5217SJeff Kirsher #define MAC_MODE_PORT_MODE_MASK 0x0000000c 381adfc5217SJeff Kirsher #define MAC_MODE_PORT_MODE_TBI 0x0000000c 382adfc5217SJeff Kirsher #define MAC_MODE_PORT_MODE_GMII 0x00000008 383adfc5217SJeff Kirsher #define MAC_MODE_PORT_MODE_MII 0x00000004 384adfc5217SJeff Kirsher #define MAC_MODE_PORT_MODE_NONE 0x00000000 385adfc5217SJeff Kirsher #define MAC_MODE_PORT_INT_LPBACK 0x00000010 386adfc5217SJeff Kirsher #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 387adfc5217SJeff Kirsher #define MAC_MODE_TX_BURSTING 0x00000100 388adfc5217SJeff Kirsher #define MAC_MODE_MAX_DEFER 0x00000200 389adfc5217SJeff Kirsher #define MAC_MODE_LINK_POLARITY 0x00000400 390adfc5217SJeff Kirsher #define MAC_MODE_RXSTAT_ENABLE 0x00000800 391adfc5217SJeff Kirsher #define MAC_MODE_RXSTAT_CLEAR 0x00001000 392adfc5217SJeff Kirsher #define MAC_MODE_RXSTAT_FLUSH 0x00002000 393adfc5217SJeff Kirsher #define MAC_MODE_TXSTAT_ENABLE 0x00004000 394adfc5217SJeff Kirsher #define MAC_MODE_TXSTAT_CLEAR 0x00008000 395adfc5217SJeff Kirsher #define MAC_MODE_TXSTAT_FLUSH 0x00010000 396adfc5217SJeff Kirsher #define MAC_MODE_SEND_CONFIGS 0x00020000 397adfc5217SJeff Kirsher #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 398adfc5217SJeff Kirsher #define MAC_MODE_ACPI_ENABLE 0x00080000 399adfc5217SJeff Kirsher #define MAC_MODE_MIP_ENABLE 0x00100000 400adfc5217SJeff Kirsher #define MAC_MODE_TDE_ENABLE 0x00200000 401adfc5217SJeff Kirsher #define MAC_MODE_RDE_ENABLE 0x00400000 402adfc5217SJeff Kirsher #define MAC_MODE_FHDE_ENABLE 0x00800000 403adfc5217SJeff Kirsher #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 404adfc5217SJeff Kirsher #define MAC_MODE_APE_RX_EN 0x08000000 405adfc5217SJeff Kirsher #define MAC_MODE_APE_TX_EN 0x10000000 406adfc5217SJeff Kirsher #define MAC_STATUS 0x00000404 407adfc5217SJeff Kirsher #define MAC_STATUS_PCS_SYNCED 0x00000001 408adfc5217SJeff Kirsher #define MAC_STATUS_SIGNAL_DET 0x00000002 409adfc5217SJeff Kirsher #define MAC_STATUS_RCVD_CFG 0x00000004 410adfc5217SJeff Kirsher #define MAC_STATUS_CFG_CHANGED 0x00000008 411adfc5217SJeff Kirsher #define MAC_STATUS_SYNC_CHANGED 0x00000010 412adfc5217SJeff Kirsher #define MAC_STATUS_PORT_DEC_ERR 0x00000400 413adfc5217SJeff Kirsher #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 414adfc5217SJeff Kirsher #define MAC_STATUS_MI_COMPLETION 0x00400000 415adfc5217SJeff Kirsher #define MAC_STATUS_MI_INTERRUPT 0x00800000 416adfc5217SJeff Kirsher #define MAC_STATUS_AP_ERROR 0x01000000 417adfc5217SJeff Kirsher #define MAC_STATUS_ODI_ERROR 0x02000000 418adfc5217SJeff Kirsher #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 419adfc5217SJeff Kirsher #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 420adfc5217SJeff Kirsher #define MAC_EVENT 0x00000408 421adfc5217SJeff Kirsher #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 422adfc5217SJeff Kirsher #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 423adfc5217SJeff Kirsher #define MAC_EVENT_MI_COMPLETION 0x00400000 424adfc5217SJeff Kirsher #define MAC_EVENT_MI_INTERRUPT 0x00800000 425adfc5217SJeff Kirsher #define MAC_EVENT_AP_ERROR 0x01000000 426adfc5217SJeff Kirsher #define MAC_EVENT_ODI_ERROR 0x02000000 427adfc5217SJeff Kirsher #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 428adfc5217SJeff Kirsher #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 429adfc5217SJeff Kirsher #define MAC_LED_CTRL 0x0000040c 430adfc5217SJeff Kirsher #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 431adfc5217SJeff Kirsher #define LED_CTRL_1000MBPS_ON 0x00000002 432adfc5217SJeff Kirsher #define LED_CTRL_100MBPS_ON 0x00000004 433adfc5217SJeff Kirsher #define LED_CTRL_10MBPS_ON 0x00000008 434adfc5217SJeff Kirsher #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 435adfc5217SJeff Kirsher #define LED_CTRL_TRAFFIC_BLINK 0x00000020 436adfc5217SJeff Kirsher #define LED_CTRL_TRAFFIC_LED 0x00000040 437adfc5217SJeff Kirsher #define LED_CTRL_1000MBPS_STATUS 0x00000080 438adfc5217SJeff Kirsher #define LED_CTRL_100MBPS_STATUS 0x00000100 439adfc5217SJeff Kirsher #define LED_CTRL_10MBPS_STATUS 0x00000200 440adfc5217SJeff Kirsher #define LED_CTRL_TRAFFIC_STATUS 0x00000400 441adfc5217SJeff Kirsher #define LED_CTRL_MODE_MAC 0x00000000 442adfc5217SJeff Kirsher #define LED_CTRL_MODE_PHY_1 0x00000800 443adfc5217SJeff Kirsher #define LED_CTRL_MODE_PHY_2 0x00001000 444adfc5217SJeff Kirsher #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 445adfc5217SJeff Kirsher #define LED_CTRL_MODE_SHARED 0x00004000 446adfc5217SJeff Kirsher #define LED_CTRL_MODE_COMBO 0x00008000 447adfc5217SJeff Kirsher #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 448adfc5217SJeff Kirsher #define LED_CTRL_BLINK_RATE_SHIFT 19 449adfc5217SJeff Kirsher #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 450adfc5217SJeff Kirsher #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 451adfc5217SJeff Kirsher #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 452adfc5217SJeff Kirsher #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 453adfc5217SJeff Kirsher #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 454adfc5217SJeff Kirsher #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 455adfc5217SJeff Kirsher #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 456adfc5217SJeff Kirsher #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 457adfc5217SJeff Kirsher #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 458adfc5217SJeff Kirsher #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 459adfc5217SJeff Kirsher #define MAC_ACPI_MBUF_PTR 0x00000430 460adfc5217SJeff Kirsher #define MAC_ACPI_LEN_OFFSET 0x00000434 461adfc5217SJeff Kirsher #define ACPI_LENOFF_LEN_MASK 0x0000ffff 462adfc5217SJeff Kirsher #define ACPI_LENOFF_LEN_SHIFT 0 463adfc5217SJeff Kirsher #define ACPI_LENOFF_OFF_MASK 0x0fff0000 464adfc5217SJeff Kirsher #define ACPI_LENOFF_OFF_SHIFT 16 465adfc5217SJeff Kirsher #define MAC_TX_BACKOFF_SEED 0x00000438 466adfc5217SJeff Kirsher #define TX_BACKOFF_SEED_MASK 0x000003ff 467adfc5217SJeff Kirsher #define MAC_RX_MTU_SIZE 0x0000043c 468adfc5217SJeff Kirsher #define RX_MTU_SIZE_MASK 0x0000ffff 469adfc5217SJeff Kirsher #define MAC_PCS_TEST 0x00000440 470adfc5217SJeff Kirsher #define PCS_TEST_PATTERN_MASK 0x000fffff 471adfc5217SJeff Kirsher #define PCS_TEST_PATTERN_SHIFT 0 472adfc5217SJeff Kirsher #define PCS_TEST_ENABLE 0x00100000 473adfc5217SJeff Kirsher #define MAC_TX_AUTO_NEG 0x00000444 474adfc5217SJeff Kirsher #define TX_AUTO_NEG_MASK 0x0000ffff 475adfc5217SJeff Kirsher #define TX_AUTO_NEG_SHIFT 0 476adfc5217SJeff Kirsher #define MAC_RX_AUTO_NEG 0x00000448 477adfc5217SJeff Kirsher #define RX_AUTO_NEG_MASK 0x0000ffff 478adfc5217SJeff Kirsher #define RX_AUTO_NEG_SHIFT 0 479adfc5217SJeff Kirsher #define MAC_MI_COM 0x0000044c 480adfc5217SJeff Kirsher #define MI_COM_CMD_MASK 0x0c000000 481adfc5217SJeff Kirsher #define MI_COM_CMD_WRITE 0x04000000 482adfc5217SJeff Kirsher #define MI_COM_CMD_READ 0x08000000 483adfc5217SJeff Kirsher #define MI_COM_READ_FAILED 0x10000000 484adfc5217SJeff Kirsher #define MI_COM_START 0x20000000 485adfc5217SJeff Kirsher #define MI_COM_BUSY 0x20000000 486adfc5217SJeff Kirsher #define MI_COM_PHY_ADDR_MASK 0x03e00000 487adfc5217SJeff Kirsher #define MI_COM_PHY_ADDR_SHIFT 21 488adfc5217SJeff Kirsher #define MI_COM_REG_ADDR_MASK 0x001f0000 489adfc5217SJeff Kirsher #define MI_COM_REG_ADDR_SHIFT 16 490adfc5217SJeff Kirsher #define MI_COM_DATA_MASK 0x0000ffff 491adfc5217SJeff Kirsher #define MAC_MI_STAT 0x00000450 492adfc5217SJeff Kirsher #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 493adfc5217SJeff Kirsher #define MAC_MI_STAT_10MBPS_MODE 0x00000002 494adfc5217SJeff Kirsher #define MAC_MI_MODE 0x00000454 495adfc5217SJeff Kirsher #define MAC_MI_MODE_CLK_10MHZ 0x00000001 496adfc5217SJeff Kirsher #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 497adfc5217SJeff Kirsher #define MAC_MI_MODE_AUTO_POLL 0x00000010 498adfc5217SJeff Kirsher #define MAC_MI_MODE_500KHZ_CONST 0x00008000 499adfc5217SJeff Kirsher #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 500adfc5217SJeff Kirsher #define MAC_AUTO_POLL_STATUS 0x00000458 501adfc5217SJeff Kirsher #define MAC_AUTO_POLL_ERROR 0x00000001 502adfc5217SJeff Kirsher #define MAC_TX_MODE 0x0000045c 503adfc5217SJeff Kirsher #define TX_MODE_RESET 0x00000001 504adfc5217SJeff Kirsher #define TX_MODE_ENABLE 0x00000002 505adfc5217SJeff Kirsher #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 506adfc5217SJeff Kirsher #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 507adfc5217SJeff Kirsher #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 508adfc5217SJeff Kirsher #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 509adfc5217SJeff Kirsher #define TX_MODE_JMB_FRM_LEN 0x00400000 510adfc5217SJeff Kirsher #define TX_MODE_CNT_DN_MODE 0x00800000 511adfc5217SJeff Kirsher #define MAC_TX_STATUS 0x00000460 512adfc5217SJeff Kirsher #define TX_STATUS_XOFFED 0x00000001 513adfc5217SJeff Kirsher #define TX_STATUS_SENT_XOFF 0x00000002 514adfc5217SJeff Kirsher #define TX_STATUS_SENT_XON 0x00000004 515adfc5217SJeff Kirsher #define TX_STATUS_LINK_UP 0x00000008 516adfc5217SJeff Kirsher #define TX_STATUS_ODI_UNDERRUN 0x00000010 517adfc5217SJeff Kirsher #define TX_STATUS_ODI_OVERRUN 0x00000020 518adfc5217SJeff Kirsher #define MAC_TX_LENGTHS 0x00000464 519adfc5217SJeff Kirsher #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 520adfc5217SJeff Kirsher #define TX_LENGTHS_SLOT_TIME_SHIFT 0 521adfc5217SJeff Kirsher #define TX_LENGTHS_IPG_MASK 0x00000f00 522adfc5217SJeff Kirsher #define TX_LENGTHS_IPG_SHIFT 8 523adfc5217SJeff Kirsher #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 524adfc5217SJeff Kirsher #define TX_LENGTHS_IPG_CRS_SHIFT 12 525adfc5217SJeff Kirsher #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 526adfc5217SJeff Kirsher #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 527adfc5217SJeff Kirsher #define MAC_RX_MODE 0x00000468 528adfc5217SJeff Kirsher #define RX_MODE_RESET 0x00000001 529adfc5217SJeff Kirsher #define RX_MODE_ENABLE 0x00000002 530adfc5217SJeff Kirsher #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 531adfc5217SJeff Kirsher #define RX_MODE_KEEP_MAC_CTRL 0x00000008 532adfc5217SJeff Kirsher #define RX_MODE_KEEP_PAUSE 0x00000010 533adfc5217SJeff Kirsher #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 534adfc5217SJeff Kirsher #define RX_MODE_ACCEPT_RUNTS 0x00000040 535adfc5217SJeff Kirsher #define RX_MODE_LEN_CHECK 0x00000080 536adfc5217SJeff Kirsher #define RX_MODE_PROMISC 0x00000100 537adfc5217SJeff Kirsher #define RX_MODE_NO_CRC_CHECK 0x00000200 538adfc5217SJeff Kirsher #define RX_MODE_KEEP_VLAN_TAG 0x00000400 539adfc5217SJeff Kirsher #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 540adfc5217SJeff Kirsher #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 541adfc5217SJeff Kirsher #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 542adfc5217SJeff Kirsher #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 543adfc5217SJeff Kirsher #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 544adfc5217SJeff Kirsher #define RX_MODE_RSS_ENABLE 0x00800000 545adfc5217SJeff Kirsher #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 546378b72c8SNithin Sujir #define RX_MODE_IPV4_FRAG_FIX 0x02000000 547adfc5217SJeff Kirsher #define MAC_RX_STATUS 0x0000046c 548adfc5217SJeff Kirsher #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 549adfc5217SJeff Kirsher #define RX_STATUS_XOFF_RCVD 0x00000002 550adfc5217SJeff Kirsher #define RX_STATUS_XON_RCVD 0x00000004 551adfc5217SJeff Kirsher #define MAC_HASH_REG_0 0x00000470 552adfc5217SJeff Kirsher #define MAC_HASH_REG_1 0x00000474 553adfc5217SJeff Kirsher #define MAC_HASH_REG_2 0x00000478 554adfc5217SJeff Kirsher #define MAC_HASH_REG_3 0x0000047c 555adfc5217SJeff Kirsher #define MAC_RCV_RULE_0 0x00000480 556adfc5217SJeff Kirsher #define MAC_RCV_VALUE_0 0x00000484 557adfc5217SJeff Kirsher #define MAC_RCV_RULE_1 0x00000488 558adfc5217SJeff Kirsher #define MAC_RCV_VALUE_1 0x0000048c 559adfc5217SJeff Kirsher #define MAC_RCV_RULE_2 0x00000490 560adfc5217SJeff Kirsher #define MAC_RCV_VALUE_2 0x00000494 561adfc5217SJeff Kirsher #define MAC_RCV_RULE_3 0x00000498 562adfc5217SJeff Kirsher #define MAC_RCV_VALUE_3 0x0000049c 563adfc5217SJeff Kirsher #define MAC_RCV_RULE_4 0x000004a0 564adfc5217SJeff Kirsher #define MAC_RCV_VALUE_4 0x000004a4 565adfc5217SJeff Kirsher #define MAC_RCV_RULE_5 0x000004a8 566adfc5217SJeff Kirsher #define MAC_RCV_VALUE_5 0x000004ac 567adfc5217SJeff Kirsher #define MAC_RCV_RULE_6 0x000004b0 568adfc5217SJeff Kirsher #define MAC_RCV_VALUE_6 0x000004b4 569adfc5217SJeff Kirsher #define MAC_RCV_RULE_7 0x000004b8 570adfc5217SJeff Kirsher #define MAC_RCV_VALUE_7 0x000004bc 571adfc5217SJeff Kirsher #define MAC_RCV_RULE_8 0x000004c0 572adfc5217SJeff Kirsher #define MAC_RCV_VALUE_8 0x000004c4 573adfc5217SJeff Kirsher #define MAC_RCV_RULE_9 0x000004c8 574adfc5217SJeff Kirsher #define MAC_RCV_VALUE_9 0x000004cc 575adfc5217SJeff Kirsher #define MAC_RCV_RULE_10 0x000004d0 576adfc5217SJeff Kirsher #define MAC_RCV_VALUE_10 0x000004d4 577adfc5217SJeff Kirsher #define MAC_RCV_RULE_11 0x000004d8 578adfc5217SJeff Kirsher #define MAC_RCV_VALUE_11 0x000004dc 579adfc5217SJeff Kirsher #define MAC_RCV_RULE_12 0x000004e0 580adfc5217SJeff Kirsher #define MAC_RCV_VALUE_12 0x000004e4 581adfc5217SJeff Kirsher #define MAC_RCV_RULE_13 0x000004e8 582adfc5217SJeff Kirsher #define MAC_RCV_VALUE_13 0x000004ec 583adfc5217SJeff Kirsher #define MAC_RCV_RULE_14 0x000004f0 584adfc5217SJeff Kirsher #define MAC_RCV_VALUE_14 0x000004f4 585adfc5217SJeff Kirsher #define MAC_RCV_RULE_15 0x000004f8 586adfc5217SJeff Kirsher #define MAC_RCV_VALUE_15 0x000004fc 587adfc5217SJeff Kirsher #define RCV_RULE_DISABLE_MASK 0x7fffffff 588adfc5217SJeff Kirsher #define MAC_RCV_RULE_CFG 0x00000500 589adfc5217SJeff Kirsher #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 590adfc5217SJeff Kirsher #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 591adfc5217SJeff Kirsher /* 0x508 --> 0x520 unused */ 592adfc5217SJeff Kirsher #define MAC_HASHREGU_0 0x00000520 593adfc5217SJeff Kirsher #define MAC_HASHREGU_1 0x00000524 594adfc5217SJeff Kirsher #define MAC_HASHREGU_2 0x00000528 595adfc5217SJeff Kirsher #define MAC_HASHREGU_3 0x0000052c 596adfc5217SJeff Kirsher #define MAC_EXTADDR_0_HIGH 0x00000530 597adfc5217SJeff Kirsher #define MAC_EXTADDR_0_LOW 0x00000534 598adfc5217SJeff Kirsher #define MAC_EXTADDR_1_HIGH 0x00000538 599adfc5217SJeff Kirsher #define MAC_EXTADDR_1_LOW 0x0000053c 600adfc5217SJeff Kirsher #define MAC_EXTADDR_2_HIGH 0x00000540 601adfc5217SJeff Kirsher #define MAC_EXTADDR_2_LOW 0x00000544 602adfc5217SJeff Kirsher #define MAC_EXTADDR_3_HIGH 0x00000548 603adfc5217SJeff Kirsher #define MAC_EXTADDR_3_LOW 0x0000054c 604adfc5217SJeff Kirsher #define MAC_EXTADDR_4_HIGH 0x00000550 605adfc5217SJeff Kirsher #define MAC_EXTADDR_4_LOW 0x00000554 606adfc5217SJeff Kirsher #define MAC_EXTADDR_5_HIGH 0x00000558 607adfc5217SJeff Kirsher #define MAC_EXTADDR_5_LOW 0x0000055c 608adfc5217SJeff Kirsher #define MAC_EXTADDR_6_HIGH 0x00000560 609adfc5217SJeff Kirsher #define MAC_EXTADDR_6_LOW 0x00000564 610adfc5217SJeff Kirsher #define MAC_EXTADDR_7_HIGH 0x00000568 611adfc5217SJeff Kirsher #define MAC_EXTADDR_7_LOW 0x0000056c 612adfc5217SJeff Kirsher #define MAC_EXTADDR_8_HIGH 0x00000570 613adfc5217SJeff Kirsher #define MAC_EXTADDR_8_LOW 0x00000574 614adfc5217SJeff Kirsher #define MAC_EXTADDR_9_HIGH 0x00000578 615adfc5217SJeff Kirsher #define MAC_EXTADDR_9_LOW 0x0000057c 616adfc5217SJeff Kirsher #define MAC_EXTADDR_10_HIGH 0x00000580 617adfc5217SJeff Kirsher #define MAC_EXTADDR_10_LOW 0x00000584 618adfc5217SJeff Kirsher #define MAC_EXTADDR_11_HIGH 0x00000588 619adfc5217SJeff Kirsher #define MAC_EXTADDR_11_LOW 0x0000058c 620adfc5217SJeff Kirsher #define MAC_SERDES_CFG 0x00000590 621adfc5217SJeff Kirsher #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 622adfc5217SJeff Kirsher #define MAC_SERDES_STAT 0x00000594 623adfc5217SJeff Kirsher /* 0x598 --> 0x5a0 unused */ 624adfc5217SJeff Kirsher #define MAC_PHYCFG1 0x000005a0 625adfc5217SJeff Kirsher #define MAC_PHYCFG1_RGMII_INT 0x00000001 626adfc5217SJeff Kirsher #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 627adfc5217SJeff Kirsher #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 628adfc5217SJeff Kirsher #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 629adfc5217SJeff Kirsher #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 630adfc5217SJeff Kirsher #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 631adfc5217SJeff Kirsher #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 632adfc5217SJeff Kirsher #define MAC_PHYCFG1_TXC_DRV 0x20000000 633adfc5217SJeff Kirsher #define MAC_PHYCFG2 0x000005a4 634adfc5217SJeff Kirsher #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 635adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 636adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 637adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 638adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 639adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 640adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 641adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 642adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 643adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 644adfc5217SJeff Kirsher #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 645adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 646adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 647adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 648adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 649adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 650adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 651adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 652adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 653adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 654adfc5217SJeff Kirsher #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 655adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 656adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 657adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 658adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 659adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 660adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 661adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 662adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 663adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 664adfc5217SJeff Kirsher #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 665adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 666adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 667adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 668adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 669adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 670adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 671adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 672adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 673adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 674adfc5217SJeff Kirsher #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 675adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 676adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 677adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 678adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 679adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 680adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 681adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 682adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 683adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 684adfc5217SJeff Kirsher #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 685adfc5217SJeff Kirsher #define MAC_PHYCFG2_50610_LED_MODES \ 686adfc5217SJeff Kirsher (MAC_PHYCFG2_EMODE_MASK_50610 | \ 687adfc5217SJeff Kirsher MAC_PHYCFG2_EMODE_COMP_50610 | \ 688adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_MASK_50610 | \ 689adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_COMP_50610 | \ 690adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_MASK_50610 | \ 691adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_COMP_50610 | \ 692adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_MASK_50610 | \ 693adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_COMP_50610 | \ 694adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_MASK_50610 | \ 695adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_COMP_50610) 696adfc5217SJeff Kirsher #define MAC_PHYCFG2_AC131_LED_MODES \ 697adfc5217SJeff Kirsher (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 698adfc5217SJeff Kirsher MAC_PHYCFG2_EMODE_COMP_AC131 | \ 699adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_MASK_AC131 | \ 700adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_COMP_AC131 | \ 701adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_MASK_AC131 | \ 702adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_COMP_AC131 | \ 703adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_MASK_AC131 | \ 704adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_COMP_AC131 | \ 705adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_MASK_AC131 | \ 706adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_COMP_AC131) 707adfc5217SJeff Kirsher #define MAC_PHYCFG2_RTL8211C_LED_MODES \ 708adfc5217SJeff Kirsher (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 709adfc5217SJeff Kirsher MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 710adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 711adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 712adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 713adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 714adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_MASK_RT8211 | \ 715adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_COMP_RT8211 | \ 716adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 717adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_COMP_RT8211) 718adfc5217SJeff Kirsher #define MAC_PHYCFG2_RTL8201E_LED_MODES \ 719adfc5217SJeff Kirsher (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 720adfc5217SJeff Kirsher MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 721adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 722adfc5217SJeff Kirsher MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 723adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 724adfc5217SJeff Kirsher MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 725adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_MASK_RT8201 | \ 726adfc5217SJeff Kirsher MAC_PHYCFG2_ACT_COMP_RT8201 | \ 727adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 728adfc5217SJeff Kirsher MAC_PHYCFG2_QUAL_COMP_RT8201) 729adfc5217SJeff Kirsher #define MAC_EXT_RGMII_MODE 0x000005a8 730adfc5217SJeff Kirsher #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 731adfc5217SJeff Kirsher #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 732adfc5217SJeff Kirsher #define MAC_RGMII_MODE_TX_RESET 0x00000004 733adfc5217SJeff Kirsher #define MAC_RGMII_MODE_RX_INT_B 0x00000100 734adfc5217SJeff Kirsher #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 735adfc5217SJeff Kirsher #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 736adfc5217SJeff Kirsher #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 737adfc5217SJeff Kirsher /* 0x5ac --> 0x5b0 unused */ 738adfc5217SJeff Kirsher #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 739adfc5217SJeff Kirsher #define SERDES_RX_SIG_DETECT 0x00000400 740adfc5217SJeff Kirsher #define SG_DIG_CTRL 0x000005b0 741adfc5217SJeff Kirsher #define SG_DIG_USING_HW_AUTONEG 0x80000000 742adfc5217SJeff Kirsher #define SG_DIG_SOFT_RESET 0x40000000 743adfc5217SJeff Kirsher #define SG_DIG_DISABLE_LINKRDY 0x20000000 744adfc5217SJeff Kirsher #define SG_DIG_CRC16_CLEAR_N 0x01000000 745adfc5217SJeff Kirsher #define SG_DIG_EN10B 0x00800000 746adfc5217SJeff Kirsher #define SG_DIG_CLEAR_STATUS 0x00400000 747adfc5217SJeff Kirsher #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 748adfc5217SJeff Kirsher #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 749adfc5217SJeff Kirsher #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 750adfc5217SJeff Kirsher #define SG_DIG_SPEED_STATUS_SHIFT 18 751adfc5217SJeff Kirsher #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 752adfc5217SJeff Kirsher #define SG_DIG_RESTART_AUTONEG 0x00010000 753adfc5217SJeff Kirsher #define SG_DIG_FIBER_MODE 0x00008000 754adfc5217SJeff Kirsher #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 755adfc5217SJeff Kirsher #define SG_DIG_PAUSE_MASK 0x00001800 756adfc5217SJeff Kirsher #define SG_DIG_PAUSE_CAP 0x00000800 757adfc5217SJeff Kirsher #define SG_DIG_ASYM_PAUSE 0x00001000 758adfc5217SJeff Kirsher #define SG_DIG_GBIC_ENABLE 0x00000400 759adfc5217SJeff Kirsher #define SG_DIG_CHECK_END_ENABLE 0x00000200 760adfc5217SJeff Kirsher #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 761adfc5217SJeff Kirsher #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 762adfc5217SJeff Kirsher #define SG_DIG_GMII_INPUT_SELECT 0x00000040 763adfc5217SJeff Kirsher #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 764adfc5217SJeff Kirsher #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 765adfc5217SJeff Kirsher #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 766adfc5217SJeff Kirsher #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 767adfc5217SJeff Kirsher #define SG_DIG_REMOTE_LOOPBACK 0x00000002 768adfc5217SJeff Kirsher #define SG_DIG_LOOPBACK 0x00000001 769adfc5217SJeff Kirsher #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 770adfc5217SJeff Kirsher SG_DIG_LOCAL_DUPLEX_STATUS | \ 771adfc5217SJeff Kirsher SG_DIG_LOCAL_LINK_STATUS | \ 772adfc5217SJeff Kirsher (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 773adfc5217SJeff Kirsher SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 774adfc5217SJeff Kirsher #define SG_DIG_STATUS 0x000005b4 775adfc5217SJeff Kirsher #define SG_DIG_CRC16_BUS_MASK 0xffff0000 776adfc5217SJeff Kirsher #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 777adfc5217SJeff Kirsher #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 778adfc5217SJeff Kirsher #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 779adfc5217SJeff Kirsher #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 780adfc5217SJeff Kirsher #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 781adfc5217SJeff Kirsher #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 782adfc5217SJeff Kirsher #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 783adfc5217SJeff Kirsher #define SG_DIG_IS_SERDES 0x00000100 784adfc5217SJeff Kirsher #define SG_DIG_COMMA_DETECTOR 0x00000008 785adfc5217SJeff Kirsher #define SG_DIG_MAC_ACK_STATUS 0x00000004 786adfc5217SJeff Kirsher #define SG_DIG_AUTONEG_COMPLETE 0x00000002 787adfc5217SJeff Kirsher #define SG_DIG_AUTONEG_ERROR 0x00000001 788be947307SMatt Carlson #define TG3_TX_TSTAMP_LSB 0x000005c0 789be947307SMatt Carlson #define TG3_TX_TSTAMP_MSB 0x000005c4 790579e1d81SPeter Hüwe #define TG3_TSTAMP_MASK 0x7fffffffffffffffLL 791be947307SMatt Carlson /* 0x5c8 --> 0x600 unused */ 792adfc5217SJeff Kirsher #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 793adfc5217SJeff Kirsher #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 794adfc5217SJeff Kirsher /* 0x624 --> 0x670 unused */ 795adfc5217SJeff Kirsher 796adfc5217SJeff Kirsher #define MAC_RSS_INDIR_TBL_0 0x00000630 797adfc5217SJeff Kirsher 798adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_0 0x00000670 799adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_1 0x00000674 800adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_2 0x00000678 801adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_3 0x0000067c 802adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_4 0x00000680 803adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_5 0x00000684 804adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_6 0x00000688 805adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_7 0x0000068c 806adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_8 0x00000690 807adfc5217SJeff Kirsher #define MAC_RSS_HASH_KEY_9 0x00000694 808be947307SMatt Carlson /* 0x698 --> 0x6b0 unused */ 809be947307SMatt Carlson 810be947307SMatt Carlson #define TG3_RX_TSTAMP_LSB 0x000006b0 811be947307SMatt Carlson #define TG3_RX_TSTAMP_MSB 0x000006b4 812be947307SMatt Carlson /* 0x6b8 --> 0x6c8 unused */ 813be947307SMatt Carlson 814be947307SMatt Carlson #define TG3_RX_PTP_CTL 0x000006c8 815be947307SMatt Carlson #define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001 816be947307SMatt Carlson #define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002 817be947307SMatt Carlson #define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004 818be947307SMatt Carlson #define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008 819be947307SMatt Carlson #define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 820be947307SMatt Carlson TG3_RX_PTP_CTL_DELAY_REQ) 821be947307SMatt Carlson #define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 822be947307SMatt Carlson TG3_RX_PTP_CTL_DELAY_REQ | \ 823be947307SMatt Carlson TG3_RX_PTP_CTL_PDLAY_REQ | \ 824be947307SMatt Carlson TG3_RX_PTP_CTL_PDLAY_RES) 825be947307SMatt Carlson #define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100 826be947307SMatt Carlson #define TG3_RX_PTP_CTL_DELAY_RES 0x00000200 827be947307SMatt Carlson #define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400 828be947307SMatt Carlson #define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800 829be947307SMatt Carlson #define TG3_RX_PTP_CTL_SIGNALING 0x00001000 830be947307SMatt Carlson #define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000 831be947307SMatt Carlson #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000 832be947307SMatt Carlson #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000 833be947307SMatt Carlson #define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \ 834be947307SMatt Carlson TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN) 835be947307SMatt Carlson #define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000 836be947307SMatt Carlson #define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000 837be947307SMatt Carlson /* 0x6cc --> 0x800 unused */ 838adfc5217SJeff Kirsher 839adfc5217SJeff Kirsher #define MAC_TX_STATS_OCTETS 0x00000800 840adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV1 0x00000804 841adfc5217SJeff Kirsher #define MAC_TX_STATS_COLLISIONS 0x00000808 842adfc5217SJeff Kirsher #define MAC_TX_STATS_XON_SENT 0x0000080c 843adfc5217SJeff Kirsher #define MAC_TX_STATS_XOFF_SENT 0x00000810 844adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV2 0x00000814 845adfc5217SJeff Kirsher #define MAC_TX_STATS_MAC_ERRORS 0x00000818 846adfc5217SJeff Kirsher #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 847adfc5217SJeff Kirsher #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 848adfc5217SJeff Kirsher #define MAC_TX_STATS_DEFERRED 0x00000824 849adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV3 0x00000828 850adfc5217SJeff Kirsher #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 851adfc5217SJeff Kirsher #define MAC_TX_STATS_LATE_COL 0x00000830 852adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_1 0x00000834 853adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_2 0x00000838 854adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_3 0x0000083c 855adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_4 0x00000840 856adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_5 0x00000844 857adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_6 0x00000848 858adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_7 0x0000084c 859adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_8 0x00000850 860adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_9 0x00000854 861adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_10 0x00000858 862adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_11 0x0000085c 863adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_12 0x00000860 864adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_13 0x00000864 865adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV4_14 0x00000868 866adfc5217SJeff Kirsher #define MAC_TX_STATS_UCAST 0x0000086c 867adfc5217SJeff Kirsher #define MAC_TX_STATS_MCAST 0x00000870 868adfc5217SJeff Kirsher #define MAC_TX_STATS_BCAST 0x00000874 869adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV5_1 0x00000878 870adfc5217SJeff Kirsher #define MAC_TX_STATS_RESV5_2 0x0000087c 871adfc5217SJeff Kirsher #define MAC_RX_STATS_OCTETS 0x00000880 872adfc5217SJeff Kirsher #define MAC_RX_STATS_RESV1 0x00000884 873adfc5217SJeff Kirsher #define MAC_RX_STATS_FRAGMENTS 0x00000888 874adfc5217SJeff Kirsher #define MAC_RX_STATS_UCAST 0x0000088c 875adfc5217SJeff Kirsher #define MAC_RX_STATS_MCAST 0x00000890 876adfc5217SJeff Kirsher #define MAC_RX_STATS_BCAST 0x00000894 877adfc5217SJeff Kirsher #define MAC_RX_STATS_FCS_ERRORS 0x00000898 878adfc5217SJeff Kirsher #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 879adfc5217SJeff Kirsher #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 880adfc5217SJeff Kirsher #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 881adfc5217SJeff Kirsher #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 882adfc5217SJeff Kirsher #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 883adfc5217SJeff Kirsher #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 884adfc5217SJeff Kirsher #define MAC_RX_STATS_JABBERS 0x000008b4 885adfc5217SJeff Kirsher #define MAC_RX_STATS_UNDERSIZE 0x000008b8 886adfc5217SJeff Kirsher /* 0x8bc --> 0xc00 unused */ 887adfc5217SJeff Kirsher 888adfc5217SJeff Kirsher /* Send data initiator control registers */ 889adfc5217SJeff Kirsher #define SNDDATAI_MODE 0x00000c00 890adfc5217SJeff Kirsher #define SNDDATAI_MODE_RESET 0x00000001 891adfc5217SJeff Kirsher #define SNDDATAI_MODE_ENABLE 0x00000002 892adfc5217SJeff Kirsher #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 893adfc5217SJeff Kirsher #define SNDDATAI_STATUS 0x00000c04 894adfc5217SJeff Kirsher #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 895adfc5217SJeff Kirsher #define SNDDATAI_STATSCTRL 0x00000c08 896adfc5217SJeff Kirsher #define SNDDATAI_SCTRL_ENABLE 0x00000001 897adfc5217SJeff Kirsher #define SNDDATAI_SCTRL_FASTUPD 0x00000002 898adfc5217SJeff Kirsher #define SNDDATAI_SCTRL_CLEAR 0x00000004 899adfc5217SJeff Kirsher #define SNDDATAI_SCTRL_FLUSH 0x00000008 900adfc5217SJeff Kirsher #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 901adfc5217SJeff Kirsher #define SNDDATAI_STATSENAB 0x00000c0c 902adfc5217SJeff Kirsher #define SNDDATAI_STATSINCMASK 0x00000c10 903adfc5217SJeff Kirsher #define ISO_PKT_TX 0x00000c20 904adfc5217SJeff Kirsher /* 0xc24 --> 0xc80 unused */ 905adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_0 0x00000c80 906adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_1 0x00000c84 907adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_2 0x00000c88 908adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_3 0x00000c8c 909adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_4 0x00000c90 910adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_5 0x00000c94 911adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_6 0x00000c98 912adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_7 0x00000c9c 913adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_8 0x00000ca0 914adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_9 0x00000ca4 915adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_10 0x00000ca8 916adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_11 0x00000cac 917adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_12 0x00000cb0 918adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_13 0x00000cb4 919adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_14 0x00000cb8 920adfc5217SJeff Kirsher #define SNDDATAI_COS_CNT_15 0x00000cbc 921adfc5217SJeff Kirsher #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 922adfc5217SJeff Kirsher #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 923adfc5217SJeff Kirsher #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 924adfc5217SJeff Kirsher #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 925adfc5217SJeff Kirsher #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 926adfc5217SJeff Kirsher #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 927adfc5217SJeff Kirsher #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 928adfc5217SJeff Kirsher #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 929adfc5217SJeff Kirsher /* 0xce0 --> 0x1000 unused */ 930adfc5217SJeff Kirsher 931adfc5217SJeff Kirsher /* Send data completion control registers */ 932adfc5217SJeff Kirsher #define SNDDATAC_MODE 0x00001000 933adfc5217SJeff Kirsher #define SNDDATAC_MODE_RESET 0x00000001 934adfc5217SJeff Kirsher #define SNDDATAC_MODE_ENABLE 0x00000002 935adfc5217SJeff Kirsher #define SNDDATAC_MODE_CDELAY 0x00000010 936adfc5217SJeff Kirsher /* 0x1004 --> 0x1400 unused */ 937adfc5217SJeff Kirsher 938adfc5217SJeff Kirsher /* Send BD ring selector */ 939adfc5217SJeff Kirsher #define SNDBDS_MODE 0x00001400 940adfc5217SJeff Kirsher #define SNDBDS_MODE_RESET 0x00000001 941adfc5217SJeff Kirsher #define SNDBDS_MODE_ENABLE 0x00000002 942adfc5217SJeff Kirsher #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 943adfc5217SJeff Kirsher #define SNDBDS_STATUS 0x00001404 944adfc5217SJeff Kirsher #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 945adfc5217SJeff Kirsher #define SNDBDS_HWDIAG 0x00001408 946adfc5217SJeff Kirsher /* 0x140c --> 0x1440 */ 947adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_0 0x00001440 948adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_1 0x00001444 949adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_2 0x00001448 950adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_3 0x0000144c 951adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_4 0x00001450 952adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_5 0x00001454 953adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_6 0x00001458 954adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_7 0x0000145c 955adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_8 0x00001460 956adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_9 0x00001464 957adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_10 0x00001468 958adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_11 0x0000146c 959adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_12 0x00001470 960adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_13 0x00001474 961adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_14 0x00001478 962adfc5217SJeff Kirsher #define SNDBDS_SEL_CON_IDX_15 0x0000147c 963adfc5217SJeff Kirsher /* 0x1480 --> 0x1800 unused */ 964adfc5217SJeff Kirsher 965adfc5217SJeff Kirsher /* Send BD initiator control registers */ 966adfc5217SJeff Kirsher #define SNDBDI_MODE 0x00001800 967adfc5217SJeff Kirsher #define SNDBDI_MODE_RESET 0x00000001 968adfc5217SJeff Kirsher #define SNDBDI_MODE_ENABLE 0x00000002 969adfc5217SJeff Kirsher #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 970adfc5217SJeff Kirsher #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 971adfc5217SJeff Kirsher #define SNDBDI_STATUS 0x00001804 972adfc5217SJeff Kirsher #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 973adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_0 0x00001808 974adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_1 0x0000180c 975adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_2 0x00001810 976adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_3 0x00001814 977adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_4 0x00001818 978adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_5 0x0000181c 979adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_6 0x00001820 980adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_7 0x00001824 981adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_8 0x00001828 982adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_9 0x0000182c 983adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_10 0x00001830 984adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_11 0x00001834 985adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_12 0x00001838 986adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_13 0x0000183c 987adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_14 0x00001840 988adfc5217SJeff Kirsher #define SNDBDI_IN_PROD_IDX_15 0x00001844 989adfc5217SJeff Kirsher /* 0x1848 --> 0x1c00 unused */ 990adfc5217SJeff Kirsher 991adfc5217SJeff Kirsher /* Send BD completion control registers */ 992adfc5217SJeff Kirsher #define SNDBDC_MODE 0x00001c00 993adfc5217SJeff Kirsher #define SNDBDC_MODE_RESET 0x00000001 994adfc5217SJeff Kirsher #define SNDBDC_MODE_ENABLE 0x00000002 995adfc5217SJeff Kirsher #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 996adfc5217SJeff Kirsher /* 0x1c04 --> 0x2000 unused */ 997adfc5217SJeff Kirsher 998adfc5217SJeff Kirsher /* Receive list placement control registers */ 999adfc5217SJeff Kirsher #define RCVLPC_MODE 0x00002000 1000adfc5217SJeff Kirsher #define RCVLPC_MODE_RESET 0x00000001 1001adfc5217SJeff Kirsher #define RCVLPC_MODE_ENABLE 0x00000002 1002adfc5217SJeff Kirsher #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 1003adfc5217SJeff Kirsher #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 1004adfc5217SJeff Kirsher #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 1005adfc5217SJeff Kirsher #define RCVLPC_STATUS 0x00002004 1006adfc5217SJeff Kirsher #define RCVLPC_STATUS_CLASS0 0x00000004 1007adfc5217SJeff Kirsher #define RCVLPC_STATUS_MAPOOR 0x00000008 1008adfc5217SJeff Kirsher #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 1009adfc5217SJeff Kirsher #define RCVLPC_LOCK 0x00002008 1010adfc5217SJeff Kirsher #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 1011adfc5217SJeff Kirsher #define RCVLPC_LOCK_REQ_SHIFT 0 1012adfc5217SJeff Kirsher #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 1013adfc5217SJeff Kirsher #define RCVLPC_LOCK_GRANT_SHIFT 16 1014adfc5217SJeff Kirsher #define RCVLPC_NON_EMPTY_BITS 0x0000200c 1015adfc5217SJeff Kirsher #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 1016adfc5217SJeff Kirsher #define RCVLPC_CONFIG 0x00002010 1017adfc5217SJeff Kirsher #define RCVLPC_STATSCTRL 0x00002014 1018adfc5217SJeff Kirsher #define RCVLPC_STATSCTRL_ENABLE 0x00000001 1019adfc5217SJeff Kirsher #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 1020adfc5217SJeff Kirsher #define RCVLPC_STATS_ENABLE 0x00002018 1021adfc5217SJeff Kirsher #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 1022adfc5217SJeff Kirsher #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 1023adfc5217SJeff Kirsher #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 1024adfc5217SJeff Kirsher #define RCVLPC_STATS_INCMASK 0x0000201c 1025adfc5217SJeff Kirsher /* 0x2020 --> 0x2100 unused */ 1026adfc5217SJeff Kirsher #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 1027adfc5217SJeff Kirsher #define SELLST_TAIL 0x00000004 1028adfc5217SJeff Kirsher #define SELLST_CONT 0x00000008 1029adfc5217SJeff Kirsher #define SELLST_UNUSED 0x0000000c 1030adfc5217SJeff Kirsher #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 1031adfc5217SJeff Kirsher #define RCVLPC_DROP_FILTER_CNT 0x00002240 1032adfc5217SJeff Kirsher #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 1033adfc5217SJeff Kirsher #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 1034adfc5217SJeff Kirsher #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 1035adfc5217SJeff Kirsher #define RCVLPC_IN_DISCARDS_CNT 0x00002250 1036adfc5217SJeff Kirsher #define RCVLPC_IN_ERRORS_CNT 0x00002254 1037adfc5217SJeff Kirsher #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 1038adfc5217SJeff Kirsher /* 0x225c --> 0x2400 unused */ 1039adfc5217SJeff Kirsher 1040adfc5217SJeff Kirsher /* Receive Data and Receive BD Initiator Control */ 1041adfc5217SJeff Kirsher #define RCVDBDI_MODE 0x00002400 1042adfc5217SJeff Kirsher #define RCVDBDI_MODE_RESET 0x00000001 1043adfc5217SJeff Kirsher #define RCVDBDI_MODE_ENABLE 0x00000002 1044adfc5217SJeff Kirsher #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 1045adfc5217SJeff Kirsher #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 1046adfc5217SJeff Kirsher #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 1047adfc5217SJeff Kirsher #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 1048adfc5217SJeff Kirsher #define RCVDBDI_STATUS 0x00002404 1049adfc5217SJeff Kirsher #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 1050adfc5217SJeff Kirsher #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 1051adfc5217SJeff Kirsher #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 1052adfc5217SJeff Kirsher #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 1053adfc5217SJeff Kirsher /* 0x240c --> 0x2440 unused */ 1054adfc5217SJeff Kirsher #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 1055adfc5217SJeff Kirsher #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 1056adfc5217SJeff Kirsher #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 1057adfc5217SJeff Kirsher #define RCVDBDI_JUMBO_CON_IDX 0x00002470 1058adfc5217SJeff Kirsher #define RCVDBDI_STD_CON_IDX 0x00002474 1059adfc5217SJeff Kirsher #define RCVDBDI_MINI_CON_IDX 0x00002478 1060adfc5217SJeff Kirsher /* 0x247c --> 0x2480 unused */ 1061adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_0 0x00002480 1062adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_1 0x00002484 1063adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_2 0x00002488 1064adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1065adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_4 0x00002490 1066adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_5 0x00002494 1067adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_6 0x00002498 1068adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1069adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1070adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1071adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1072adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1073adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1074adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1075adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1076adfc5217SJeff Kirsher #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1077adfc5217SJeff Kirsher #define RCVDBDI_HWDIAG 0x000024c0 1078adfc5217SJeff Kirsher /* 0x24c4 --> 0x2800 unused */ 1079adfc5217SJeff Kirsher 1080adfc5217SJeff Kirsher /* Receive Data Completion Control */ 1081adfc5217SJeff Kirsher #define RCVDCC_MODE 0x00002800 1082adfc5217SJeff Kirsher #define RCVDCC_MODE_RESET 0x00000001 1083adfc5217SJeff Kirsher #define RCVDCC_MODE_ENABLE 0x00000002 1084adfc5217SJeff Kirsher #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1085adfc5217SJeff Kirsher /* 0x2804 --> 0x2c00 unused */ 1086adfc5217SJeff Kirsher 1087adfc5217SJeff Kirsher /* Receive BD Initiator Control Registers */ 1088adfc5217SJeff Kirsher #define RCVBDI_MODE 0x00002c00 1089adfc5217SJeff Kirsher #define RCVBDI_MODE_RESET 0x00000001 1090adfc5217SJeff Kirsher #define RCVBDI_MODE_ENABLE 0x00000002 1091adfc5217SJeff Kirsher #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1092adfc5217SJeff Kirsher #define RCVBDI_STATUS 0x00002c04 1093adfc5217SJeff Kirsher #define RCVBDI_STATUS_RCB_ATTN 0x00000004 1094adfc5217SJeff Kirsher #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1095adfc5217SJeff Kirsher #define RCVBDI_STD_PROD_IDX 0x00002c0c 1096adfc5217SJeff Kirsher #define RCVBDI_MINI_PROD_IDX 0x00002c10 1097adfc5217SJeff Kirsher #define RCVBDI_MINI_THRESH 0x00002c14 1098adfc5217SJeff Kirsher #define RCVBDI_STD_THRESH 0x00002c18 1099adfc5217SJeff Kirsher #define RCVBDI_JUMBO_THRESH 0x00002c1c 1100adfc5217SJeff Kirsher /* 0x2c20 --> 0x2d00 unused */ 1101adfc5217SJeff Kirsher 1102adfc5217SJeff Kirsher #define STD_REPLENISH_LWM 0x00002d00 1103adfc5217SJeff Kirsher #define JMB_REPLENISH_LWM 0x00002d04 1104adfc5217SJeff Kirsher /* 0x2d08 --> 0x3000 unused */ 1105adfc5217SJeff Kirsher 1106adfc5217SJeff Kirsher /* Receive BD Completion Control Registers */ 1107adfc5217SJeff Kirsher #define RCVCC_MODE 0x00003000 1108adfc5217SJeff Kirsher #define RCVCC_MODE_RESET 0x00000001 1109adfc5217SJeff Kirsher #define RCVCC_MODE_ENABLE 0x00000002 1110adfc5217SJeff Kirsher #define RCVCC_MODE_ATTN_ENABLE 0x00000004 1111adfc5217SJeff Kirsher #define RCVCC_STATUS 0x00003004 1112adfc5217SJeff Kirsher #define RCVCC_STATUS_ERROR_ATTN 0x00000004 1113adfc5217SJeff Kirsher #define RCVCC_JUMP_PROD_IDX 0x00003008 1114adfc5217SJeff Kirsher #define RCVCC_STD_PROD_IDX 0x0000300c 1115adfc5217SJeff Kirsher #define RCVCC_MINI_PROD_IDX 0x00003010 1116adfc5217SJeff Kirsher /* 0x3014 --> 0x3400 unused */ 1117adfc5217SJeff Kirsher 1118adfc5217SJeff Kirsher /* Receive list selector control registers */ 1119adfc5217SJeff Kirsher #define RCVLSC_MODE 0x00003400 1120adfc5217SJeff Kirsher #define RCVLSC_MODE_RESET 0x00000001 1121adfc5217SJeff Kirsher #define RCVLSC_MODE_ENABLE 0x00000002 1122adfc5217SJeff Kirsher #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1123adfc5217SJeff Kirsher #define RCVLSC_STATUS 0x00003404 1124adfc5217SJeff Kirsher #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1125adfc5217SJeff Kirsher /* 0x3408 --> 0x3600 unused */ 1126adfc5217SJeff Kirsher 1127adfc5217SJeff Kirsher #define TG3_CPMU_DRV_STATUS 0x0000344c 1128adfc5217SJeff Kirsher 1129adfc5217SJeff Kirsher /* CPMU registers */ 1130adfc5217SJeff Kirsher #define TG3_CPMU_CTRL 0x00003600 1131adfc5217SJeff Kirsher #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1132adfc5217SJeff Kirsher #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1133adfc5217SJeff Kirsher #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1134adfc5217SJeff Kirsher #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1135adfc5217SJeff Kirsher #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1136adfc5217SJeff Kirsher #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1137adfc5217SJeff Kirsher #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1138adfc5217SJeff Kirsher /* 0x3608 --> 0x360c unused */ 1139adfc5217SJeff Kirsher 1140adfc5217SJeff Kirsher #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1141adfc5217SJeff Kirsher #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1142adfc5217SJeff Kirsher #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1143adfc5217SJeff Kirsher #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1144adfc5217SJeff Kirsher #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1145adfc5217SJeff Kirsher #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1146adfc5217SJeff Kirsher #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1147adfc5217SJeff Kirsher /* 0x3614 --> 0x361c unused */ 1148adfc5217SJeff Kirsher 1149adfc5217SJeff Kirsher #define TG3_CPMU_HST_ACC 0x0000361c 1150adfc5217SJeff Kirsher #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1151adfc5217SJeff Kirsher #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1152adfc5217SJeff Kirsher /* 0x3620 --> 0x3630 unused */ 1153adfc5217SJeff Kirsher 1154adfc5217SJeff Kirsher #define TG3_CPMU_CLCK_ORIDE 0x00003624 1155adfc5217SJeff Kirsher #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1156adfc5217SJeff Kirsher 1157f82995b6SNithin Sujir #define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628 1158f82995b6SNithin Sujir #define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13) 1159f82995b6SNithin Sujir 11609dc5e342SMatt Carlson #define TG3_CPMU_STATUS 0x0000362c 11619dc5e342SMatt Carlson #define TG3_CPMU_STATUS_FMSK_5717 0x20000000 11629dc5e342SMatt Carlson #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 11639dc5e342SMatt Carlson #define TG3_CPMU_STATUS_FSHFT_5719 30 11641743b83cSNithin Sujir #define TG3_CPMU_STATUS_LINK_MASK 0x180000 11659dc5e342SMatt Carlson 1166adfc5217SJeff Kirsher #define TG3_CPMU_CLCK_STAT 0x00003630 1167adfc5217SJeff Kirsher #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1168adfc5217SJeff Kirsher #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1169adfc5217SJeff Kirsher #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1170adfc5217SJeff Kirsher #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1171adfc5217SJeff Kirsher /* 0x3634 --> 0x365c unused */ 1172adfc5217SJeff Kirsher 1173adfc5217SJeff Kirsher #define TG3_CPMU_MUTEX_REQ 0x0000365c 1174adfc5217SJeff Kirsher #define CPMU_MUTEX_REQ_DRIVER 0x00001000 1175adfc5217SJeff Kirsher #define TG3_CPMU_MUTEX_GNT 0x00003660 1176adfc5217SJeff Kirsher #define CPMU_MUTEX_GNT_DRIVER 0x00001000 1177adfc5217SJeff Kirsher #define TG3_CPMU_PHY_STRAP 0x00003664 1178adfc5217SJeff Kirsher #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1179d3f677afSMatt Carlson #define TG3_CPMU_PADRNG_CTL 0x00003668 1180d3f677afSMatt Carlson #define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000 1181adfc5217SJeff Kirsher /* 0x3664 --> 0x36b0 unused */ 1182adfc5217SJeff Kirsher 1183adfc5217SJeff Kirsher #define TG3_CPMU_EEE_MODE 0x000036b0 1184adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1185adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1186adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1187adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1188adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1189adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1190adfc5217SJeff Kirsher #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1191adfc5217SJeff Kirsher #define TG3_CPMU_EEE_DBTMR1 0x000036b4 1192adfc5217SJeff Kirsher #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1193adfc5217SJeff Kirsher #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 11941cbf9eb8SNithin Sujir #define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff 1195adfc5217SJeff Kirsher #define TG3_CPMU_EEE_DBTMR2 0x000036b8 1196adfc5217SJeff Kirsher #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1197adfc5217SJeff Kirsher #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1198adfc5217SJeff Kirsher #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1199adfc5217SJeff Kirsher #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 1200adfc5217SJeff Kirsher #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 1201c65a17f4SMichael Chan #define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002 1202adfc5217SJeff Kirsher /* 0x36c0 --> 0x36d0 unused */ 1203adfc5217SJeff Kirsher 1204adfc5217SJeff Kirsher #define TG3_CPMU_EEE_CTRL 0x000036d0 1205adfc5217SJeff Kirsher #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d 1206adfc5217SJeff Kirsher #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 1207adfc5217SJeff Kirsher #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 1208adfc5217SJeff Kirsher /* 0x36d4 --> 0x3800 unused */ 1209adfc5217SJeff Kirsher 1210adfc5217SJeff Kirsher /* Mbuf cluster free registers */ 1211adfc5217SJeff Kirsher #define MBFREE_MODE 0x00003800 1212adfc5217SJeff Kirsher #define MBFREE_MODE_RESET 0x00000001 1213adfc5217SJeff Kirsher #define MBFREE_MODE_ENABLE 0x00000002 1214adfc5217SJeff Kirsher #define MBFREE_STATUS 0x00003804 1215adfc5217SJeff Kirsher /* 0x3808 --> 0x3c00 unused */ 1216adfc5217SJeff Kirsher 1217adfc5217SJeff Kirsher /* Host coalescing control registers */ 1218adfc5217SJeff Kirsher #define HOSTCC_MODE 0x00003c00 1219adfc5217SJeff Kirsher #define HOSTCC_MODE_RESET 0x00000001 1220adfc5217SJeff Kirsher #define HOSTCC_MODE_ENABLE 0x00000002 1221adfc5217SJeff Kirsher #define HOSTCC_MODE_ATTN 0x00000004 1222adfc5217SJeff Kirsher #define HOSTCC_MODE_NOW 0x00000008 1223adfc5217SJeff Kirsher #define HOSTCC_MODE_FULL_STATUS 0x00000000 1224adfc5217SJeff Kirsher #define HOSTCC_MODE_64BYTE 0x00000080 1225adfc5217SJeff Kirsher #define HOSTCC_MODE_32BYTE 0x00000100 1226adfc5217SJeff Kirsher #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1227adfc5217SJeff Kirsher #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1228adfc5217SJeff Kirsher #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1229adfc5217SJeff Kirsher #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1230adfc5217SJeff Kirsher #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1231adfc5217SJeff Kirsher #define HOSTCC_STATUS 0x00003c04 1232adfc5217SJeff Kirsher #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1233adfc5217SJeff Kirsher #define HOSTCC_RXCOL_TICKS 0x00003c08 1234adfc5217SJeff Kirsher #define LOW_RXCOL_TICKS 0x00000032 1235adfc5217SJeff Kirsher #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1236adfc5217SJeff Kirsher #define DEFAULT_RXCOL_TICKS 0x00000048 1237adfc5217SJeff Kirsher #define HIGH_RXCOL_TICKS 0x00000096 1238adfc5217SJeff Kirsher #define MAX_RXCOL_TICKS 0x000003ff 1239adfc5217SJeff Kirsher #define HOSTCC_TXCOL_TICKS 0x00003c0c 1240adfc5217SJeff Kirsher #define LOW_TXCOL_TICKS 0x00000096 1241adfc5217SJeff Kirsher #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1242adfc5217SJeff Kirsher #define DEFAULT_TXCOL_TICKS 0x0000012c 1243adfc5217SJeff Kirsher #define HIGH_TXCOL_TICKS 0x00000145 1244adfc5217SJeff Kirsher #define MAX_TXCOL_TICKS 0x000003ff 1245adfc5217SJeff Kirsher #define HOSTCC_RXMAX_FRAMES 0x00003c10 1246adfc5217SJeff Kirsher #define LOW_RXMAX_FRAMES 0x00000005 1247adfc5217SJeff Kirsher #define DEFAULT_RXMAX_FRAMES 0x00000008 1248adfc5217SJeff Kirsher #define HIGH_RXMAX_FRAMES 0x00000012 1249adfc5217SJeff Kirsher #define MAX_RXMAX_FRAMES 0x000000ff 1250adfc5217SJeff Kirsher #define HOSTCC_TXMAX_FRAMES 0x00003c14 1251adfc5217SJeff Kirsher #define LOW_TXMAX_FRAMES 0x00000035 1252adfc5217SJeff Kirsher #define DEFAULT_TXMAX_FRAMES 0x0000004b 1253adfc5217SJeff Kirsher #define HIGH_TXMAX_FRAMES 0x00000052 1254adfc5217SJeff Kirsher #define MAX_TXMAX_FRAMES 0x000000ff 1255adfc5217SJeff Kirsher #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1256adfc5217SJeff Kirsher #define DEFAULT_RXCOAL_TICK_INT 0x00000019 1257adfc5217SJeff Kirsher #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1258adfc5217SJeff Kirsher #define MAX_RXCOAL_TICK_INT 0x000003ff 1259adfc5217SJeff Kirsher #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1260adfc5217SJeff Kirsher #define DEFAULT_TXCOAL_TICK_INT 0x00000019 1261adfc5217SJeff Kirsher #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1262adfc5217SJeff Kirsher #define MAX_TXCOAL_TICK_INT 0x000003ff 1263adfc5217SJeff Kirsher #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1264adfc5217SJeff Kirsher #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1265adfc5217SJeff Kirsher #define MAX_RXCOAL_MAXF_INT 0x000000ff 1266adfc5217SJeff Kirsher #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1267adfc5217SJeff Kirsher #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1268adfc5217SJeff Kirsher #define MAX_TXCOAL_MAXF_INT 0x000000ff 1269adfc5217SJeff Kirsher #define HOSTCC_STAT_COAL_TICKS 0x00003c28 1270adfc5217SJeff Kirsher #define DEFAULT_STAT_COAL_TICKS 0x000f4240 1271adfc5217SJeff Kirsher #define MAX_STAT_COAL_TICKS 0xd693d400 1272adfc5217SJeff Kirsher #define MIN_STAT_COAL_TICKS 0x00000064 1273adfc5217SJeff Kirsher /* 0x3c2c --> 0x3c30 unused */ 1274adfc5217SJeff Kirsher #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1275adfc5217SJeff Kirsher #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1276adfc5217SJeff Kirsher #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1277adfc5217SJeff Kirsher #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1278adfc5217SJeff Kirsher #define HOSTCC_FLOW_ATTN 0x00003c48 1279adfc5217SJeff Kirsher #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040 1280adfc5217SJeff Kirsher /* 0x3c4c --> 0x3c50 unused */ 1281adfc5217SJeff Kirsher #define HOSTCC_JUMBO_CON_IDX 0x00003c50 1282adfc5217SJeff Kirsher #define HOSTCC_STD_CON_IDX 0x00003c54 1283adfc5217SJeff Kirsher #define HOSTCC_MINI_CON_IDX 0x00003c58 1284adfc5217SJeff Kirsher /* 0x3c5c --> 0x3c80 unused */ 1285adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_0 0x00003c80 1286adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_1 0x00003c84 1287adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_2 0x00003c88 1288adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1289adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_4 0x00003c90 1290adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_5 0x00003c94 1291adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_6 0x00003c98 1292adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1293adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1294adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1295adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1296adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_11 0x00003cac 1297adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1298adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1299adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1300adfc5217SJeff Kirsher #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1301adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_0 0x00003cc0 1302adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_1 0x00003cc4 1303adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_2 0x00003cc8 1304adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_3 0x00003ccc 1305adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_4 0x00003cd0 1306adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_5 0x00003cd4 1307adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_6 0x00003cd8 1308adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_7 0x00003cdc 1309adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_8 0x00003ce0 1310adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_9 0x00003ce4 1311adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_10 0x00003ce8 1312adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_11 0x00003cec 1313adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_12 0x00003cf0 1314adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_13 0x00003cf4 1315adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_14 0x00003cf8 1316adfc5217SJeff Kirsher #define HOSTCC_SND_CON_IDX_15 0x00003cfc 1317adfc5217SJeff Kirsher #define HOSTCC_STATBLCK_RING1 0x00003d00 1318adfc5217SJeff Kirsher /* 0x3d00 --> 0x3d80 unused */ 1319adfc5217SJeff Kirsher 1320adfc5217SJeff Kirsher #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1321adfc5217SJeff Kirsher #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1322adfc5217SJeff Kirsher #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1323adfc5217SJeff Kirsher #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1324adfc5217SJeff Kirsher #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1325adfc5217SJeff Kirsher #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1326adfc5217SJeff Kirsher /* 0x3d98 --> 0x4000 unused */ 1327adfc5217SJeff Kirsher 1328adfc5217SJeff Kirsher /* Memory arbiter control registers */ 1329adfc5217SJeff Kirsher #define MEMARB_MODE 0x00004000 1330adfc5217SJeff Kirsher #define MEMARB_MODE_RESET 0x00000001 1331adfc5217SJeff Kirsher #define MEMARB_MODE_ENABLE 0x00000002 1332adfc5217SJeff Kirsher #define MEMARB_STATUS 0x00004004 1333adfc5217SJeff Kirsher #define MEMARB_TRAP_ADDR_LOW 0x00004008 1334adfc5217SJeff Kirsher #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1335adfc5217SJeff Kirsher /* 0x4010 --> 0x4400 unused */ 1336adfc5217SJeff Kirsher 1337adfc5217SJeff Kirsher /* Buffer manager control registers */ 1338adfc5217SJeff Kirsher #define BUFMGR_MODE 0x00004400 1339adfc5217SJeff Kirsher #define BUFMGR_MODE_RESET 0x00000001 1340adfc5217SJeff Kirsher #define BUFMGR_MODE_ENABLE 0x00000002 1341adfc5217SJeff Kirsher #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1342adfc5217SJeff Kirsher #define BUFMGR_MODE_BM_TEST 0x00000008 1343adfc5217SJeff Kirsher #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1344adfc5217SJeff Kirsher #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 1345adfc5217SJeff Kirsher #define BUFMGR_STATUS 0x00004404 1346adfc5217SJeff Kirsher #define BUFMGR_STATUS_ERROR 0x00000004 1347adfc5217SJeff Kirsher #define BUFMGR_STATUS_MBLOW 0x00000010 1348adfc5217SJeff Kirsher #define BUFMGR_MB_POOL_ADDR 0x00004408 1349adfc5217SJeff Kirsher #define BUFMGR_MB_POOL_SIZE 0x0000440c 1350adfc5217SJeff Kirsher #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1351adfc5217SJeff Kirsher #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1352adfc5217SJeff Kirsher #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1353adfc5217SJeff Kirsher #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1354adfc5217SJeff Kirsher #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1355adfc5217SJeff Kirsher #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1356adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1357adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1358adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1359adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1360adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1361adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1362adfc5217SJeff Kirsher #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1363adfc5217SJeff Kirsher #define BUFMGR_MB_HIGH_WATER 0x00004418 1364adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER 0x00000060 1365adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1366adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1367adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1368adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1369adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1370adfc5217SJeff Kirsher #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1371adfc5217SJeff Kirsher #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1372adfc5217SJeff Kirsher #define BUFMGR_MB_ALLOC_BIT 0x10000000 1373adfc5217SJeff Kirsher #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1374adfc5217SJeff Kirsher #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1375adfc5217SJeff Kirsher #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1376adfc5217SJeff Kirsher #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1377adfc5217SJeff Kirsher #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1378adfc5217SJeff Kirsher #define BUFMGR_DMA_LOW_WATER 0x00004434 1379adfc5217SJeff Kirsher #define DEFAULT_DMA_LOW_WATER 0x00000005 1380adfc5217SJeff Kirsher #define BUFMGR_DMA_HIGH_WATER 0x00004438 1381adfc5217SJeff Kirsher #define DEFAULT_DMA_HIGH_WATER 0x0000000a 1382adfc5217SJeff Kirsher #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1383adfc5217SJeff Kirsher #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1384adfc5217SJeff Kirsher #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1385adfc5217SJeff Kirsher #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1386adfc5217SJeff Kirsher #define BUFMGR_HWDIAG_0 0x0000444c 1387adfc5217SJeff Kirsher #define BUFMGR_HWDIAG_1 0x00004450 1388adfc5217SJeff Kirsher #define BUFMGR_HWDIAG_2 0x00004454 1389adfc5217SJeff Kirsher /* 0x4458 --> 0x4800 unused */ 1390adfc5217SJeff Kirsher 1391adfc5217SJeff Kirsher /* Read DMA control registers */ 1392adfc5217SJeff Kirsher #define RDMAC_MODE 0x00004800 1393adfc5217SJeff Kirsher #define RDMAC_MODE_RESET 0x00000001 1394adfc5217SJeff Kirsher #define RDMAC_MODE_ENABLE 0x00000002 1395adfc5217SJeff Kirsher #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1396adfc5217SJeff Kirsher #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1397adfc5217SJeff Kirsher #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1398adfc5217SJeff Kirsher #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1399adfc5217SJeff Kirsher #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1400adfc5217SJeff Kirsher #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1401adfc5217SJeff Kirsher #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1402adfc5217SJeff Kirsher #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1403adfc5217SJeff Kirsher #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1404adfc5217SJeff Kirsher #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1405adfc5217SJeff Kirsher #define RDMAC_MODE_SPLIT_RESET 0x00001000 1406adfc5217SJeff Kirsher #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1407adfc5217SJeff Kirsher #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1408adfc5217SJeff Kirsher #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1409adfc5217SJeff Kirsher #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 141055086ad9SMatt Carlson #define RDMAC_MODE_JMB_2K_MMRR 0x00800000 1411adfc5217SJeff Kirsher #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1412adfc5217SJeff Kirsher #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1413adfc5217SJeff Kirsher #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1414adfc5217SJeff Kirsher #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000 1415adfc5217SJeff Kirsher #define RDMAC_STATUS 0x00004804 1416adfc5217SJeff Kirsher #define RDMAC_STATUS_TGTABORT 0x00000004 1417adfc5217SJeff Kirsher #define RDMAC_STATUS_MSTABORT 0x00000008 1418adfc5217SJeff Kirsher #define RDMAC_STATUS_PARITYERR 0x00000010 1419adfc5217SJeff Kirsher #define RDMAC_STATUS_ADDROFLOW 0x00000020 1420adfc5217SJeff Kirsher #define RDMAC_STATUS_FIFOOFLOW 0x00000040 1421adfc5217SJeff Kirsher #define RDMAC_STATUS_FIFOURUN 0x00000080 1422adfc5217SJeff Kirsher #define RDMAC_STATUS_FIFOOREAD 0x00000100 1423adfc5217SJeff Kirsher #define RDMAC_STATUS_LNGREAD 0x00000200 1424c65a17f4SMichael Chan /* 0x4808 --> 0x4890 unused */ 1425c65a17f4SMichael Chan 1426c65a17f4SMichael Chan #define TG3_RDMA_RSRVCTRL_REG2 0x00004890 1427c65a17f4SMichael Chan #define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0 1428adfc5217SJeff Kirsher 1429adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_REG 0x00004900 1430adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1431adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 1432adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 1433adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 1434adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 1435adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1436adfc5217SJeff Kirsher #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1437adfc5217SJeff Kirsher /* 0x4904 --> 0x4910 unused */ 1438adfc5217SJeff Kirsher 1439adfc5217SJeff Kirsher #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 1440adfc5217SJeff Kirsher #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1441adfc5217SJeff Kirsher #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 14429bc297eaSNithin Sujir #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000 14439bc297eaSNithin Sujir #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000 1444091f0ea3SMichael Chan /* 0x4914 --> 0x4be0 unused */ 1445091f0ea3SMichael Chan 1446091f0ea3SMichael Chan #define TG3_NUM_RDMA_CHANNELS 4 1447091f0ea3SMichael Chan #define TG3_RDMA_LENGTH 0x00004be0 1448adfc5217SJeff Kirsher 1449adfc5217SJeff Kirsher /* Write DMA control registers */ 1450adfc5217SJeff Kirsher #define WDMAC_MODE 0x00004c00 1451adfc5217SJeff Kirsher #define WDMAC_MODE_RESET 0x00000001 1452adfc5217SJeff Kirsher #define WDMAC_MODE_ENABLE 0x00000002 1453adfc5217SJeff Kirsher #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1454adfc5217SJeff Kirsher #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1455adfc5217SJeff Kirsher #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1456adfc5217SJeff Kirsher #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1457adfc5217SJeff Kirsher #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1458adfc5217SJeff Kirsher #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1459adfc5217SJeff Kirsher #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1460adfc5217SJeff Kirsher #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1461adfc5217SJeff Kirsher #define WDMAC_MODE_RX_ACCEL 0x00000400 1462adfc5217SJeff Kirsher #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1463adfc5217SJeff Kirsher #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1464adfc5217SJeff Kirsher #define WDMAC_STATUS 0x00004c04 1465adfc5217SJeff Kirsher #define WDMAC_STATUS_TGTABORT 0x00000004 1466adfc5217SJeff Kirsher #define WDMAC_STATUS_MSTABORT 0x00000008 1467adfc5217SJeff Kirsher #define WDMAC_STATUS_PARITYERR 0x00000010 1468adfc5217SJeff Kirsher #define WDMAC_STATUS_ADDROFLOW 0x00000020 1469adfc5217SJeff Kirsher #define WDMAC_STATUS_FIFOOFLOW 0x00000040 1470adfc5217SJeff Kirsher #define WDMAC_STATUS_FIFOURUN 0x00000080 1471adfc5217SJeff Kirsher #define WDMAC_STATUS_FIFOOREAD 0x00000100 1472adfc5217SJeff Kirsher #define WDMAC_STATUS_LNGREAD 0x00000200 1473adfc5217SJeff Kirsher /* 0x4c08 --> 0x5000 unused */ 1474adfc5217SJeff Kirsher 1475adfc5217SJeff Kirsher /* Per-cpu register offsets (arm9) */ 1476adfc5217SJeff Kirsher #define CPU_MODE 0x00000000 1477adfc5217SJeff Kirsher #define CPU_MODE_RESET 0x00000001 1478adfc5217SJeff Kirsher #define CPU_MODE_HALT 0x00000400 1479adfc5217SJeff Kirsher #define CPU_STATE 0x00000004 1480adfc5217SJeff Kirsher #define CPU_EVTMASK 0x00000008 1481adfc5217SJeff Kirsher /* 0xc --> 0x1c reserved */ 1482adfc5217SJeff Kirsher #define CPU_PC 0x0000001c 1483adfc5217SJeff Kirsher #define CPU_INSN 0x00000020 1484adfc5217SJeff Kirsher #define CPU_SPAD_UFLOW 0x00000024 1485adfc5217SJeff Kirsher #define CPU_WDOG_CLEAR 0x00000028 1486adfc5217SJeff Kirsher #define CPU_WDOG_VECTOR 0x0000002c 1487adfc5217SJeff Kirsher #define CPU_WDOG_PC 0x00000030 1488adfc5217SJeff Kirsher #define CPU_HW_BP 0x00000034 1489adfc5217SJeff Kirsher /* 0x38 --> 0x44 unused */ 1490adfc5217SJeff Kirsher #define CPU_WDOG_SAVED_STATE 0x00000044 1491adfc5217SJeff Kirsher #define CPU_LAST_BRANCH_ADDR 0x00000048 1492adfc5217SJeff Kirsher #define CPU_SPAD_UFLOW_SET 0x0000004c 1493adfc5217SJeff Kirsher /* 0x50 --> 0x200 unused */ 1494adfc5217SJeff Kirsher #define CPU_R0 0x00000200 1495adfc5217SJeff Kirsher #define CPU_R1 0x00000204 1496adfc5217SJeff Kirsher #define CPU_R2 0x00000208 1497adfc5217SJeff Kirsher #define CPU_R3 0x0000020c 1498adfc5217SJeff Kirsher #define CPU_R4 0x00000210 1499adfc5217SJeff Kirsher #define CPU_R5 0x00000214 1500adfc5217SJeff Kirsher #define CPU_R6 0x00000218 1501adfc5217SJeff Kirsher #define CPU_R7 0x0000021c 1502adfc5217SJeff Kirsher #define CPU_R8 0x00000220 1503adfc5217SJeff Kirsher #define CPU_R9 0x00000224 1504adfc5217SJeff Kirsher #define CPU_R10 0x00000228 1505adfc5217SJeff Kirsher #define CPU_R11 0x0000022c 1506adfc5217SJeff Kirsher #define CPU_R12 0x00000230 1507adfc5217SJeff Kirsher #define CPU_R13 0x00000234 1508adfc5217SJeff Kirsher #define CPU_R14 0x00000238 1509adfc5217SJeff Kirsher #define CPU_R15 0x0000023c 1510adfc5217SJeff Kirsher #define CPU_R16 0x00000240 1511adfc5217SJeff Kirsher #define CPU_R17 0x00000244 1512adfc5217SJeff Kirsher #define CPU_R18 0x00000248 1513adfc5217SJeff Kirsher #define CPU_R19 0x0000024c 1514adfc5217SJeff Kirsher #define CPU_R20 0x00000250 1515adfc5217SJeff Kirsher #define CPU_R21 0x00000254 1516adfc5217SJeff Kirsher #define CPU_R22 0x00000258 1517adfc5217SJeff Kirsher #define CPU_R23 0x0000025c 1518adfc5217SJeff Kirsher #define CPU_R24 0x00000260 1519adfc5217SJeff Kirsher #define CPU_R25 0x00000264 1520adfc5217SJeff Kirsher #define CPU_R26 0x00000268 1521adfc5217SJeff Kirsher #define CPU_R27 0x0000026c 1522adfc5217SJeff Kirsher #define CPU_R28 0x00000270 1523adfc5217SJeff Kirsher #define CPU_R29 0x00000274 1524adfc5217SJeff Kirsher #define CPU_R30 0x00000278 1525adfc5217SJeff Kirsher #define CPU_R31 0x0000027c 1526adfc5217SJeff Kirsher /* 0x280 --> 0x400 unused */ 1527adfc5217SJeff Kirsher 1528adfc5217SJeff Kirsher #define RX_CPU_BASE 0x00005000 1529adfc5217SJeff Kirsher #define RX_CPU_MODE 0x00005000 1530adfc5217SJeff Kirsher #define RX_CPU_STATE 0x00005004 1531adfc5217SJeff Kirsher #define RX_CPU_PGMCTR 0x0000501c 1532adfc5217SJeff Kirsher #define RX_CPU_HWBKPT 0x00005034 1533adfc5217SJeff Kirsher #define TX_CPU_BASE 0x00005400 1534adfc5217SJeff Kirsher #define TX_CPU_MODE 0x00005400 1535adfc5217SJeff Kirsher #define TX_CPU_STATE 0x00005404 1536adfc5217SJeff Kirsher #define TX_CPU_PGMCTR 0x0000541c 1537adfc5217SJeff Kirsher 1538adfc5217SJeff Kirsher #define VCPU_STATUS 0x00005100 1539adfc5217SJeff Kirsher #define VCPU_STATUS_INIT_DONE 0x04000000 1540adfc5217SJeff Kirsher #define VCPU_STATUS_DRV_RESET 0x08000000 1541adfc5217SJeff Kirsher 1542adfc5217SJeff Kirsher #define VCPU_CFGSHDW 0x00005104 1543adfc5217SJeff Kirsher #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1544adfc5217SJeff Kirsher #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1545adfc5217SJeff Kirsher #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1546adfc5217SJeff Kirsher 1547adfc5217SJeff Kirsher /* Mailboxes */ 1548adfc5217SJeff Kirsher #define GRCMBOX_BASE 0x00005600 1549adfc5217SJeff Kirsher #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1550adfc5217SJeff Kirsher #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1551adfc5217SJeff Kirsher #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1552adfc5217SJeff Kirsher #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1553adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1554adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1555adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1556adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1557adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1558adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1559adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1560adfc5217SJeff Kirsher #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1561adfc5217SJeff Kirsher #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1562adfc5217SJeff Kirsher #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1563adfc5217SJeff Kirsher #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1564adfc5217SJeff Kirsher #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1565adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1566adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1567adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1568adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1569adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1570adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1571adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1572adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1573adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1574adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1575adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1576adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1577adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1578adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1579adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1580adfc5217SJeff Kirsher #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1581adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1582adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1583adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1584adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1585adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1586adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1587adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1588adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1589adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1590adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1591adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1592adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1593adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1594adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1595adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1596adfc5217SJeff Kirsher #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1597adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1598adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1599adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1600adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1601adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1602adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1603adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1604adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1605adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1606adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1607adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1608adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1609adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1610adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1611adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1612adfc5217SJeff Kirsher #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1613adfc5217SJeff Kirsher #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1614adfc5217SJeff Kirsher #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1615adfc5217SJeff Kirsher #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1616adfc5217SJeff Kirsher #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1617adfc5217SJeff Kirsher /* 0x5a10 --> 0x5c00 */ 1618adfc5217SJeff Kirsher 1619adfc5217SJeff Kirsher /* Flow Through queues */ 1620adfc5217SJeff Kirsher #define FTQ_RESET 0x00005c00 1621adfc5217SJeff Kirsher /* 0x5c04 --> 0x5c10 unused */ 1622adfc5217SJeff Kirsher #define FTQ_DMA_NORM_READ_CTL 0x00005c10 1623adfc5217SJeff Kirsher #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1624adfc5217SJeff Kirsher #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1625adfc5217SJeff Kirsher #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1626adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1627adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1628adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1629adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1630adfc5217SJeff Kirsher #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1631adfc5217SJeff Kirsher #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1632adfc5217SJeff Kirsher #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1633adfc5217SJeff Kirsher #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1634adfc5217SJeff Kirsher #define FTQ_SEND_BD_COMP_CTL 0x00005c40 1635adfc5217SJeff Kirsher #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1636adfc5217SJeff Kirsher #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1637adfc5217SJeff Kirsher #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1638adfc5217SJeff Kirsher #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1639adfc5217SJeff Kirsher #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1640adfc5217SJeff Kirsher #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1641adfc5217SJeff Kirsher #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1642adfc5217SJeff Kirsher #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1643adfc5217SJeff Kirsher #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1644adfc5217SJeff Kirsher #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1645adfc5217SJeff Kirsher #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1646adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1647adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1648adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1649adfc5217SJeff Kirsher #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1650adfc5217SJeff Kirsher #define FTQ_SWTYPE1_CTL 0x00005c80 1651adfc5217SJeff Kirsher #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1652adfc5217SJeff Kirsher #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1653adfc5217SJeff Kirsher #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1654adfc5217SJeff Kirsher #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1655adfc5217SJeff Kirsher #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1656adfc5217SJeff Kirsher #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1657adfc5217SJeff Kirsher #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1658adfc5217SJeff Kirsher #define FTQ_HOST_COAL_CTL 0x00005ca0 1659adfc5217SJeff Kirsher #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1660adfc5217SJeff Kirsher #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1661adfc5217SJeff Kirsher #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1662adfc5217SJeff Kirsher #define FTQ_MAC_TX_CTL 0x00005cb0 1663adfc5217SJeff Kirsher #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1664adfc5217SJeff Kirsher #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1665adfc5217SJeff Kirsher #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1666adfc5217SJeff Kirsher #define FTQ_MB_FREE_CTL 0x00005cc0 1667adfc5217SJeff Kirsher #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1668adfc5217SJeff Kirsher #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1669adfc5217SJeff Kirsher #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1670adfc5217SJeff Kirsher #define FTQ_RCVBD_COMP_CTL 0x00005cd0 1671adfc5217SJeff Kirsher #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1672adfc5217SJeff Kirsher #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1673adfc5217SJeff Kirsher #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1674adfc5217SJeff Kirsher #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1675adfc5217SJeff Kirsher #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1676adfc5217SJeff Kirsher #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1677adfc5217SJeff Kirsher #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1678adfc5217SJeff Kirsher #define FTQ_RCVDATA_INI_CTL 0x00005cf0 1679adfc5217SJeff Kirsher #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1680adfc5217SJeff Kirsher #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1681adfc5217SJeff Kirsher #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1682adfc5217SJeff Kirsher #define FTQ_RCVDATA_COMP_CTL 0x00005d00 1683adfc5217SJeff Kirsher #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1684adfc5217SJeff Kirsher #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1685adfc5217SJeff Kirsher #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1686adfc5217SJeff Kirsher #define FTQ_SWTYPE2_CTL 0x00005d10 1687adfc5217SJeff Kirsher #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1688adfc5217SJeff Kirsher #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1689adfc5217SJeff Kirsher #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1690adfc5217SJeff Kirsher /* 0x5d20 --> 0x6000 unused */ 1691adfc5217SJeff Kirsher 1692adfc5217SJeff Kirsher /* Message signaled interrupt registers */ 1693adfc5217SJeff Kirsher #define MSGINT_MODE 0x00006000 1694adfc5217SJeff Kirsher #define MSGINT_MODE_RESET 0x00000001 1695adfc5217SJeff Kirsher #define MSGINT_MODE_ENABLE 0x00000002 1696adfc5217SJeff Kirsher #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1697adfc5217SJeff Kirsher #define MSGINT_MODE_MULTIVEC_EN 0x00000080 1698adfc5217SJeff Kirsher #define MSGINT_STATUS 0x00006004 1699adfc5217SJeff Kirsher #define MSGINT_STATUS_MSI_REQ 0x00000001 1700adfc5217SJeff Kirsher #define MSGINT_FIFO 0x00006008 1701adfc5217SJeff Kirsher /* 0x600c --> 0x6400 unused */ 1702adfc5217SJeff Kirsher 1703adfc5217SJeff Kirsher /* DMA completion registers */ 1704adfc5217SJeff Kirsher #define DMAC_MODE 0x00006400 1705adfc5217SJeff Kirsher #define DMAC_MODE_RESET 0x00000001 1706adfc5217SJeff Kirsher #define DMAC_MODE_ENABLE 0x00000002 1707adfc5217SJeff Kirsher /* 0x6404 --> 0x6800 unused */ 1708adfc5217SJeff Kirsher 1709adfc5217SJeff Kirsher /* GRC registers */ 1710adfc5217SJeff Kirsher #define GRC_MODE 0x00006800 1711adfc5217SJeff Kirsher #define GRC_MODE_UPD_ON_COAL 0x00000001 1712adfc5217SJeff Kirsher #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1713adfc5217SJeff Kirsher #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1714adfc5217SJeff Kirsher #define GRC_MODE_BSWAP_DATA 0x00000010 1715adfc5217SJeff Kirsher #define GRC_MODE_WSWAP_DATA 0x00000020 1716adfc5217SJeff Kirsher #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040 1717adfc5217SJeff Kirsher #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080 1718adfc5217SJeff Kirsher #define GRC_MODE_SPLITHDR 0x00000100 1719adfc5217SJeff Kirsher #define GRC_MODE_NOFRM_CRACKING 0x00000200 1720adfc5217SJeff Kirsher #define GRC_MODE_INCL_CRC 0x00000400 1721adfc5217SJeff Kirsher #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1722adfc5217SJeff Kirsher #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1723adfc5217SJeff Kirsher #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1724adfc5217SJeff Kirsher #define GRC_MODE_FORCE_PCI32BIT 0x00008000 1725adfc5217SJeff Kirsher #define GRC_MODE_B2HRX_ENABLE 0x00008000 1726adfc5217SJeff Kirsher #define GRC_MODE_HOST_STACKUP 0x00010000 1727adfc5217SJeff Kirsher #define GRC_MODE_HOST_SENDBDS 0x00020000 1728adfc5217SJeff Kirsher #define GRC_MODE_HTX2B_ENABLE 0x00040000 1729be947307SMatt Carlson #define GRC_MODE_TIME_SYNC_ENABLE 0x00080000 1730adfc5217SJeff Kirsher #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1731adfc5217SJeff Kirsher #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1732adfc5217SJeff Kirsher #define GRC_MODE_PCIE_TL_SEL 0x00000000 1733adfc5217SJeff Kirsher #define GRC_MODE_PCIE_PL_SEL 0x00400000 1734adfc5217SJeff Kirsher #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1735adfc5217SJeff Kirsher #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1736adfc5217SJeff Kirsher #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1737adfc5217SJeff Kirsher #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1738adfc5217SJeff Kirsher #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1739adfc5217SJeff Kirsher #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1740adfc5217SJeff Kirsher #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1741adfc5217SJeff Kirsher #define GRC_MODE_PCIE_DL_SEL 0x20000000 1742adfc5217SJeff Kirsher #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1743adfc5217SJeff Kirsher #define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1744adfc5217SJeff Kirsher #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1745adfc5217SJeff Kirsher GRC_MODE_PCIE_PL_SEL | \ 1746adfc5217SJeff Kirsher GRC_MODE_PCIE_DL_SEL | \ 1747adfc5217SJeff Kirsher GRC_MODE_PCIE_HI_1K_EN) 1748adfc5217SJeff Kirsher #define GRC_MISC_CFG 0x00006804 1749adfc5217SJeff Kirsher #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1750adfc5217SJeff Kirsher #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1751adfc5217SJeff Kirsher #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1752adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1753adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1754adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1755adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1756adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1757adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1758adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1759adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1760adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1761adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1762adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1763adfc5217SJeff Kirsher #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1764adfc5217SJeff Kirsher #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1765adfc5217SJeff Kirsher #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1766adfc5217SJeff Kirsher #define GRC_LOCAL_CTRL 0x00006808 1767adfc5217SJeff Kirsher #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1768adfc5217SJeff Kirsher #define GRC_LCLCTRL_CLEARINT 0x00000002 1769adfc5217SJeff Kirsher #define GRC_LCLCTRL_SETINT 0x00000004 1770adfc5217SJeff Kirsher #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1771adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1772adfc5217SJeff Kirsher #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1773adfc5217SJeff Kirsher #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1774adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1775adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OE3 0x00000040 1776adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1777adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1778adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1779adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1780adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OE0 0x00000800 1781adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OE1 0x00001000 1782adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OE2 0x00002000 1783adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1784adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1785adfc5217SJeff Kirsher #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1786adfc5217SJeff Kirsher #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1787adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1788adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1789adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1790adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1791adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1792adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1793adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1794adfc5217SJeff Kirsher #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1795adfc5217SJeff Kirsher #define GRC_LCLCTRL_BANK_SELECT 0x00200000 1796adfc5217SJeff Kirsher #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1797adfc5217SJeff Kirsher #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1798adfc5217SJeff Kirsher #define GRC_TIMER 0x0000680c 1799adfc5217SJeff Kirsher #define GRC_RX_CPU_EVENT 0x00006810 1800adfc5217SJeff Kirsher #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1801adfc5217SJeff Kirsher #define GRC_RX_TIMER_REF 0x00006814 1802adfc5217SJeff Kirsher #define GRC_RX_CPU_SEM 0x00006818 1803adfc5217SJeff Kirsher #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1804adfc5217SJeff Kirsher #define GRC_TX_CPU_EVENT 0x00006820 1805adfc5217SJeff Kirsher #define GRC_TX_TIMER_REF 0x00006824 1806adfc5217SJeff Kirsher #define GRC_TX_CPU_SEM 0x00006828 1807adfc5217SJeff Kirsher #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1808adfc5217SJeff Kirsher #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1809adfc5217SJeff Kirsher #define GRC_EEPROM_ADDR 0x00006838 1810adfc5217SJeff Kirsher #define EEPROM_ADDR_WRITE 0x00000000 1811adfc5217SJeff Kirsher #define EEPROM_ADDR_READ 0x80000000 1812adfc5217SJeff Kirsher #define EEPROM_ADDR_COMPLETE 0x40000000 1813adfc5217SJeff Kirsher #define EEPROM_ADDR_FSM_RESET 0x20000000 1814adfc5217SJeff Kirsher #define EEPROM_ADDR_DEVID_MASK 0x1c000000 1815adfc5217SJeff Kirsher #define EEPROM_ADDR_DEVID_SHIFT 26 1816adfc5217SJeff Kirsher #define EEPROM_ADDR_START 0x02000000 1817adfc5217SJeff Kirsher #define EEPROM_ADDR_CLKPERD_SHIFT 16 1818adfc5217SJeff Kirsher #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1819adfc5217SJeff Kirsher #define EEPROM_ADDR_ADDR_SHIFT 0 1820adfc5217SJeff Kirsher #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1821adfc5217SJeff Kirsher #define EEPROM_CHIP_SIZE (64 * 1024) 1822adfc5217SJeff Kirsher #define GRC_EEPROM_DATA 0x0000683c 1823adfc5217SJeff Kirsher #define GRC_EEPROM_CTRL 0x00006840 1824adfc5217SJeff Kirsher #define GRC_MDI_CTRL 0x00006844 1825adfc5217SJeff Kirsher #define GRC_SEEPROM_DELAY 0x00006848 1826adfc5217SJeff Kirsher /* 0x684c --> 0x6890 unused */ 1827adfc5217SJeff Kirsher #define GRC_VCPU_EXT_CTRL 0x00006890 1828adfc5217SJeff Kirsher #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1829adfc5217SJeff Kirsher #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1830adfc5217SJeff Kirsher #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1831adfc5217SJeff Kirsher 1832be947307SMatt Carlson #define TG3_EAV_REF_CLCK_LSB 0x00006900 1833be947307SMatt Carlson #define TG3_EAV_REF_CLCK_MSB 0x00006904 1834be947307SMatt Carlson #define TG3_EAV_REF_CLCK_CTL 0x00006908 1835be947307SMatt Carlson #define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002 1836be947307SMatt Carlson #define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004 183792e6457dSNithin Sujir #define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16) 183892e6457dSNithin Sujir #define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17) 183992e6457dSNithin Sujir 184092e6457dSNithin Sujir #define TG3_EAV_WATCHDOG0_LSB 0x00006918 184192e6457dSNithin Sujir #define TG3_EAV_WATCHDOG0_MSB 0x0000691c 184292e6457dSNithin Sujir #define TG3_EAV_WATCHDOG0_EN (1 << 31) 184392e6457dSNithin Sujir #define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff 184492e6457dSNithin Sujir 1845be947307SMatt Carlson #define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928 1846be947307SMatt Carlson #define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31) 1847be947307SMatt Carlson #define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30) 1848be947307SMatt Carlson 1849be947307SMatt Carlson #define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff 185092e6457dSNithin Sujir 185192e6457dSNithin Sujir /* 0x692c --> 0x7000 unused */ 1852adfc5217SJeff Kirsher 1853adfc5217SJeff Kirsher /* NVRAM Control registers */ 1854adfc5217SJeff Kirsher #define NVRAM_CMD 0x00007000 1855adfc5217SJeff Kirsher #define NVRAM_CMD_RESET 0x00000001 1856adfc5217SJeff Kirsher #define NVRAM_CMD_DONE 0x00000008 1857adfc5217SJeff Kirsher #define NVRAM_CMD_GO 0x00000010 1858adfc5217SJeff Kirsher #define NVRAM_CMD_WR 0x00000020 1859adfc5217SJeff Kirsher #define NVRAM_CMD_RD 0x00000000 1860adfc5217SJeff Kirsher #define NVRAM_CMD_ERASE 0x00000040 1861adfc5217SJeff Kirsher #define NVRAM_CMD_FIRST 0x00000080 1862adfc5217SJeff Kirsher #define NVRAM_CMD_LAST 0x00000100 1863adfc5217SJeff Kirsher #define NVRAM_CMD_WREN 0x00010000 1864adfc5217SJeff Kirsher #define NVRAM_CMD_WRDI 0x00020000 1865adfc5217SJeff Kirsher #define NVRAM_STAT 0x00007004 1866adfc5217SJeff Kirsher #define NVRAM_WRDATA 0x00007008 1867adfc5217SJeff Kirsher #define NVRAM_ADDR 0x0000700c 18688a4816caSPrashant Sreedharan #define NVRAM_ADDR_MSK 0x07ffffff 1869adfc5217SJeff Kirsher #define NVRAM_RDDATA 0x00007010 1870adfc5217SJeff Kirsher #define NVRAM_CFG1 0x00007014 1871adfc5217SJeff Kirsher #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1872adfc5217SJeff Kirsher #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1873adfc5217SJeff Kirsher #define NVRAM_CFG1_PASS_THRU 0x00000004 1874adfc5217SJeff Kirsher #define NVRAM_CFG1_STATUS_BITS 0x00000070 1875adfc5217SJeff Kirsher #define NVRAM_CFG1_BIT_BANG 0x00000008 1876adfc5217SJeff Kirsher #define NVRAM_CFG1_FLASH_SIZE 0x02000000 1877adfc5217SJeff Kirsher #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1878adfc5217SJeff Kirsher #define NVRAM_CFG1_VENDOR_MASK 0x03000003 1879adfc5217SJeff Kirsher #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1880adfc5217SJeff Kirsher #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1881adfc5217SJeff Kirsher #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1882adfc5217SJeff Kirsher #define FLASH_VENDOR_ST 0x03000001 1883adfc5217SJeff Kirsher #define FLASH_VENDOR_SAIFUN 0x01000003 1884adfc5217SJeff Kirsher #define FLASH_VENDOR_SST_SMALL 0x00000001 1885adfc5217SJeff Kirsher #define FLASH_VENDOR_SST_LARGE 0x02000001 1886adfc5217SJeff Kirsher #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1887c86a8560SMichael Chan #define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003 1888adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1889adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1890adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1891adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1892adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1893adfc5217SJeff Kirsher #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1894adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1895adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1896adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1897adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1898adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1899adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1900adfc5217SJeff Kirsher #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1901adfc5217SJeff Kirsher #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1902adfc5217SJeff Kirsher #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1903adfc5217SJeff Kirsher #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1904adfc5217SJeff Kirsher #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1905adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1906adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1907adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1908adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1909adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1910adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1911adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1912adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1913adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1914adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1915adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1916adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1917adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1918adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1919adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1920adfc5217SJeff Kirsher #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1921adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1922adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1923adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1924adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1925adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1926adfc5217SJeff Kirsher #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1927adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1928adfc5217SJeff Kirsher #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1929adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1930adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1931adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1932adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1933adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1934adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1935adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1936adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1937adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1938adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1939adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1940adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1941adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1942adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1943adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1944adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_25USPT 0x03400002 1945adfc5217SJeff Kirsher #define FLASH_5717VENDOR_ST_45USPT 0x03400001 1946adfc5217SJeff Kirsher #define FLASH_5720_EEPROM_HD 0x00000001 1947adfc5217SJeff Kirsher #define FLASH_5720_EEPROM_LD 0x00000003 1948c65a17f4SMichael Chan #define FLASH_5762_EEPROM_HD 0x02000001 1949c65a17f4SMichael Chan #define FLASH_5762_EEPROM_LD 0x02000003 19508a4816caSPrashant Sreedharan #define FLASH_5762_MX25L_100 0x00800000 19518a4816caSPrashant Sreedharan #define FLASH_5762_MX25L_200 0x00800002 19528a4816caSPrashant Sreedharan #define FLASH_5762_MX25L_400 0x00800001 19538a4816caSPrashant Sreedharan #define FLASH_5762_MX25L_800 0x00800003 19548a4816caSPrashant Sreedharan #define FLASH_5762_MX25L_160_320 0x03800002 1955adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000 1956adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002 1957adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001 1958adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003 1959adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000 1960adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002 1961adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001 1962adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003 1963adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000 1964adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002 1965adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001 1966adfc5217SJeff Kirsher #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003 1967adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000 1968adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002 1969adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001 1970adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000 1971adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002 1972adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001 1973adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003 1974adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000 1975adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002 1976adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001 1977adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003 1978adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000 1979adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002 1980adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001 1981adfc5217SJeff Kirsher #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003 1982adfc5217SJeff Kirsher #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000 1983adfc5217SJeff Kirsher #define FLASH_5720VENDOR_ST_25USPT 0x03c00002 1984adfc5217SJeff Kirsher #define FLASH_5720VENDOR_ST_45USPT 0x03c00001 1985adfc5217SJeff Kirsher #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1986adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_256 0x00000000 1987adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_512 0x10000000 1988adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_1K 0x20000000 1989adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_2K 0x30000000 1990adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_4K 0x40000000 1991adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_264 0x50000000 1992adfc5217SJeff Kirsher #define FLASH_5752PAGE_SIZE_528 0x60000000 1993adfc5217SJeff Kirsher #define NVRAM_CFG2 0x00007018 1994adfc5217SJeff Kirsher #define NVRAM_CFG3 0x0000701c 1995adfc5217SJeff Kirsher #define NVRAM_SWARB 0x00007020 1996adfc5217SJeff Kirsher #define SWARB_REQ_SET0 0x00000001 1997adfc5217SJeff Kirsher #define SWARB_REQ_SET1 0x00000002 1998adfc5217SJeff Kirsher #define SWARB_REQ_SET2 0x00000004 1999adfc5217SJeff Kirsher #define SWARB_REQ_SET3 0x00000008 2000adfc5217SJeff Kirsher #define SWARB_REQ_CLR0 0x00000010 2001adfc5217SJeff Kirsher #define SWARB_REQ_CLR1 0x00000020 2002adfc5217SJeff Kirsher #define SWARB_REQ_CLR2 0x00000040 2003adfc5217SJeff Kirsher #define SWARB_REQ_CLR3 0x00000080 2004adfc5217SJeff Kirsher #define SWARB_GNT0 0x00000100 2005adfc5217SJeff Kirsher #define SWARB_GNT1 0x00000200 2006adfc5217SJeff Kirsher #define SWARB_GNT2 0x00000400 2007adfc5217SJeff Kirsher #define SWARB_GNT3 0x00000800 2008adfc5217SJeff Kirsher #define SWARB_REQ0 0x00001000 2009adfc5217SJeff Kirsher #define SWARB_REQ1 0x00002000 2010adfc5217SJeff Kirsher #define SWARB_REQ2 0x00004000 2011adfc5217SJeff Kirsher #define SWARB_REQ3 0x00008000 2012adfc5217SJeff Kirsher #define NVRAM_ACCESS 0x00007024 2013adfc5217SJeff Kirsher #define ACCESS_ENABLE 0x00000001 2014adfc5217SJeff Kirsher #define ACCESS_WR_ENABLE 0x00000002 2015adfc5217SJeff Kirsher #define NVRAM_WRITE1 0x00007028 2016adfc5217SJeff Kirsher /* 0x702c unused */ 2017adfc5217SJeff Kirsher 2018adfc5217SJeff Kirsher #define NVRAM_ADDR_LOCKOUT 0x00007030 20198a4816caSPrashant Sreedharan #define NVRAM_AUTOSENSE_STATUS 0x00007038 20208a4816caSPrashant Sreedharan #define AUTOSENSE_DEVID 0x00000010 20218a4816caSPrashant Sreedharan #define AUTOSENSE_DEVID_MASK 0x00000007 20228a4816caSPrashant Sreedharan #define AUTOSENSE_SIZE_IN_MB 17 20238a4816caSPrashant Sreedharan /* 0x703c --> 0x7500 unused */ 2024adfc5217SJeff Kirsher 2025adfc5217SJeff Kirsher #define OTP_MODE 0x00007500 2026adfc5217SJeff Kirsher #define OTP_MODE_OTP_THRU_GRC 0x00000001 2027adfc5217SJeff Kirsher #define OTP_CTRL 0x00007504 2028adfc5217SJeff Kirsher #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 2029adfc5217SJeff Kirsher #define OTP_CTRL_OTP_CMD_READ 0x00000000 2030adfc5217SJeff Kirsher #define OTP_CTRL_OTP_CMD_INIT 0x00000008 2031adfc5217SJeff Kirsher #define OTP_CTRL_OTP_CMD_START 0x00000001 2032adfc5217SJeff Kirsher #define OTP_STATUS 0x00007508 2033adfc5217SJeff Kirsher #define OTP_STATUS_CMD_DONE 0x00000001 2034adfc5217SJeff Kirsher #define OTP_ADDRESS 0x0000750c 2035adfc5217SJeff Kirsher #define OTP_ADDRESS_MAGIC1 0x000000a0 2036adfc5217SJeff Kirsher #define OTP_ADDRESS_MAGIC2 0x00000080 2037adfc5217SJeff Kirsher /* 0x7510 unused */ 2038adfc5217SJeff Kirsher 2039adfc5217SJeff Kirsher #define OTP_READ_DATA 0x00007514 2040adfc5217SJeff Kirsher /* 0x7518 --> 0x7c04 unused */ 2041adfc5217SJeff Kirsher 2042adfc5217SJeff Kirsher #define PCIE_TRANSACTION_CFG 0x00007c04 2043adfc5217SJeff Kirsher #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 2044adfc5217SJeff Kirsher #define PCIE_TRANS_CFG_LOM 0x00000020 2045adfc5217SJeff Kirsher /* 0x7c08 --> 0x7d28 unused */ 2046adfc5217SJeff Kirsher 2047adfc5217SJeff Kirsher #define PCIE_PWR_MGMT_THRESH 0x00007d28 2048adfc5217SJeff Kirsher #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 2049adfc5217SJeff Kirsher #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 2050adfc5217SJeff Kirsher #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 2051adfc5217SJeff Kirsher /* 0x7d2c --> 0x7d54 unused */ 2052adfc5217SJeff Kirsher 2053adfc5217SJeff Kirsher #define TG3_PCIE_LNKCTL 0x00007d54 2054adfc5217SJeff Kirsher #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 2055adfc5217SJeff Kirsher #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 2056adfc5217SJeff Kirsher /* 0x7d58 --> 0x7e70 unused */ 2057adfc5217SJeff Kirsher 2058adfc5217SJeff Kirsher #define TG3_PCIE_PHY_TSTCTL 0x00007e2c 2059adfc5217SJeff Kirsher #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2060adfc5217SJeff Kirsher #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2061adfc5217SJeff Kirsher 2062adfc5217SJeff Kirsher #define TG3_PCIE_EIDLE_DELAY 0x00007e70 2063adfc5217SJeff Kirsher #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 2064adfc5217SJeff Kirsher #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 2065adfc5217SJeff Kirsher /* 0x7e74 --> 0x8000 unused */ 2066adfc5217SJeff Kirsher 2067adfc5217SJeff Kirsher 2068adfc5217SJeff Kirsher /* Alternate PCIE definitions */ 2069adfc5217SJeff Kirsher #define TG3_PCIE_TLDLPL_PORT 0x00007c00 2070adfc5217SJeff Kirsher #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c 2071adfc5217SJeff Kirsher #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff 2072adfc5217SJeff Kirsher #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2073adfc5217SJeff Kirsher #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 2074adfc5217SJeff Kirsher #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 2075adfc5217SJeff Kirsher #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 2076adfc5217SJeff Kirsher #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2077adfc5217SJeff Kirsher 2078adfc5217SJeff Kirsher #define TG3_REG_BLK_SIZE 0x00008000 2079adfc5217SJeff Kirsher 2080adfc5217SJeff Kirsher /* OTP bit definitions */ 2081adfc5217SJeff Kirsher #define TG3_OTP_AGCTGT_MASK 0x000000e0 2082adfc5217SJeff Kirsher #define TG3_OTP_AGCTGT_SHIFT 1 2083adfc5217SJeff Kirsher #define TG3_OTP_HPFFLTR_MASK 0x00000300 2084adfc5217SJeff Kirsher #define TG3_OTP_HPFFLTR_SHIFT 1 2085adfc5217SJeff Kirsher #define TG3_OTP_HPFOVER_MASK 0x00000400 2086adfc5217SJeff Kirsher #define TG3_OTP_HPFOVER_SHIFT 1 2087adfc5217SJeff Kirsher #define TG3_OTP_LPFDIS_MASK 0x00000800 2088adfc5217SJeff Kirsher #define TG3_OTP_LPFDIS_SHIFT 11 2089adfc5217SJeff Kirsher #define TG3_OTP_VDAC_MASK 0xff000000 2090adfc5217SJeff Kirsher #define TG3_OTP_VDAC_SHIFT 24 2091adfc5217SJeff Kirsher #define TG3_OTP_10BTAMP_MASK 0x0000f000 2092adfc5217SJeff Kirsher #define TG3_OTP_10BTAMP_SHIFT 8 2093adfc5217SJeff Kirsher #define TG3_OTP_ROFF_MASK 0x00e00000 2094adfc5217SJeff Kirsher #define TG3_OTP_ROFF_SHIFT 11 2095adfc5217SJeff Kirsher #define TG3_OTP_RCOFF_MASK 0x001c0000 2096adfc5217SJeff Kirsher #define TG3_OTP_RCOFF_SHIFT 16 2097adfc5217SJeff Kirsher 2098adfc5217SJeff Kirsher #define TG3_OTP_DEFAULT 0x286c1640 2099adfc5217SJeff Kirsher 2100adfc5217SJeff Kirsher 2101adfc5217SJeff Kirsher /* Hardware Legacy NVRAM layout */ 2102adfc5217SJeff Kirsher #define TG3_NVM_VPD_OFF 0x100 2103adfc5217SJeff Kirsher #define TG3_NVM_VPD_LEN 256 2104adfc5217SJeff Kirsher 2105adfc5217SJeff Kirsher /* Hardware Selfboot NVRAM layout */ 2106adfc5217SJeff Kirsher #define TG3_NVM_HWSB_CFG1 0x00000004 2107adfc5217SJeff Kirsher #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 2108adfc5217SJeff Kirsher #define TG3_NVM_HWSB_CFG1_MAJSFT 27 2109adfc5217SJeff Kirsher #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 2110adfc5217SJeff Kirsher #define TG3_NVM_HWSB_CFG1_MINSFT 22 2111adfc5217SJeff Kirsher 2112adfc5217SJeff Kirsher #define TG3_EEPROM_MAGIC 0x669955aa 2113adfc5217SJeff Kirsher #define TG3_EEPROM_MAGIC_FW 0xa5000000 2114adfc5217SJeff Kirsher #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 2115adfc5217SJeff Kirsher #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 2116adfc5217SJeff Kirsher #define TG3_EEPROM_SB_FORMAT_1 0x00200000 2117adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 2118adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_0 0x00000000 2119adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_2 0x00020000 2120adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_3 0x00030000 2121adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_4 0x00040000 2122adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_5 0x00050000 2123adfc5217SJeff Kirsher #define TG3_EEPROM_SB_REVISION_6 0x00060000 2124adfc5217SJeff Kirsher #define TG3_EEPROM_MAGIC_HW 0xabcd 2125adfc5217SJeff Kirsher #define TG3_EEPROM_MAGIC_HW_MSK 0xffff 2126adfc5217SJeff Kirsher 2127adfc5217SJeff Kirsher #define TG3_NVM_DIR_START 0x18 2128adfc5217SJeff Kirsher #define TG3_NVM_DIR_END 0x78 2129adfc5217SJeff Kirsher #define TG3_NVM_DIRENT_SIZE 0xc 2130adfc5217SJeff Kirsher #define TG3_NVM_DIRTYPE_SHIFT 24 2131adfc5217SJeff Kirsher #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff 2132adfc5217SJeff Kirsher #define TG3_NVM_DIRTYPE_ASFINI 1 2133adfc5217SJeff Kirsher #define TG3_NVM_DIRTYPE_EXTVPD 20 2134adfc5217SJeff Kirsher #define TG3_NVM_PTREV_BCVER 0x94 2135adfc5217SJeff Kirsher #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 2136adfc5217SJeff Kirsher #define TG3_NVM_BCVER_MAJSFT 8 2137adfc5217SJeff Kirsher #define TG3_NVM_BCVER_MINMSK 0x000000ff 2138adfc5217SJeff Kirsher 2139adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 2140adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 2141adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2142adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 2143adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 2144adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 2145adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c 2146adfc5217SJeff Kirsher #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 2147adfc5217SJeff Kirsher #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 2148adfc5217SJeff Kirsher #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 2149adfc5217SJeff Kirsher #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 2150adfc5217SJeff Kirsher #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 2151adfc5217SJeff Kirsher 2152adfc5217SJeff Kirsher 2153adfc5217SJeff Kirsher /* 32K Window into NIC internal memory */ 2154adfc5217SJeff Kirsher #define NIC_SRAM_WIN_BASE 0x00008000 2155adfc5217SJeff Kirsher 2156adfc5217SJeff Kirsher /* Offsets into first 32k of NIC internal memory. */ 2157adfc5217SJeff Kirsher #define NIC_SRAM_PAGE_ZERO 0x00000000 2158adfc5217SJeff Kirsher #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 2159adfc5217SJeff Kirsher #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 2160adfc5217SJeff Kirsher #define NIC_SRAM_STATS_BLK 0x00000300 2161adfc5217SJeff Kirsher #define NIC_SRAM_STATUS_BLK 0x00000b00 2162adfc5217SJeff Kirsher 2163adfc5217SJeff Kirsher #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 2164adfc5217SJeff Kirsher #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 2165adfc5217SJeff Kirsher #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 2166adfc5217SJeff Kirsher 2167adfc5217SJeff Kirsher #define NIC_SRAM_DATA_SIG 0x00000b54 2168adfc5217SJeff Kirsher #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 2169adfc5217SJeff Kirsher 2170adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG 0x00000b58 2171adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 2172adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 2173adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 2174adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 2175adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 2176adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 2177adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 2178adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 2179adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 2180adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 2181adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 2182adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 2183adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 2184adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 2185adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 2186adfc5217SJeff Kirsher 2187adfc5217SJeff Kirsher #define NIC_SRAM_DATA_VER 0x00000b5c 2188adfc5217SJeff Kirsher #define NIC_SRAM_DATA_VER_SHIFT 16 2189adfc5217SJeff Kirsher 2190adfc5217SJeff Kirsher #define NIC_SRAM_DATA_PHY_ID 0x00000b74 2191adfc5217SJeff Kirsher #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 2192adfc5217SJeff Kirsher #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 2193adfc5217SJeff Kirsher 2194adfc5217SJeff Kirsher #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 2195adfc5217SJeff Kirsher #define FWCMD_NICDRV_ALIVE 0x00000001 2196adfc5217SJeff Kirsher #define FWCMD_NICDRV_PAUSE_FW 0x00000002 2197adfc5217SJeff Kirsher #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 2198adfc5217SJeff Kirsher #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 2199adfc5217SJeff Kirsher #define FWCMD_NICDRV_FIX_DMAR 0x00000005 2200adfc5217SJeff Kirsher #define FWCMD_NICDRV_FIX_DMAW 0x00000006 2201adfc5217SJeff Kirsher #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 2202adfc5217SJeff Kirsher #define FWCMD_NICDRV_ALIVE2 0x0000000d 2203adfc5217SJeff Kirsher #define FWCMD_NICDRV_ALIVE3 0x0000000e 2204adfc5217SJeff Kirsher #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 2205adfc5217SJeff Kirsher #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 2206adfc5217SJeff Kirsher #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 2207adfc5217SJeff Kirsher #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 2208adfc5217SJeff Kirsher #define DRV_STATE_START 0x00000001 2209adfc5217SJeff Kirsher #define DRV_STATE_START_DONE 0x80000001 2210adfc5217SJeff Kirsher #define DRV_STATE_UNLOAD 0x00000002 2211adfc5217SJeff Kirsher #define DRV_STATE_UNLOAD_DONE 0x80000002 2212adfc5217SJeff Kirsher #define DRV_STATE_WOL 0x00000003 2213adfc5217SJeff Kirsher #define DRV_STATE_SUSPEND 0x00000004 2214adfc5217SJeff Kirsher 2215adfc5217SJeff Kirsher #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 2216adfc5217SJeff Kirsher 2217adfc5217SJeff Kirsher #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 2218adfc5217SJeff Kirsher #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 2219adfc5217SJeff Kirsher 2220adfc5217SJeff Kirsher #define NIC_SRAM_WOL_MBOX 0x00000d30 2221adfc5217SJeff Kirsher #define WOL_SIGNATURE 0x474c0000 2222adfc5217SJeff Kirsher #define WOL_DRV_STATE_SHUTDOWN 0x00000001 2223adfc5217SJeff Kirsher #define WOL_DRV_WOL 0x00000002 2224adfc5217SJeff Kirsher #define WOL_SET_MAGIC_PKT 0x00000004 2225adfc5217SJeff Kirsher 2226adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_2 0x00000d38 2227adfc5217SJeff Kirsher 2228efe8f0eaSNithin Sujir #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000 2229adfc5217SJeff Kirsher #define SHASTA_EXT_LED_MODE_MASK 0x00018000 2230adfc5217SJeff Kirsher #define SHASTA_EXT_LED_LEGACY 0x00000000 2231adfc5217SJeff Kirsher #define SHASTA_EXT_LED_SHARED 0x00008000 2232adfc5217SJeff Kirsher #define SHASTA_EXT_LED_MAC 0x00010000 2233adfc5217SJeff Kirsher #define SHASTA_EXT_LED_COMBO 0x00018000 2234adfc5217SJeff Kirsher 2235adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_3 0x00000d3c 2236adfc5217SJeff Kirsher #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2237942d1af0SNithin Sujir #define NIC_SRAM_LNK_FLAP_AVOID 0x00400000 2238942d1af0SNithin Sujir #define NIC_SRAM_1G_ON_VAUX_OK 0x00800000 2239adfc5217SJeff Kirsher 2240adfc5217SJeff Kirsher #define NIC_SRAM_DATA_CFG_4 0x00000d60 2241adfc5217SJeff Kirsher #define NIC_SRAM_GMII_MODE 0x00000002 2242adfc5217SJeff Kirsher #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2243adfc5217SJeff Kirsher #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2244adfc5217SJeff Kirsher #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2245adfc5217SJeff Kirsher 22469dc5e342SMatt Carlson #define NIC_SRAM_CPMU_STATUS 0x00000e00 22479dc5e342SMatt Carlson #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c 22489dc5e342SMatt Carlson #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff 22499dc5e342SMatt Carlson 22507c786065SNithin Sujir #define NIC_SRAM_DATA_CFG_5 0x00000e0c 22517c786065SNithin Sujir #define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002 22527c786065SNithin Sujir 2253adfc5217SJeff Kirsher #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2254adfc5217SJeff Kirsher 2255adfc5217SJeff Kirsher #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2256adfc5217SJeff Kirsher #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2257adfc5217SJeff Kirsher #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2258adfc5217SJeff Kirsher #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2259adfc5217SJeff Kirsher #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2260adfc5217SJeff Kirsher #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2261adfc5217SJeff Kirsher #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2262adfc5217SJeff Kirsher #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2263adfc5217SJeff Kirsher #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2264adfc5217SJeff Kirsher #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2265adfc5217SJeff Kirsher 2266c4dab506SNithin Sujir #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000 2267c4dab506SNithin Sujir #define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000 2268c4dab506SNithin Sujir #define TG3_57766_FW_BASE_ADDR 0x00030000 2269c4dab506SNithin Sujir #define TG3_57766_FW_HANDSHAKE 0x0003fccc 2270c4dab506SNithin Sujir #define TG3_SBROM_IN_SERVICE_LOOP 0x51 2271c4dab506SNithin Sujir 2272adfc5217SJeff Kirsher #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 2273adfc5217SJeff Kirsher #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 2274adfc5217SJeff Kirsher #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 2275adfc5217SJeff Kirsher 2276adfc5217SJeff Kirsher #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 2277adfc5217SJeff Kirsher #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 2278adfc5217SJeff Kirsher 2279adfc5217SJeff Kirsher 2280adfc5217SJeff Kirsher /* Currently this is fixed. */ 2281adfc5217SJeff Kirsher #define TG3_PHY_MII_ADDR 0x01 2282adfc5217SJeff Kirsher 2283adfc5217SJeff Kirsher 2284adfc5217SJeff Kirsher /*** Tigon3 specific PHY MII registers. ***/ 2285adfc5217SJeff Kirsher #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ 2286adfc5217SJeff Kirsher #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 2287adfc5217SJeff Kirsher #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ 2288adfc5217SJeff Kirsher 2289adfc5217SJeff Kirsher #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2290adfc5217SJeff Kirsher #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2291adfc5217SJeff Kirsher #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2292adfc5217SJeff Kirsher #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2293adfc5217SJeff Kirsher #define MII_TG3_EXT_CTRL_TBI 0x8000 2294adfc5217SJeff Kirsher 2295adfc5217SJeff Kirsher #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2296e348c5e7SMatt Carlson #define MII_TG3_EXT_STAT_MDIX 0x2000 2297adfc5217SJeff Kirsher #define MII_TG3_EXT_STAT_LPASS 0x0100 2298adfc5217SJeff Kirsher 2299adfc5217SJeff Kirsher #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2300adfc5217SJeff Kirsher #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2301adfc5217SJeff Kirsher #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2302adfc5217SJeff Kirsher #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2303adfc5217SJeff Kirsher 2304adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP1 0x0001 2305adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2306adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP26 0x001a 2307adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP26_ALNOKO 0x0001 2308adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 2309adfc5217SJeff Kirsher #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 2310adfc5217SJeff Kirsher #define MII_TG3_DSP_AADJ1CH0 0x001f 2311adfc5217SJeff Kirsher #define MII_TG3_DSP_CH34TP2 0x4022 2312adfc5217SJeff Kirsher #define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff 2313adfc5217SJeff Kirsher #define MII_TG3_DSP_AADJ1CH3 0x601f 2314adfc5217SJeff Kirsher #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2315adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2316adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP8 0x0f08 2317adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2318adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP8_AEDW 0x0200 2319adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP75 0x0f75 2320adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP96 0x0f96 2321adfc5217SJeff Kirsher #define MII_TG3_DSP_EXP97 0x0f97 2322adfc5217SJeff Kirsher 2323adfc5217SJeff Kirsher #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ 2324adfc5217SJeff Kirsher 2325adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2326adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2327adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2328adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 2329941ec90fSMatt Carlson #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000 2330adfc5217SJeff Kirsher 2331adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2332adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 2333adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2334adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2335adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 2336adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2337adfc5217SJeff Kirsher 2338adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 2339adfc5217SJeff Kirsher 2340adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2341adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 2342adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2343adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 2344adfc5217SJeff Kirsher #define MII_TG3_AUXCTL_MISC_WREN 0x8000 2345adfc5217SJeff Kirsher 2346adfc5217SJeff Kirsher 2347adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ 2348adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_LPASS 0x0004 2349adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_SPDMASK 0x0700 2350adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_10HALF 0x0100 2351adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_10FULL 0x0200 2352adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_100HALF 0x0300 2353adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_100_4 0x0400 2354adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_100FULL 0x0500 2355adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_1000HALF 0x0600 2356adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_1000FULL 0x0700 2357adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_100 0x0008 2358adfc5217SJeff Kirsher #define MII_TG3_AUX_STAT_FULL 0x0001 2359adfc5217SJeff Kirsher 2360adfc5217SJeff Kirsher #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2361adfc5217SJeff Kirsher #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2362adfc5217SJeff Kirsher 2363adfc5217SJeff Kirsher /* ISTAT/IMASK event bits */ 2364adfc5217SJeff Kirsher #define MII_TG3_INT_LINKCHG 0x0002 2365adfc5217SJeff Kirsher #define MII_TG3_INT_SPEEDCHG 0x0004 2366adfc5217SJeff Kirsher #define MII_TG3_INT_DUPLEXCHG 0x0008 2367adfc5217SJeff Kirsher #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2368adfc5217SJeff Kirsher 2369adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW 0x1c 2370adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_WREN 0x8000 2371adfc5217SJeff Kirsher 2372adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2373adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2374adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2375adfc5217SJeff Kirsher 2376adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2377adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2378adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2379adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2380adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2381adfc5217SJeff Kirsher #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2382adfc5217SJeff Kirsher 2383adfc5217SJeff Kirsher #define MII_TG3_TEST1 0x1e 2384adfc5217SJeff Kirsher #define MII_TG3_TEST1_TRIM_EN 0x0010 2385adfc5217SJeff Kirsher #define MII_TG3_TEST1_CRC_EN 0x8000 2386adfc5217SJeff Kirsher 2387adfc5217SJeff Kirsher /* Clause 45 expansion registers */ 2388adfc5217SJeff Kirsher #define TG3_CL45_D7_EEERES_STAT 0x803e 2389adfc5217SJeff Kirsher #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2390adfc5217SJeff Kirsher #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2391adfc5217SJeff Kirsher 2392adfc5217SJeff Kirsher 2393adfc5217SJeff Kirsher /* Fast Ethernet Tranceiver definitions */ 2394adfc5217SJeff Kirsher #define MII_TG3_FET_PTEST 0x17 2395941ec90fSMatt Carlson #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2396941ec90fSMatt Carlson #define MII_TG3_FET_PTEST_TRIM_2 0x0002 2397adfc5217SJeff Kirsher #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2398adfc5217SJeff Kirsher #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2399adfc5217SJeff Kirsher 2400e348c5e7SMatt Carlson #define MII_TG3_FET_GEN_STAT 0x1c 2401e348c5e7SMatt Carlson #define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000 2402e348c5e7SMatt Carlson 2403adfc5217SJeff Kirsher #define MII_TG3_FET_TEST 0x1f 2404adfc5217SJeff Kirsher #define MII_TG3_FET_SHADOW_EN 0x0080 2405adfc5217SJeff Kirsher 2406adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_MISCCTRL 0x10 2407adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2408adfc5217SJeff Kirsher 2409adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2410adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2411adfc5217SJeff Kirsher 2412adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2413adfc5217SJeff Kirsher #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2414adfc5217SJeff Kirsher 241585730a63SMichael Chan /* Serdes PHY Register Definitions */ 241685730a63SMichael Chan #define SERDES_TG3_1000X_STATUS 0x14 241785730a63SMichael Chan #define SERDES_TG3_SGMII_MODE 0x0001 241885730a63SMichael Chan #define SERDES_TG3_LINK_UP 0x0002 241985730a63SMichael Chan #define SERDES_TG3_FULL_DUPLEX 0x0004 242085730a63SMichael Chan #define SERDES_TG3_SPEED_100 0x0008 242185730a63SMichael Chan #define SERDES_TG3_SPEED_1000 0x0010 2422adfc5217SJeff Kirsher 2423adfc5217SJeff Kirsher /* APE registers. Accessible through BAR1 */ 2424adfc5217SJeff Kirsher #define TG3_APE_GPIO_MSG 0x0008 2425adfc5217SJeff Kirsher #define TG3_APE_GPIO_MSG_SHIFT 4 2426adfc5217SJeff Kirsher #define TG3_APE_EVENT 0x000c 2427adfc5217SJeff Kirsher #define APE_EVENT_1 0x00000001 2428adfc5217SJeff Kirsher #define TG3_APE_LOCK_REQ 0x002c 2429adfc5217SJeff Kirsher #define APE_LOCK_REQ_DRIVER 0x00001000 2430adfc5217SJeff Kirsher #define TG3_APE_LOCK_GRANT 0x004c 2431adfc5217SJeff Kirsher #define APE_LOCK_GRANT_DRIVER 0x00001000 2432c86a8560SMichael Chan #define TG3_APE_OTP_CTRL 0x00e8 2433c86a8560SMichael Chan #define APE_OTP_CTRL_PROG_EN 0x200000 2434c86a8560SMichael Chan #define APE_OTP_CTRL_CMD_RD 0x000000 2435c86a8560SMichael Chan #define APE_OTP_CTRL_START 0x000001 2436c86a8560SMichael Chan #define TG3_APE_OTP_STATUS 0x00ec 2437c86a8560SMichael Chan #define APE_OTP_STATUS_CMD_DONE 0x000001 2438c86a8560SMichael Chan #define TG3_APE_OTP_ADDR 0x00f0 2439c86a8560SMichael Chan #define APE_OTP_ADDR_CPU_ENABLE 0x80000000 2440c86a8560SMichael Chan #define TG3_APE_OTP_RD_DATA 0x00f8 2441c86a8560SMichael Chan 2442c86a8560SMichael Chan #define OTP_ADDRESS_MAGIC0 0x00000050 2443c86a8560SMichael Chan #define TG3_OTP_MAGIC0_VALID(val) \ 2444c86a8560SMichael Chan ((((val) & 0xf0000000) == 0xa0000000) ||\ 2445c86a8560SMichael Chan (((val) & 0x0f000000) == 0x0a000000)) 2446adfc5217SJeff Kirsher 2447adfc5217SJeff Kirsher /* APE shared memory. Accessible through BAR1 */ 2448cf8d55aeSMatt Carlson #define TG3_APE_SHMEM_BASE 0x4000 2449cf8d55aeSMatt Carlson #define TG3_APE_SEG_SIG 0x4000 2450cf8d55aeSMatt Carlson #define APE_SEG_SIG_MAGIC 0x41504521 2451adfc5217SJeff Kirsher #define TG3_APE_FW_STATUS 0x400c 2452adfc5217SJeff Kirsher #define APE_FW_STATUS_READY 0x00000100 2453adfc5217SJeff Kirsher #define TG3_APE_FW_FEATURES 0x4010 2454adfc5217SJeff Kirsher #define TG3_APE_FW_FEATURE_NCSI 0x00000002 2455adfc5217SJeff Kirsher #define TG3_APE_FW_VERSION 0x4018 2456adfc5217SJeff Kirsher #define APE_FW_VERSION_MAJMSK 0xff000000 2457adfc5217SJeff Kirsher #define APE_FW_VERSION_MAJSFT 24 2458adfc5217SJeff Kirsher #define APE_FW_VERSION_MINMSK 0x00ff0000 2459adfc5217SJeff Kirsher #define APE_FW_VERSION_MINSFT 16 2460adfc5217SJeff Kirsher #define APE_FW_VERSION_REVMSK 0x0000ff00 2461adfc5217SJeff Kirsher #define APE_FW_VERSION_REVSFT 8 2462adfc5217SJeff Kirsher #define APE_FW_VERSION_BLDMSK 0x000000ff 2463cf8d55aeSMatt Carlson #define TG3_APE_SEG_MSG_BUF_OFF 0x401c 2464cf8d55aeSMatt Carlson #define TG3_APE_SEG_MSG_BUF_LEN 0x4020 2465adfc5217SJeff Kirsher #define TG3_APE_HOST_SEG_SIG 0x4200 2466adfc5217SJeff Kirsher #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2467adfc5217SJeff Kirsher #define TG3_APE_HOST_SEG_LEN 0x4204 2468adfc5217SJeff Kirsher #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2469adfc5217SJeff Kirsher #define TG3_APE_HOST_INIT_COUNT 0x4208 2470adfc5217SJeff Kirsher #define TG3_APE_HOST_DRIVER_ID 0x420c 2471adfc5217SJeff Kirsher #define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2472adfc5217SJeff Kirsher #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2473adfc5217SJeff Kirsher (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2474adfc5217SJeff Kirsher #define TG3_APE_HOST_BEHAVIOR 0x4210 2475adfc5217SJeff Kirsher #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2476adfc5217SJeff Kirsher #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2477adfc5217SJeff Kirsher #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2478adfc5217SJeff Kirsher #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2479adfc5217SJeff Kirsher #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2480adfc5217SJeff Kirsher #define TG3_APE_HOST_DRVR_STATE 0x421c 2481adfc5217SJeff Kirsher #define TG3_APE_HOST_DRVR_STATE_START 0x00000001 2482adfc5217SJeff Kirsher #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2483adfc5217SJeff Kirsher #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 2484adfc5217SJeff Kirsher #define TG3_APE_HOST_WOL_SPEED 0x4224 2485adfc5217SJeff Kirsher #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 2486adfc5217SJeff Kirsher 2487adfc5217SJeff Kirsher #define TG3_APE_EVENT_STATUS 0x4300 2488adfc5217SJeff Kirsher 2489adfc5217SJeff Kirsher #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2490adfc5217SJeff Kirsher #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2491cf8d55aeSMatt Carlson #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2492cf8d55aeSMatt Carlson #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2493adfc5217SJeff Kirsher #define APE_EVENT_STATUS_STATE_START 0x00010000 2494adfc5217SJeff Kirsher #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2495adfc5217SJeff Kirsher #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2496adfc5217SJeff Kirsher #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2497adfc5217SJeff Kirsher #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2498adfc5217SJeff Kirsher 2499adfc5217SJeff Kirsher #define TG3_APE_PER_LOCK_REQ 0x8400 2500adfc5217SJeff Kirsher #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2501adfc5217SJeff Kirsher #define TG3_APE_PER_LOCK_GRANT 0x8420 2502adfc5217SJeff Kirsher #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2503adfc5217SJeff Kirsher 2504adfc5217SJeff Kirsher /* APE convenience enumerations. */ 250578f94dc7SMatt Carlson #define TG3_APE_LOCK_PHY0 0 2506adfc5217SJeff Kirsher #define TG3_APE_LOCK_GRC 1 250778f94dc7SMatt Carlson #define TG3_APE_LOCK_PHY1 2 250878f94dc7SMatt Carlson #define TG3_APE_LOCK_PHY2 3 2509adfc5217SJeff Kirsher #define TG3_APE_LOCK_MEM 4 251078f94dc7SMatt Carlson #define TG3_APE_LOCK_PHY3 5 2511adfc5217SJeff Kirsher #define TG3_APE_LOCK_GPIO 7 2512adfc5217SJeff Kirsher 2513506b0a39SPrashant Sreedharan #define TG3_APE_HB_INTERVAL (tp->ape_hb_interval) 2514adfc5217SJeff Kirsher #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2515adfc5217SJeff Kirsher 2516adfc5217SJeff Kirsher 2517adfc5217SJeff Kirsher /* There are two ways to manage the TX descriptors on the tigon3. 2518adfc5217SJeff Kirsher * Either the descriptors are in host DMA'able memory, or they 2519adfc5217SJeff Kirsher * exist only in the cards on-chip SRAM. All 16 send bds are under 2520adfc5217SJeff Kirsher * the same mode, they may not be configured individually. 2521adfc5217SJeff Kirsher * 2522adfc5217SJeff Kirsher * This driver always uses host memory TX descriptors. 2523adfc5217SJeff Kirsher * 2524adfc5217SJeff Kirsher * To use host memory TX descriptors: 2525adfc5217SJeff Kirsher * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2526adfc5217SJeff Kirsher * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2527adfc5217SJeff Kirsher * 2) Allocate DMA'able memory. 2528adfc5217SJeff Kirsher * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2529adfc5217SJeff Kirsher * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2530adfc5217SJeff Kirsher * obtained in step 2 2531adfc5217SJeff Kirsher * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2532adfc5217SJeff Kirsher * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2533adfc5217SJeff Kirsher * of TX descriptors. Leave flags field clear. 2534adfc5217SJeff Kirsher * 4) Access TX descriptors via host memory. The chip 2535adfc5217SJeff Kirsher * will refetch into local SRAM as needed when producer 2536adfc5217SJeff Kirsher * index mailboxes are updated. 2537adfc5217SJeff Kirsher * 2538adfc5217SJeff Kirsher * To use on-chip TX descriptors: 2539adfc5217SJeff Kirsher * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2540adfc5217SJeff Kirsher * Make sure GRC_MODE_HOST_SENDBDS is clear. 2541adfc5217SJeff Kirsher * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2542adfc5217SJeff Kirsher * a) Set TG3_BDINFO_HOST_ADDR to zero. 2543adfc5217SJeff Kirsher * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2544adfc5217SJeff Kirsher * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2545adfc5217SJeff Kirsher * 3) Access TX descriptors directly in on-chip SRAM 2546adfc5217SJeff Kirsher * using normal {read,write}l(). (and not using 2547adfc5217SJeff Kirsher * pointer dereferencing of ioremap()'d memory like 2548adfc5217SJeff Kirsher * the broken Broadcom driver does) 2549adfc5217SJeff Kirsher * 2550adfc5217SJeff Kirsher * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2551adfc5217SJeff Kirsher * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2552adfc5217SJeff Kirsher */ 2553adfc5217SJeff Kirsher struct tg3_tx_buffer_desc { 2554adfc5217SJeff Kirsher u32 addr_hi; 2555adfc5217SJeff Kirsher u32 addr_lo; 2556adfc5217SJeff Kirsher 2557adfc5217SJeff Kirsher u32 len_flags; 2558adfc5217SJeff Kirsher #define TXD_FLAG_TCPUDP_CSUM 0x0001 2559adfc5217SJeff Kirsher #define TXD_FLAG_IP_CSUM 0x0002 2560adfc5217SJeff Kirsher #define TXD_FLAG_END 0x0004 2561adfc5217SJeff Kirsher #define TXD_FLAG_IP_FRAG 0x0008 2562adfc5217SJeff Kirsher #define TXD_FLAG_JMB_PKT 0x0008 2563adfc5217SJeff Kirsher #define TXD_FLAG_IP_FRAG_END 0x0010 2564be947307SMatt Carlson #define TXD_FLAG_HWTSTAMP 0x0020 2565adfc5217SJeff Kirsher #define TXD_FLAG_VLAN 0x0040 2566adfc5217SJeff Kirsher #define TXD_FLAG_COAL_NOW 0x0080 2567adfc5217SJeff Kirsher #define TXD_FLAG_CPU_PRE_DMA 0x0100 2568adfc5217SJeff Kirsher #define TXD_FLAG_CPU_POST_DMA 0x0200 2569adfc5217SJeff Kirsher #define TXD_FLAG_ADD_SRC_ADDR 0x1000 2570adfc5217SJeff Kirsher #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2571adfc5217SJeff Kirsher #define TXD_FLAG_NO_CRC 0x8000 2572adfc5217SJeff Kirsher #define TXD_LEN_SHIFT 16 2573adfc5217SJeff Kirsher 2574adfc5217SJeff Kirsher u32 vlan_tag; 2575adfc5217SJeff Kirsher #define TXD_VLAN_TAG_SHIFT 0 2576adfc5217SJeff Kirsher #define TXD_MSS_SHIFT 16 2577adfc5217SJeff Kirsher }; 2578adfc5217SJeff Kirsher 2579adfc5217SJeff Kirsher #define TXD_ADDR 0x00UL /* 64-bit */ 2580adfc5217SJeff Kirsher #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2581adfc5217SJeff Kirsher #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2582adfc5217SJeff Kirsher #define TXD_SIZE 0x10UL 2583adfc5217SJeff Kirsher 2584adfc5217SJeff Kirsher struct tg3_rx_buffer_desc { 2585adfc5217SJeff Kirsher u32 addr_hi; 2586adfc5217SJeff Kirsher u32 addr_lo; 2587adfc5217SJeff Kirsher 2588adfc5217SJeff Kirsher u32 idx_len; 2589adfc5217SJeff Kirsher #define RXD_IDX_MASK 0xffff0000 2590adfc5217SJeff Kirsher #define RXD_IDX_SHIFT 16 2591adfc5217SJeff Kirsher #define RXD_LEN_MASK 0x0000ffff 2592adfc5217SJeff Kirsher #define RXD_LEN_SHIFT 0 2593adfc5217SJeff Kirsher 2594adfc5217SJeff Kirsher u32 type_flags; 2595adfc5217SJeff Kirsher #define RXD_TYPE_SHIFT 16 2596adfc5217SJeff Kirsher #define RXD_FLAGS_SHIFT 0 2597adfc5217SJeff Kirsher 2598adfc5217SJeff Kirsher #define RXD_FLAG_END 0x0004 2599adfc5217SJeff Kirsher #define RXD_FLAG_MINI 0x0800 2600adfc5217SJeff Kirsher #define RXD_FLAG_JUMBO 0x0020 2601adfc5217SJeff Kirsher #define RXD_FLAG_VLAN 0x0040 2602adfc5217SJeff Kirsher #define RXD_FLAG_ERROR 0x0400 2603adfc5217SJeff Kirsher #define RXD_FLAG_IP_CSUM 0x1000 2604adfc5217SJeff Kirsher #define RXD_FLAG_TCPUDP_CSUM 0x2000 2605adfc5217SJeff Kirsher #define RXD_FLAG_IS_TCP 0x4000 2606be947307SMatt Carlson #define RXD_FLAG_PTPSTAT_MASK 0x0210 2607be947307SMatt Carlson #define RXD_FLAG_PTPSTAT_PTPV1 0x0010 2608be947307SMatt Carlson #define RXD_FLAG_PTPSTAT_PTPV2 0x0200 2609adfc5217SJeff Kirsher 2610adfc5217SJeff Kirsher u32 ip_tcp_csum; 2611adfc5217SJeff Kirsher #define RXD_IPCSUM_MASK 0xffff0000 2612adfc5217SJeff Kirsher #define RXD_IPCSUM_SHIFT 16 2613adfc5217SJeff Kirsher #define RXD_TCPCSUM_MASK 0x0000ffff 2614adfc5217SJeff Kirsher #define RXD_TCPCSUM_SHIFT 0 2615adfc5217SJeff Kirsher 2616adfc5217SJeff Kirsher u32 err_vlan; 2617adfc5217SJeff Kirsher 2618adfc5217SJeff Kirsher #define RXD_VLAN_MASK 0x0000ffff 2619adfc5217SJeff Kirsher 2620adfc5217SJeff Kirsher #define RXD_ERR_BAD_CRC 0x00010000 2621adfc5217SJeff Kirsher #define RXD_ERR_COLLISION 0x00020000 2622adfc5217SJeff Kirsher #define RXD_ERR_LINK_LOST 0x00040000 2623adfc5217SJeff Kirsher #define RXD_ERR_PHY_DECODE 0x00080000 2624adfc5217SJeff Kirsher #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2625adfc5217SJeff Kirsher #define RXD_ERR_MAC_ABRT 0x00200000 2626adfc5217SJeff Kirsher #define RXD_ERR_TOO_SMALL 0x00400000 2627adfc5217SJeff Kirsher #define RXD_ERR_NO_RESOURCES 0x00800000 2628adfc5217SJeff Kirsher #define RXD_ERR_HUGE_FRAME 0x01000000 2629d7b95315SMichael Chan 2630d7b95315SMichael Chan #define RXD_ERR_MASK (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION | \ 2631d7b95315SMichael Chan RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE | \ 2632d7b95315SMichael Chan RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL | \ 2633d7b95315SMichael Chan RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME) 2634adfc5217SJeff Kirsher 2635adfc5217SJeff Kirsher u32 reserved; 2636adfc5217SJeff Kirsher u32 opaque; 2637adfc5217SJeff Kirsher #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2638adfc5217SJeff Kirsher #define RXD_OPAQUE_INDEX_SHIFT 0 2639adfc5217SJeff Kirsher #define RXD_OPAQUE_RING_STD 0x00010000 2640adfc5217SJeff Kirsher #define RXD_OPAQUE_RING_JUMBO 0x00020000 2641adfc5217SJeff Kirsher #define RXD_OPAQUE_RING_MINI 0x00040000 2642adfc5217SJeff Kirsher #define RXD_OPAQUE_RING_MASK 0x00070000 2643adfc5217SJeff Kirsher }; 2644adfc5217SJeff Kirsher 2645adfc5217SJeff Kirsher struct tg3_ext_rx_buffer_desc { 2646adfc5217SJeff Kirsher struct { 2647adfc5217SJeff Kirsher u32 addr_hi; 2648adfc5217SJeff Kirsher u32 addr_lo; 2649adfc5217SJeff Kirsher } addrlist[3]; 2650adfc5217SJeff Kirsher u32 len2_len1; 2651adfc5217SJeff Kirsher u32 resv_len3; 2652adfc5217SJeff Kirsher struct tg3_rx_buffer_desc std; 2653adfc5217SJeff Kirsher }; 2654adfc5217SJeff Kirsher 2655adfc5217SJeff Kirsher /* We only use this when testing out the DMA engine 2656adfc5217SJeff Kirsher * at probe time. This is the internal format of buffer 2657adfc5217SJeff Kirsher * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2658adfc5217SJeff Kirsher */ 2659adfc5217SJeff Kirsher struct tg3_internal_buffer_desc { 2660adfc5217SJeff Kirsher u32 addr_hi; 2661adfc5217SJeff Kirsher u32 addr_lo; 2662adfc5217SJeff Kirsher u32 nic_mbuf; 2663adfc5217SJeff Kirsher /* XXX FIX THIS */ 2664adfc5217SJeff Kirsher #ifdef __BIG_ENDIAN 2665adfc5217SJeff Kirsher u16 cqid_sqid; 2666adfc5217SJeff Kirsher u16 len; 2667adfc5217SJeff Kirsher #else 2668adfc5217SJeff Kirsher u16 len; 2669adfc5217SJeff Kirsher u16 cqid_sqid; 2670adfc5217SJeff Kirsher #endif 2671adfc5217SJeff Kirsher u32 flags; 2672adfc5217SJeff Kirsher u32 __cookie1; 2673adfc5217SJeff Kirsher u32 __cookie2; 2674adfc5217SJeff Kirsher u32 __cookie3; 2675adfc5217SJeff Kirsher }; 2676adfc5217SJeff Kirsher 2677adfc5217SJeff Kirsher #define TG3_HW_STATUS_SIZE 0x50 2678adfc5217SJeff Kirsher struct tg3_hw_status { 2679adfc5217SJeff Kirsher u32 status; 2680adfc5217SJeff Kirsher #define SD_STATUS_UPDATED 0x00000001 2681adfc5217SJeff Kirsher #define SD_STATUS_LINK_CHG 0x00000002 2682adfc5217SJeff Kirsher #define SD_STATUS_ERROR 0x00000004 2683adfc5217SJeff Kirsher 2684adfc5217SJeff Kirsher u32 status_tag; 2685adfc5217SJeff Kirsher 2686adfc5217SJeff Kirsher #ifdef __BIG_ENDIAN 2687adfc5217SJeff Kirsher u16 rx_consumer; 2688adfc5217SJeff Kirsher u16 rx_jumbo_consumer; 2689adfc5217SJeff Kirsher #else 2690adfc5217SJeff Kirsher u16 rx_jumbo_consumer; 2691adfc5217SJeff Kirsher u16 rx_consumer; 2692adfc5217SJeff Kirsher #endif 2693adfc5217SJeff Kirsher 2694adfc5217SJeff Kirsher #ifdef __BIG_ENDIAN 2695adfc5217SJeff Kirsher u16 reserved; 2696adfc5217SJeff Kirsher u16 rx_mini_consumer; 2697adfc5217SJeff Kirsher #else 2698adfc5217SJeff Kirsher u16 rx_mini_consumer; 2699adfc5217SJeff Kirsher u16 reserved; 2700adfc5217SJeff Kirsher #endif 2701adfc5217SJeff Kirsher struct { 2702adfc5217SJeff Kirsher #ifdef __BIG_ENDIAN 2703adfc5217SJeff Kirsher u16 tx_consumer; 2704adfc5217SJeff Kirsher u16 rx_producer; 2705adfc5217SJeff Kirsher #else 2706adfc5217SJeff Kirsher u16 rx_producer; 2707adfc5217SJeff Kirsher u16 tx_consumer; 2708adfc5217SJeff Kirsher #endif 2709adfc5217SJeff Kirsher } idx[16]; 2710adfc5217SJeff Kirsher }; 2711adfc5217SJeff Kirsher 2712adfc5217SJeff Kirsher typedef struct { 2713adfc5217SJeff Kirsher u32 high, low; 2714adfc5217SJeff Kirsher } tg3_stat64_t; 2715adfc5217SJeff Kirsher 2716adfc5217SJeff Kirsher struct tg3_hw_stats { 2717adfc5217SJeff Kirsher u8 __reserved0[0x400-0x300]; 2718adfc5217SJeff Kirsher 2719adfc5217SJeff Kirsher /* Statistics maintained by Receive MAC. */ 2720adfc5217SJeff Kirsher tg3_stat64_t rx_octets; 2721adfc5217SJeff Kirsher u64 __reserved1; 2722adfc5217SJeff Kirsher tg3_stat64_t rx_fragments; 2723adfc5217SJeff Kirsher tg3_stat64_t rx_ucast_packets; 2724adfc5217SJeff Kirsher tg3_stat64_t rx_mcast_packets; 2725adfc5217SJeff Kirsher tg3_stat64_t rx_bcast_packets; 2726adfc5217SJeff Kirsher tg3_stat64_t rx_fcs_errors; 2727adfc5217SJeff Kirsher tg3_stat64_t rx_align_errors; 2728adfc5217SJeff Kirsher tg3_stat64_t rx_xon_pause_rcvd; 2729adfc5217SJeff Kirsher tg3_stat64_t rx_xoff_pause_rcvd; 2730adfc5217SJeff Kirsher tg3_stat64_t rx_mac_ctrl_rcvd; 2731adfc5217SJeff Kirsher tg3_stat64_t rx_xoff_entered; 2732adfc5217SJeff Kirsher tg3_stat64_t rx_frame_too_long_errors; 2733adfc5217SJeff Kirsher tg3_stat64_t rx_jabbers; 2734adfc5217SJeff Kirsher tg3_stat64_t rx_undersize_packets; 2735adfc5217SJeff Kirsher tg3_stat64_t rx_in_length_errors; 2736adfc5217SJeff Kirsher tg3_stat64_t rx_out_length_errors; 2737adfc5217SJeff Kirsher tg3_stat64_t rx_64_or_less_octet_packets; 2738adfc5217SJeff Kirsher tg3_stat64_t rx_65_to_127_octet_packets; 2739adfc5217SJeff Kirsher tg3_stat64_t rx_128_to_255_octet_packets; 2740adfc5217SJeff Kirsher tg3_stat64_t rx_256_to_511_octet_packets; 2741adfc5217SJeff Kirsher tg3_stat64_t rx_512_to_1023_octet_packets; 2742adfc5217SJeff Kirsher tg3_stat64_t rx_1024_to_1522_octet_packets; 2743adfc5217SJeff Kirsher tg3_stat64_t rx_1523_to_2047_octet_packets; 2744adfc5217SJeff Kirsher tg3_stat64_t rx_2048_to_4095_octet_packets; 2745adfc5217SJeff Kirsher tg3_stat64_t rx_4096_to_8191_octet_packets; 2746adfc5217SJeff Kirsher tg3_stat64_t rx_8192_to_9022_octet_packets; 2747adfc5217SJeff Kirsher 2748adfc5217SJeff Kirsher u64 __unused0[37]; 2749adfc5217SJeff Kirsher 2750adfc5217SJeff Kirsher /* Statistics maintained by Transmit MAC. */ 2751adfc5217SJeff Kirsher tg3_stat64_t tx_octets; 2752adfc5217SJeff Kirsher u64 __reserved2; 2753adfc5217SJeff Kirsher tg3_stat64_t tx_collisions; 2754adfc5217SJeff Kirsher tg3_stat64_t tx_xon_sent; 2755adfc5217SJeff Kirsher tg3_stat64_t tx_xoff_sent; 2756adfc5217SJeff Kirsher tg3_stat64_t tx_flow_control; 2757adfc5217SJeff Kirsher tg3_stat64_t tx_mac_errors; 2758adfc5217SJeff Kirsher tg3_stat64_t tx_single_collisions; 2759adfc5217SJeff Kirsher tg3_stat64_t tx_mult_collisions; 2760adfc5217SJeff Kirsher tg3_stat64_t tx_deferred; 2761adfc5217SJeff Kirsher u64 __reserved3; 2762adfc5217SJeff Kirsher tg3_stat64_t tx_excessive_collisions; 2763adfc5217SJeff Kirsher tg3_stat64_t tx_late_collisions; 2764adfc5217SJeff Kirsher tg3_stat64_t tx_collide_2times; 2765adfc5217SJeff Kirsher tg3_stat64_t tx_collide_3times; 2766adfc5217SJeff Kirsher tg3_stat64_t tx_collide_4times; 2767adfc5217SJeff Kirsher tg3_stat64_t tx_collide_5times; 2768adfc5217SJeff Kirsher tg3_stat64_t tx_collide_6times; 2769adfc5217SJeff Kirsher tg3_stat64_t tx_collide_7times; 2770adfc5217SJeff Kirsher tg3_stat64_t tx_collide_8times; 2771adfc5217SJeff Kirsher tg3_stat64_t tx_collide_9times; 2772adfc5217SJeff Kirsher tg3_stat64_t tx_collide_10times; 2773adfc5217SJeff Kirsher tg3_stat64_t tx_collide_11times; 2774adfc5217SJeff Kirsher tg3_stat64_t tx_collide_12times; 2775adfc5217SJeff Kirsher tg3_stat64_t tx_collide_13times; 2776adfc5217SJeff Kirsher tg3_stat64_t tx_collide_14times; 2777adfc5217SJeff Kirsher tg3_stat64_t tx_collide_15times; 2778adfc5217SJeff Kirsher tg3_stat64_t tx_ucast_packets; 2779adfc5217SJeff Kirsher tg3_stat64_t tx_mcast_packets; 2780adfc5217SJeff Kirsher tg3_stat64_t tx_bcast_packets; 2781adfc5217SJeff Kirsher tg3_stat64_t tx_carrier_sense_errors; 2782adfc5217SJeff Kirsher tg3_stat64_t tx_discards; 2783adfc5217SJeff Kirsher tg3_stat64_t tx_errors; 2784adfc5217SJeff Kirsher 2785adfc5217SJeff Kirsher u64 __unused1[31]; 2786adfc5217SJeff Kirsher 2787adfc5217SJeff Kirsher /* Statistics maintained by Receive List Placement. */ 2788adfc5217SJeff Kirsher tg3_stat64_t COS_rx_packets[16]; 2789adfc5217SJeff Kirsher tg3_stat64_t COS_rx_filter_dropped; 2790adfc5217SJeff Kirsher tg3_stat64_t dma_writeq_full; 2791adfc5217SJeff Kirsher tg3_stat64_t dma_write_prioq_full; 2792adfc5217SJeff Kirsher tg3_stat64_t rxbds_empty; 2793adfc5217SJeff Kirsher tg3_stat64_t rx_discards; 2794adfc5217SJeff Kirsher tg3_stat64_t rx_errors; 2795adfc5217SJeff Kirsher tg3_stat64_t rx_threshold_hit; 2796adfc5217SJeff Kirsher 2797adfc5217SJeff Kirsher u64 __unused2[9]; 2798adfc5217SJeff Kirsher 2799adfc5217SJeff Kirsher /* Statistics maintained by Send Data Initiator. */ 2800adfc5217SJeff Kirsher tg3_stat64_t COS_out_packets[16]; 2801adfc5217SJeff Kirsher tg3_stat64_t dma_readq_full; 2802adfc5217SJeff Kirsher tg3_stat64_t dma_read_prioq_full; 2803adfc5217SJeff Kirsher tg3_stat64_t tx_comp_queue_full; 2804adfc5217SJeff Kirsher 2805adfc5217SJeff Kirsher /* Statistics maintained by Host Coalescing. */ 2806adfc5217SJeff Kirsher tg3_stat64_t ring_set_send_prod_index; 2807adfc5217SJeff Kirsher tg3_stat64_t ring_status_update; 2808adfc5217SJeff Kirsher tg3_stat64_t nic_irqs; 2809adfc5217SJeff Kirsher tg3_stat64_t nic_avoided_irqs; 2810adfc5217SJeff Kirsher tg3_stat64_t nic_tx_threshold_hit; 2811adfc5217SJeff Kirsher 2812adfc5217SJeff Kirsher /* NOT a part of the hardware statistics block format. 2813adfc5217SJeff Kirsher * These stats are here as storage for tg3_periodic_fetch_stats(). 2814adfc5217SJeff Kirsher */ 2815adfc5217SJeff Kirsher tg3_stat64_t mbuf_lwm_thresh_hit; 2816adfc5217SJeff Kirsher 2817adfc5217SJeff Kirsher u8 __reserved4[0xb00-0x9c8]; 2818adfc5217SJeff Kirsher }; 2819adfc5217SJeff Kirsher 2820aed93e0bSMichael Chan #define TG3_SD_NUM_RECS 3 2821aed93e0bSMichael Chan #define TG3_OCIR_LEN (sizeof(struct tg3_ocir)) 2822aed93e0bSMichael Chan #define TG3_OCIR_SIG_MAGIC 0x5253434f 2823aed93e0bSMichael Chan #define TG3_OCIR_FLAG_ACTIVE 0x00000001 2824aed93e0bSMichael Chan 2825aed93e0bSMichael Chan #define TG3_TEMP_CAUTION_OFFSET 0xc8 2826aed93e0bSMichael Chan #define TG3_TEMP_MAX_OFFSET 0xcc 2827aed93e0bSMichael Chan #define TG3_TEMP_SENSOR_OFFSET 0xd4 2828aed93e0bSMichael Chan 2829aed93e0bSMichael Chan 2830aed93e0bSMichael Chan struct tg3_ocir { 2831aed93e0bSMichael Chan u32 signature; 2832aed93e0bSMichael Chan u16 version_flags; 2833aed93e0bSMichael Chan u16 refresh_int; 2834aed93e0bSMichael Chan u32 refresh_tmr; 2835aed93e0bSMichael Chan u32 update_tmr; 2836aed93e0bSMichael Chan u32 dst_base_addr; 2837aed93e0bSMichael Chan u16 src_hdr_offset; 2838aed93e0bSMichael Chan u16 src_hdr_length; 2839aed93e0bSMichael Chan u16 src_data_offset; 2840aed93e0bSMichael Chan u16 src_data_length; 2841aed93e0bSMichael Chan u16 dst_hdr_offset; 2842aed93e0bSMichael Chan u16 dst_data_offset; 2843aed93e0bSMichael Chan u16 dst_reg_upd_offset; 2844aed93e0bSMichael Chan u16 dst_sem_offset; 2845aed93e0bSMichael Chan u32 reserved1[2]; 2846aed93e0bSMichael Chan u32 port0_flags; 2847aed93e0bSMichael Chan u32 port1_flags; 2848aed93e0bSMichael Chan u32 port2_flags; 2849aed93e0bSMichael Chan u32 port3_flags; 28507ec3e95eSGustavo A. R. Silva u32 reserved2; 2851aed93e0bSMichael Chan }; 2852aed93e0bSMichael Chan 2853aed93e0bSMichael Chan 2854adfc5217SJeff Kirsher /* 'mapping' is superfluous as the chip does not write into 2855adfc5217SJeff Kirsher * the tx/rx post rings so we could just fetch it from there. 2856adfc5217SJeff Kirsher * But the cache behavior is better how we are doing it now. 28579205fd9cSEric Dumazet * 28589205fd9cSEric Dumazet * This driver uses new build_skb() API : 28599205fd9cSEric Dumazet * RX ring buffer contains pointer to kmalloc() data only, 28609205fd9cSEric Dumazet * skb are built only after Hardware filled the frame. 2861adfc5217SJeff Kirsher */ 2862adfc5217SJeff Kirsher struct ring_info { 28639205fd9cSEric Dumazet u8 *data; 2864adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 2865adfc5217SJeff Kirsher }; 2866adfc5217SJeff Kirsher 2867adfc5217SJeff Kirsher struct tg3_tx_ring_info { 2868adfc5217SJeff Kirsher struct sk_buff *skb; 2869adfc5217SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping); 2870adfc5217SJeff Kirsher bool fragmented; 2871adfc5217SJeff Kirsher }; 2872adfc5217SJeff Kirsher 2873adfc5217SJeff Kirsher struct tg3_link_config { 2874adfc5217SJeff Kirsher /* Describes what we're trying to get. */ 2875adfc5217SJeff Kirsher u32 advertising; 2876caf2c520SMichael Zhivich u32 speed; 2877adfc5217SJeff Kirsher u8 duplex; 2878adfc5217SJeff Kirsher u8 autoneg; 2879adfc5217SJeff Kirsher u8 flowctrl; 2880adfc5217SJeff Kirsher 2881adfc5217SJeff Kirsher /* Describes what we actually have. */ 2882adfc5217SJeff Kirsher u8 active_flowctrl; 2883adfc5217SJeff Kirsher 2884adfc5217SJeff Kirsher u8 active_duplex; 2885caf2c520SMichael Zhivich u32 active_speed; 2886859edb26SMatt Carlson u32 rmt_adv; 2887adfc5217SJeff Kirsher }; 2888adfc5217SJeff Kirsher 2889adfc5217SJeff Kirsher struct tg3_bufmgr_config { 2890adfc5217SJeff Kirsher u32 mbuf_read_dma_low_water; 2891adfc5217SJeff Kirsher u32 mbuf_mac_rx_low_water; 2892adfc5217SJeff Kirsher u32 mbuf_high_water; 2893adfc5217SJeff Kirsher 2894adfc5217SJeff Kirsher u32 mbuf_read_dma_low_water_jumbo; 2895adfc5217SJeff Kirsher u32 mbuf_mac_rx_low_water_jumbo; 2896adfc5217SJeff Kirsher u32 mbuf_high_water_jumbo; 2897adfc5217SJeff Kirsher 2898adfc5217SJeff Kirsher u32 dma_low_water; 2899adfc5217SJeff Kirsher u32 dma_high_water; 2900adfc5217SJeff Kirsher }; 2901adfc5217SJeff Kirsher 2902adfc5217SJeff Kirsher struct tg3_ethtool_stats { 2903adfc5217SJeff Kirsher /* Statistics maintained by Receive MAC. */ 2904adfc5217SJeff Kirsher u64 rx_octets; 2905adfc5217SJeff Kirsher u64 rx_fragments; 2906adfc5217SJeff Kirsher u64 rx_ucast_packets; 2907adfc5217SJeff Kirsher u64 rx_mcast_packets; 2908adfc5217SJeff Kirsher u64 rx_bcast_packets; 2909adfc5217SJeff Kirsher u64 rx_fcs_errors; 2910adfc5217SJeff Kirsher u64 rx_align_errors; 2911adfc5217SJeff Kirsher u64 rx_xon_pause_rcvd; 2912adfc5217SJeff Kirsher u64 rx_xoff_pause_rcvd; 2913adfc5217SJeff Kirsher u64 rx_mac_ctrl_rcvd; 2914adfc5217SJeff Kirsher u64 rx_xoff_entered; 2915adfc5217SJeff Kirsher u64 rx_frame_too_long_errors; 2916adfc5217SJeff Kirsher u64 rx_jabbers; 2917adfc5217SJeff Kirsher u64 rx_undersize_packets; 2918adfc5217SJeff Kirsher u64 rx_in_length_errors; 2919adfc5217SJeff Kirsher u64 rx_out_length_errors; 2920adfc5217SJeff Kirsher u64 rx_64_or_less_octet_packets; 2921adfc5217SJeff Kirsher u64 rx_65_to_127_octet_packets; 2922adfc5217SJeff Kirsher u64 rx_128_to_255_octet_packets; 2923adfc5217SJeff Kirsher u64 rx_256_to_511_octet_packets; 2924adfc5217SJeff Kirsher u64 rx_512_to_1023_octet_packets; 2925adfc5217SJeff Kirsher u64 rx_1024_to_1522_octet_packets; 2926adfc5217SJeff Kirsher u64 rx_1523_to_2047_octet_packets; 2927adfc5217SJeff Kirsher u64 rx_2048_to_4095_octet_packets; 2928adfc5217SJeff Kirsher u64 rx_4096_to_8191_octet_packets; 2929adfc5217SJeff Kirsher u64 rx_8192_to_9022_octet_packets; 2930adfc5217SJeff Kirsher 2931adfc5217SJeff Kirsher /* Statistics maintained by Transmit MAC. */ 2932adfc5217SJeff Kirsher u64 tx_octets; 2933adfc5217SJeff Kirsher u64 tx_collisions; 2934adfc5217SJeff Kirsher u64 tx_xon_sent; 2935adfc5217SJeff Kirsher u64 tx_xoff_sent; 2936adfc5217SJeff Kirsher u64 tx_flow_control; 2937adfc5217SJeff Kirsher u64 tx_mac_errors; 2938adfc5217SJeff Kirsher u64 tx_single_collisions; 2939adfc5217SJeff Kirsher u64 tx_mult_collisions; 2940adfc5217SJeff Kirsher u64 tx_deferred; 2941adfc5217SJeff Kirsher u64 tx_excessive_collisions; 2942adfc5217SJeff Kirsher u64 tx_late_collisions; 2943adfc5217SJeff Kirsher u64 tx_collide_2times; 2944adfc5217SJeff Kirsher u64 tx_collide_3times; 2945adfc5217SJeff Kirsher u64 tx_collide_4times; 2946adfc5217SJeff Kirsher u64 tx_collide_5times; 2947adfc5217SJeff Kirsher u64 tx_collide_6times; 2948adfc5217SJeff Kirsher u64 tx_collide_7times; 2949adfc5217SJeff Kirsher u64 tx_collide_8times; 2950adfc5217SJeff Kirsher u64 tx_collide_9times; 2951adfc5217SJeff Kirsher u64 tx_collide_10times; 2952adfc5217SJeff Kirsher u64 tx_collide_11times; 2953adfc5217SJeff Kirsher u64 tx_collide_12times; 2954adfc5217SJeff Kirsher u64 tx_collide_13times; 2955adfc5217SJeff Kirsher u64 tx_collide_14times; 2956adfc5217SJeff Kirsher u64 tx_collide_15times; 2957adfc5217SJeff Kirsher u64 tx_ucast_packets; 2958adfc5217SJeff Kirsher u64 tx_mcast_packets; 2959adfc5217SJeff Kirsher u64 tx_bcast_packets; 2960adfc5217SJeff Kirsher u64 tx_carrier_sense_errors; 2961adfc5217SJeff Kirsher u64 tx_discards; 2962adfc5217SJeff Kirsher u64 tx_errors; 2963adfc5217SJeff Kirsher 2964adfc5217SJeff Kirsher /* Statistics maintained by Receive List Placement. */ 2965adfc5217SJeff Kirsher u64 dma_writeq_full; 2966adfc5217SJeff Kirsher u64 dma_write_prioq_full; 2967adfc5217SJeff Kirsher u64 rxbds_empty; 2968adfc5217SJeff Kirsher u64 rx_discards; 2969adfc5217SJeff Kirsher u64 rx_errors; 2970adfc5217SJeff Kirsher u64 rx_threshold_hit; 2971adfc5217SJeff Kirsher 2972adfc5217SJeff Kirsher /* Statistics maintained by Send Data Initiator. */ 2973adfc5217SJeff Kirsher u64 dma_readq_full; 2974adfc5217SJeff Kirsher u64 dma_read_prioq_full; 2975adfc5217SJeff Kirsher u64 tx_comp_queue_full; 2976adfc5217SJeff Kirsher 2977adfc5217SJeff Kirsher /* Statistics maintained by Host Coalescing. */ 2978adfc5217SJeff Kirsher u64 ring_set_send_prod_index; 2979adfc5217SJeff Kirsher u64 ring_status_update; 2980adfc5217SJeff Kirsher u64 nic_irqs; 2981adfc5217SJeff Kirsher u64 nic_avoided_irqs; 2982adfc5217SJeff Kirsher u64 nic_tx_threshold_hit; 2983adfc5217SJeff Kirsher 2984adfc5217SJeff Kirsher u64 mbuf_lwm_thresh_hit; 2985adfc5217SJeff Kirsher }; 2986adfc5217SJeff Kirsher 2987adfc5217SJeff Kirsher struct tg3_rx_prodring_set { 2988adfc5217SJeff Kirsher u32 rx_std_prod_idx; 2989adfc5217SJeff Kirsher u32 rx_std_cons_idx; 2990adfc5217SJeff Kirsher u32 rx_jmb_prod_idx; 2991adfc5217SJeff Kirsher u32 rx_jmb_cons_idx; 2992adfc5217SJeff Kirsher struct tg3_rx_buffer_desc *rx_std; 2993adfc5217SJeff Kirsher struct tg3_ext_rx_buffer_desc *rx_jmb; 2994adfc5217SJeff Kirsher struct ring_info *rx_std_buffers; 2995adfc5217SJeff Kirsher struct ring_info *rx_jmb_buffers; 2996adfc5217SJeff Kirsher dma_addr_t rx_std_mapping; 2997adfc5217SJeff Kirsher dma_addr_t rx_jmb_mapping; 2998adfc5217SJeff Kirsher }; 2999adfc5217SJeff Kirsher 30009102426aSMichael Chan #define TG3_RSS_MAX_NUM_QS 4 30019102426aSMichael Chan #define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1) 3002adfc5217SJeff Kirsher #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS 3003adfc5217SJeff Kirsher 3004adfc5217SJeff Kirsher struct tg3_napi { 3005adfc5217SJeff Kirsher struct napi_struct napi ____cacheline_aligned; 3006adfc5217SJeff Kirsher struct tg3 *tp; 3007adfc5217SJeff Kirsher struct tg3_hw_status *hw_status; 3008adfc5217SJeff Kirsher 3009adfc5217SJeff Kirsher u32 chk_msi_cnt; 3010adfc5217SJeff Kirsher u32 last_tag; 3011adfc5217SJeff Kirsher u32 last_irq_tag; 3012adfc5217SJeff Kirsher u32 int_mbox; 3013adfc5217SJeff Kirsher u32 coal_now; 3014adfc5217SJeff Kirsher 3015adfc5217SJeff Kirsher u32 consmbox ____cacheline_aligned; 3016adfc5217SJeff Kirsher u32 rx_rcb_ptr; 3017adfc5217SJeff Kirsher u32 last_rx_cons; 3018adfc5217SJeff Kirsher u16 *rx_rcb_prod_idx; 3019adfc5217SJeff Kirsher struct tg3_rx_prodring_set prodring; 3020adfc5217SJeff Kirsher struct tg3_rx_buffer_desc *rx_rcb; 3021907d1bdbSAlex Pakhunov unsigned long rx_dropped; 3022adfc5217SJeff Kirsher 3023adfc5217SJeff Kirsher u32 tx_prod ____cacheline_aligned; 3024adfc5217SJeff Kirsher u32 tx_cons; 3025adfc5217SJeff Kirsher u32 tx_pending; 3026adfc5217SJeff Kirsher u32 last_tx_cons; 3027adfc5217SJeff Kirsher u32 prodmbox; 3028adfc5217SJeff Kirsher struct tg3_tx_buffer_desc *tx_ring; 3029adfc5217SJeff Kirsher struct tg3_tx_ring_info *tx_buffers; 3030907d1bdbSAlex Pakhunov unsigned long tx_dropped; 3031adfc5217SJeff Kirsher 3032adfc5217SJeff Kirsher dma_addr_t status_mapping; 3033adfc5217SJeff Kirsher dma_addr_t rx_rcb_mapping; 3034adfc5217SJeff Kirsher dma_addr_t tx_desc_mapping; 3035adfc5217SJeff Kirsher 3036adfc5217SJeff Kirsher char irq_lbl[IFNAMSIZ]; 3037adfc5217SJeff Kirsher unsigned int irq_vec; 3038adfc5217SJeff Kirsher }; 3039adfc5217SJeff Kirsher 3040adfc5217SJeff Kirsher enum TG3_FLAGS { 3041adfc5217SJeff Kirsher TG3_FLAG_TAGGED_STATUS = 0, 3042adfc5217SJeff Kirsher TG3_FLAG_TXD_MBOX_HWBUG, 3043adfc5217SJeff Kirsher TG3_FLAG_USE_LINKCHG_REG, 3044adfc5217SJeff Kirsher TG3_FLAG_ERROR_PROCESSED, 3045adfc5217SJeff Kirsher TG3_FLAG_ENABLE_ASF, 3046adfc5217SJeff Kirsher TG3_FLAG_ASPM_WORKAROUND, 3047adfc5217SJeff Kirsher TG3_FLAG_POLL_SERDES, 30481743b83cSNithin Sujir TG3_FLAG_POLL_CPMU_LINK, 3049adfc5217SJeff Kirsher TG3_FLAG_MBOX_WRITE_REORDER, 3050adfc5217SJeff Kirsher TG3_FLAG_PCIX_TARGET_HWBUG, 3051adfc5217SJeff Kirsher TG3_FLAG_WOL_SPEED_100MB, 3052adfc5217SJeff Kirsher TG3_FLAG_WOL_ENABLE, 3053adfc5217SJeff Kirsher TG3_FLAG_EEPROM_WRITE_PROT, 3054adfc5217SJeff Kirsher TG3_FLAG_NVRAM, 3055adfc5217SJeff Kirsher TG3_FLAG_NVRAM_BUFFERED, 3056adfc5217SJeff Kirsher TG3_FLAG_SUPPORT_MSI, 3057adfc5217SJeff Kirsher TG3_FLAG_SUPPORT_MSIX, 305855086ad9SMatt Carlson TG3_FLAG_USING_MSI, 305955086ad9SMatt Carlson TG3_FLAG_USING_MSIX, 3060adfc5217SJeff Kirsher TG3_FLAG_PCIX_MODE, 3061adfc5217SJeff Kirsher TG3_FLAG_PCI_HIGH_SPEED, 3062adfc5217SJeff Kirsher TG3_FLAG_PCI_32BIT, 3063adfc5217SJeff Kirsher TG3_FLAG_SRAM_USE_CONFIG, 3064adfc5217SJeff Kirsher TG3_FLAG_TX_RECOVERY_PENDING, 3065adfc5217SJeff Kirsher TG3_FLAG_WOL_CAP, 3066adfc5217SJeff Kirsher TG3_FLAG_JUMBO_RING_ENABLE, 3067adfc5217SJeff Kirsher TG3_FLAG_PAUSE_AUTONEG, 3068adfc5217SJeff Kirsher TG3_FLAG_CPMU_PRESENT, 3069adfc5217SJeff Kirsher TG3_FLAG_40BIT_DMA_BUG, 3070adfc5217SJeff Kirsher TG3_FLAG_BROKEN_CHECKSUMS, 3071adfc5217SJeff Kirsher TG3_FLAG_JUMBO_CAPABLE, 3072adfc5217SJeff Kirsher TG3_FLAG_CHIP_RESETTING, 3073adfc5217SJeff Kirsher TG3_FLAG_INIT_COMPLETE, 3074adfc5217SJeff Kirsher TG3_FLAG_MAX_RXPEND_64, 3075adfc5217SJeff Kirsher TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ 3076adfc5217SJeff Kirsher TG3_FLAG_ASF_NEW_HANDSHAKE, 3077adfc5217SJeff Kirsher TG3_FLAG_HW_AUTONEG, 3078adfc5217SJeff Kirsher TG3_FLAG_IS_NIC, 3079adfc5217SJeff Kirsher TG3_FLAG_FLASH, 30801caf13ebSMatt Carlson TG3_FLAG_FW_TSO, 3081adfc5217SJeff Kirsher TG3_FLAG_HW_TSO_1, 3082adfc5217SJeff Kirsher TG3_FLAG_HW_TSO_2, 308355086ad9SMatt Carlson TG3_FLAG_HW_TSO_3, 30841caf13ebSMatt Carlson TG3_FLAG_TSO_CAPABLE, 30851caf13ebSMatt Carlson TG3_FLAG_TSO_BUG, 308655086ad9SMatt Carlson TG3_FLAG_ICH_WORKAROUND, 3087adfc5217SJeff Kirsher TG3_FLAG_1SHOT_MSI, 3088adfc5217SJeff Kirsher TG3_FLAG_NO_FWARE_REPORTED, 3089adfc5217SJeff Kirsher TG3_FLAG_NO_NVRAM_ADDR_TRANS, 3090adfc5217SJeff Kirsher TG3_FLAG_ENABLE_APE, 3091adfc5217SJeff Kirsher TG3_FLAG_PROTECTED_NVRAM, 3092adfc5217SJeff Kirsher TG3_FLAG_5701_DMA_BUG, 3093adfc5217SJeff Kirsher TG3_FLAG_USE_PHYLIB, 3094adfc5217SJeff Kirsher TG3_FLAG_MDIOBUS_INITED, 3095adfc5217SJeff Kirsher TG3_FLAG_LRG_PROD_RING_CAP, 3096adfc5217SJeff Kirsher TG3_FLAG_RGMII_INBAND_DISABLE, 3097adfc5217SJeff Kirsher TG3_FLAG_RGMII_EXT_IBND_RX_EN, 3098adfc5217SJeff Kirsher TG3_FLAG_RGMII_EXT_IBND_TX_EN, 3099adfc5217SJeff Kirsher TG3_FLAG_CLKREQ_BUG, 3100adfc5217SJeff Kirsher TG3_FLAG_NO_NVRAM, 3101adfc5217SJeff Kirsher TG3_FLAG_ENABLE_RSS, 3102adfc5217SJeff Kirsher TG3_FLAG_ENABLE_TSS, 3103adfc5217SJeff Kirsher TG3_FLAG_SHORT_DMA_BUG, 3104adfc5217SJeff Kirsher TG3_FLAG_USE_JUMBO_BDFLAG, 3105adfc5217SJeff Kirsher TG3_FLAG_L1PLLPD_EN, 3106adfc5217SJeff Kirsher TG3_FLAG_APE_HAS_NCSI, 3107be947307SMatt Carlson TG3_FLAG_TX_TSTAMP_EN, 3108adfc5217SJeff Kirsher TG3_FLAG_4K_FIFO_LIMIT, 31099bc297eaSNithin Sujir TG3_FLAG_5719_5720_RDMA_BUG, 3110db219973SMatt Carlson TG3_FLAG_RESET_TASK_PENDING, 3111be947307SMatt Carlson TG3_FLAG_PTP_CAPABLE, 311255086ad9SMatt Carlson TG3_FLAG_5705_PLUS, 311355086ad9SMatt Carlson TG3_FLAG_IS_5788, 311455086ad9SMatt Carlson TG3_FLAG_5750_PLUS, 311555086ad9SMatt Carlson TG3_FLAG_5780_CLASS, 311655086ad9SMatt Carlson TG3_FLAG_5755_PLUS, 311755086ad9SMatt Carlson TG3_FLAG_57765_PLUS, 311855086ad9SMatt Carlson TG3_FLAG_57765_CLASS, 311955086ad9SMatt Carlson TG3_FLAG_5717_PLUS, 31207e6c63f0SHauke Mehrtens TG3_FLAG_IS_SSB_CORE, 31217e6c63f0SHauke Mehrtens TG3_FLAG_FLUSH_POSTED_WRITES, 31227e6c63f0SHauke Mehrtens TG3_FLAG_ROBOSWITCH, 31237e6c63f0SHauke Mehrtens TG3_FLAG_ONE_DMA_AT_ONCE, 31247e6c63f0SHauke Mehrtens TG3_FLAG_RGMII_MODE, 3125adfc5217SJeff Kirsher 3126adfc5217SJeff Kirsher /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ 3127adfc5217SJeff Kirsher TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ 3128adfc5217SJeff Kirsher }; 3129adfc5217SJeff Kirsher 313077997ea3SNithin Sujir struct tg3_firmware_hdr { 313177997ea3SNithin Sujir __be32 version; /* unused for fragments */ 313277997ea3SNithin Sujir __be32 base_addr; 313377997ea3SNithin Sujir __be32 len; 313477997ea3SNithin Sujir }; 313577997ea3SNithin Sujir #define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr)) 313677997ea3SNithin Sujir 3137adfc5217SJeff Kirsher struct tg3 { 3138adfc5217SJeff Kirsher /* begin "general, frequently-used members" cacheline section */ 3139adfc5217SJeff Kirsher 3140adfc5217SJeff Kirsher /* If the IRQ handler (which runs lockless) needs to be 3141adfc5217SJeff Kirsher * quiesced, the following bitmask state is used. The 3142adfc5217SJeff Kirsher * SYNC flag is set by non-IRQ context code to initiate 3143adfc5217SJeff Kirsher * the quiescence. 3144adfc5217SJeff Kirsher * 3145adfc5217SJeff Kirsher * When the IRQ handler notices that SYNC is set, it 3146adfc5217SJeff Kirsher * disables interrupts and returns. 3147adfc5217SJeff Kirsher * 3148adfc5217SJeff Kirsher * When all outstanding IRQ handlers have returned after 3149adfc5217SJeff Kirsher * the SYNC flag has been set, the setter can be assured 3150adfc5217SJeff Kirsher * that interrupts will no longer get run. 3151adfc5217SJeff Kirsher * 3152adfc5217SJeff Kirsher * In this way all SMP driver locks are never acquired 3153adfc5217SJeff Kirsher * in hw IRQ context, only sw IRQ context or lower. 3154adfc5217SJeff Kirsher */ 3155adfc5217SJeff Kirsher unsigned int irq_sync; 3156adfc5217SJeff Kirsher 3157adfc5217SJeff Kirsher /* SMP locking strategy: 3158adfc5217SJeff Kirsher * 3159adfc5217SJeff Kirsher * lock: Held during reset, PHY access, timer, and when 3160adfc5217SJeff Kirsher * updating tg3_flags. 3161adfc5217SJeff Kirsher * 3162adfc5217SJeff Kirsher * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 3163adfc5217SJeff Kirsher * netif_tx_lock when it needs to call 3164adfc5217SJeff Kirsher * netif_wake_queue. 3165adfc5217SJeff Kirsher * 3166adfc5217SJeff Kirsher * Both of these locks are to be held with BH safety. 3167adfc5217SJeff Kirsher * 3168adfc5217SJeff Kirsher * Because the IRQ handler, tg3_poll, and tg3_start_xmit 3169adfc5217SJeff Kirsher * are running lockless, it is necessary to completely 3170adfc5217SJeff Kirsher * quiesce the chip with tg3_netif_stop and tg3_full_lock 3171adfc5217SJeff Kirsher * before reconfiguring the device. 3172adfc5217SJeff Kirsher * 3173adfc5217SJeff Kirsher * indirect_lock: Held when accessing registers indirectly 3174adfc5217SJeff Kirsher * with IRQ disabling. 3175adfc5217SJeff Kirsher */ 3176adfc5217SJeff Kirsher spinlock_t lock; 3177adfc5217SJeff Kirsher spinlock_t indirect_lock; 3178adfc5217SJeff Kirsher 3179adfc5217SJeff Kirsher u32 (*read32) (struct tg3 *, u32); 3180adfc5217SJeff Kirsher void (*write32) (struct tg3 *, u32, u32); 3181adfc5217SJeff Kirsher u32 (*read32_mbox) (struct tg3 *, u32); 3182adfc5217SJeff Kirsher void (*write32_mbox) (struct tg3 *, u32, 3183adfc5217SJeff Kirsher u32); 3184adfc5217SJeff Kirsher void __iomem *regs; 3185adfc5217SJeff Kirsher void __iomem *aperegs; 3186adfc5217SJeff Kirsher struct net_device *dev; 3187adfc5217SJeff Kirsher struct pci_dev *pdev; 3188adfc5217SJeff Kirsher 3189adfc5217SJeff Kirsher u32 coal_now; 3190adfc5217SJeff Kirsher u32 msg_enable; 3191adfc5217SJeff Kirsher 3192be947307SMatt Carlson struct ptp_clock_info ptp_info; 3193be947307SMatt Carlson struct ptp_clock *ptp_clock; 3194be947307SMatt Carlson s64 ptp_adjust; 3195b22f21f7SPavan Chebbi u8 ptp_txts_retrycnt; 3196be947307SMatt Carlson 3197adfc5217SJeff Kirsher /* begin "tx thread" cacheline section */ 3198adfc5217SJeff Kirsher void (*write32_tx_mbox) (struct tg3 *, u32, 3199adfc5217SJeff Kirsher u32); 3200a4cb428dSMatt Carlson u32 dma_limit; 32010968169cSMichael Chan u32 txq_req; 320249a359e3SMichael Chan u32 txq_cnt; 32039102426aSMichael Chan u32 txq_max; 3204adfc5217SJeff Kirsher 3205adfc5217SJeff Kirsher /* begin "rx thread" cacheline section */ 3206adfc5217SJeff Kirsher struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 3207adfc5217SJeff Kirsher void (*write32_rx_mbox) (struct tg3 *, u32, 3208adfc5217SJeff Kirsher u32); 3209adfc5217SJeff Kirsher u32 rx_copy_thresh; 3210adfc5217SJeff Kirsher u32 rx_std_ring_mask; 3211adfc5217SJeff Kirsher u32 rx_jmb_ring_mask; 3212adfc5217SJeff Kirsher u32 rx_ret_ring_mask; 3213adfc5217SJeff Kirsher u32 rx_pending; 3214adfc5217SJeff Kirsher u32 rx_jumbo_pending; 3215adfc5217SJeff Kirsher u32 rx_std_max_post; 3216adfc5217SJeff Kirsher u32 rx_offset; 3217adfc5217SJeff Kirsher u32 rx_pkt_map_sz; 32180968169cSMichael Chan u32 rxq_req; 321949a359e3SMichael Chan u32 rxq_cnt; 32209102426aSMichael Chan u32 rxq_max; 32217ae52890SMichael Chan bool rx_refill; 3222adfc5217SJeff Kirsher 3223adfc5217SJeff Kirsher 3224adfc5217SJeff Kirsher /* begin "everything else" cacheline(s) section */ 3225adfc5217SJeff Kirsher struct rtnl_link_stats64 net_stats_prev; 3226adfc5217SJeff Kirsher struct tg3_ethtool_stats estats_prev; 3227adfc5217SJeff Kirsher 3228adfc5217SJeff Kirsher DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS); 3229adfc5217SJeff Kirsher 3230adfc5217SJeff Kirsher union { 3231adfc5217SJeff Kirsher unsigned long phy_crc_errors; 3232adfc5217SJeff Kirsher unsigned long last_event_jiffies; 3233adfc5217SJeff Kirsher }; 3234adfc5217SJeff Kirsher 3235adfc5217SJeff Kirsher struct timer_list timer; 3236adfc5217SJeff Kirsher u16 timer_counter; 3237adfc5217SJeff Kirsher u16 timer_multiplier; 3238adfc5217SJeff Kirsher u32 timer_offset; 3239adfc5217SJeff Kirsher u16 asf_counter; 3240adfc5217SJeff Kirsher u16 asf_multiplier; 3241adfc5217SJeff Kirsher 3242adfc5217SJeff Kirsher /* 1 second counter for transient serdes link events */ 3243adfc5217SJeff Kirsher u32 serdes_counter; 3244adfc5217SJeff Kirsher #define SERDES_AN_TIMEOUT_5704S 2 3245adfc5217SJeff Kirsher #define SERDES_PARALLEL_DET_TIMEOUT 1 3246adfc5217SJeff Kirsher #define SERDES_AN_TIMEOUT_5714S 1 3247adfc5217SJeff Kirsher 3248adfc5217SJeff Kirsher struct tg3_link_config link_config; 3249adfc5217SJeff Kirsher struct tg3_bufmgr_config bufmgr_config; 3250adfc5217SJeff Kirsher 3251adfc5217SJeff Kirsher /* cache h/w values, often passed straight to h/w */ 3252adfc5217SJeff Kirsher u32 rx_mode; 3253adfc5217SJeff Kirsher u32 tx_mode; 3254adfc5217SJeff Kirsher u32 mac_mode; 3255adfc5217SJeff Kirsher u32 mi_mode; 3256adfc5217SJeff Kirsher u32 misc_host_ctrl; 3257adfc5217SJeff Kirsher u32 grc_mode; 3258adfc5217SJeff Kirsher u32 grc_local_ctrl; 3259adfc5217SJeff Kirsher u32 dma_rwctrl; 3260adfc5217SJeff Kirsher u32 coalesce_mode; 3261adfc5217SJeff Kirsher u32 pwrmgmt_thresh; 3262be947307SMatt Carlson u32 rxptpctl; 3263adfc5217SJeff Kirsher 3264adfc5217SJeff Kirsher /* PCI block */ 3265adfc5217SJeff Kirsher u32 pci_chip_rev_id; 3266adfc5217SJeff Kirsher u16 pci_cmd; 3267adfc5217SJeff Kirsher u8 pci_cacheline_sz; 3268adfc5217SJeff Kirsher u8 pci_lat_timer; 3269adfc5217SJeff Kirsher 3270adfc5217SJeff Kirsher int pci_fn; 3271adfc5217SJeff Kirsher int msi_cap; 3272adfc5217SJeff Kirsher int pcix_cap; 3273adfc5217SJeff Kirsher int pcie_readrq; 3274adfc5217SJeff Kirsher 3275adfc5217SJeff Kirsher struct mii_bus *mdio_bus; 327634655ad6SMatt Carlson int old_link; 3277adfc5217SJeff Kirsher 3278adfc5217SJeff Kirsher u8 phy_addr; 32798151ad57SMichael Chan u8 phy_ape_lock; 3280adfc5217SJeff Kirsher 3281adfc5217SJeff Kirsher /* PHY info */ 3282adfc5217SJeff Kirsher u32 phy_id; 3283adfc5217SJeff Kirsher #define TG3_PHY_ID_MASK 0xfffffff0 3284adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5400 0x60008040 3285adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5401 0x60008050 3286adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5411 0x60008070 3287adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5701 0x60008110 3288adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5703 0x60008160 3289adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5704 0x60008190 3290adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5705 0x600081a0 3291adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5750 0x60008180 3292adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5752 0x60008100 3293adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5714 0x60008340 3294adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5780 0x60008350 3295adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5755 0xbc050cc0 3296adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5787 0xbc050ce0 3297adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5756 0xbc050ed0 3298adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5784 0xbc050fa0 3299adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5761 0xbc050fd0 3300adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5718C 0x5c0d8a00 3301adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5718S 0xbc050ff0 3302adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM57765 0x5c0d8a40 3303adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5719C 0x5c0d8a20 3304adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5720C 0x5c0d8b60 3305c65a17f4SMichael Chan #define TG3_PHY_ID_BCM5762 0x85803780 3306adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM5906 0xdc00ac40 3307adfc5217SJeff Kirsher #define TG3_PHY_ID_BCM8002 0x60010140 3308adfc5217SJeff Kirsher #define TG3_PHY_ID_INVALID 0xffffffff 3309adfc5217SJeff Kirsher 3310adfc5217SJeff Kirsher #define PHY_ID_RTL8211C 0x001cc910 3311adfc5217SJeff Kirsher #define PHY_ID_RTL8201E 0x00008200 3312adfc5217SJeff Kirsher 3313adfc5217SJeff Kirsher #define TG3_PHY_ID_REV_MASK 0x0000000f 3314adfc5217SJeff Kirsher #define TG3_PHY_REV_BCM5401_B0 0x1 3315adfc5217SJeff Kirsher 3316adfc5217SJeff Kirsher /* This macro assumes the passed PHY ID is 3317adfc5217SJeff Kirsher * already masked with TG3_PHY_ID_MASK. 3318adfc5217SJeff Kirsher */ 3319adfc5217SJeff Kirsher #define TG3_KNOWN_PHY_ID(X) \ 3320adfc5217SJeff Kirsher ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 3321adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 3322adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 3323adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 3324adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 3325adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 3326adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 3327adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 3328adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 3329adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 3330c65a17f4SMichael Chan (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \ 3331adfc5217SJeff Kirsher (X) == TG3_PHY_ID_BCM8002) 3332adfc5217SJeff Kirsher 3333adfc5217SJeff Kirsher u32 phy_flags; 3334adfc5217SJeff Kirsher #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 3335adfc5217SJeff Kirsher #define TG3_PHYFLG_IS_CONNECTED 0x00000002 3336adfc5217SJeff Kirsher #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 3337fdad8de4SNithin Sujir #define TG3_PHYFLG_USER_CONFIGURED 0x00000008 3338adfc5217SJeff Kirsher #define TG3_PHYFLG_PHY_SERDES 0x00000010 3339adfc5217SJeff Kirsher #define TG3_PHYFLG_MII_SERDES 0x00000020 3340adfc5217SJeff Kirsher #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 3341adfc5217SJeff Kirsher TG3_PHYFLG_MII_SERDES) 3342adfc5217SJeff Kirsher #define TG3_PHYFLG_IS_FET 0x00000040 3343adfc5217SJeff Kirsher #define TG3_PHYFLG_10_100_ONLY 0x00000080 3344adfc5217SJeff Kirsher #define TG3_PHYFLG_ENABLE_APD 0x00000100 3345adfc5217SJeff Kirsher #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 3346adfc5217SJeff Kirsher #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 3347adfc5217SJeff Kirsher #define TG3_PHYFLG_JITTER_BUG 0x00000800 3348adfc5217SJeff Kirsher #define TG3_PHYFLG_ADJUST_TRIM 0x00001000 3349adfc5217SJeff Kirsher #define TG3_PHYFLG_ADC_BUG 0x00002000 3350adfc5217SJeff Kirsher #define TG3_PHYFLG_5704_A0_BUG 0x00004000 3351adfc5217SJeff Kirsher #define TG3_PHYFLG_BER_BUG 0x00008000 3352adfc5217SJeff Kirsher #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3353adfc5217SJeff Kirsher #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3354adfc5217SJeff Kirsher #define TG3_PHYFLG_EEE_CAP 0x00040000 3355942d1af0SNithin Sujir #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 3356942d1af0SNithin Sujir #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 3357e348c5e7SMatt Carlson #define TG3_PHYFLG_MDIX_STATE 0x00200000 33587c786065SNithin Sujir #define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000 3359adfc5217SJeff Kirsher 3360adfc5217SJeff Kirsher u32 led_ctrl; 3361adfc5217SJeff Kirsher u32 phy_otp; 3362adfc5217SJeff Kirsher u32 setlpicnt; 3363bcebcc46SMatt Carlson u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE]; 3364adfc5217SJeff Kirsher 3365adfc5217SJeff Kirsher #define TG3_BPN_SIZE 24 3366adfc5217SJeff Kirsher char board_part_number[TG3_BPN_SIZE]; 3367adfc5217SJeff Kirsher #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 3368adfc5217SJeff Kirsher char fw_ver[TG3_VER_SIZE]; 3369adfc5217SJeff Kirsher u32 nic_sram_data_cfg; 3370adfc5217SJeff Kirsher u32 pci_clock_ctrl; 3371adfc5217SJeff Kirsher struct pci_dev *pdev_peer; 3372adfc5217SJeff Kirsher 3373adfc5217SJeff Kirsher struct tg3_hw_stats *hw_stats; 3374adfc5217SJeff Kirsher dma_addr_t stats_mapping; 3375adfc5217SJeff Kirsher struct work_struct reset_task; 3376b22f21f7SPavan Chebbi struct sk_buff *tx_tstamp_skb; 3377b22f21f7SPavan Chebbi u64 pre_tx_ts; 3378adfc5217SJeff Kirsher 3379adfc5217SJeff Kirsher int nvram_lock_cnt; 3380adfc5217SJeff Kirsher u32 nvram_size; 3381adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_2KB 0x00000800 3382adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_64KB 0x00010000 3383adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_128KB 0x00020000 3384adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_256KB 0x00040000 3385adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_512KB 0x00080000 3386adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_1MB 0x00100000 3387adfc5217SJeff Kirsher #define TG3_NVRAM_SIZE_2MB 0x00200000 3388adfc5217SJeff Kirsher 3389adfc5217SJeff Kirsher u32 nvram_pagesize; 3390adfc5217SJeff Kirsher u32 nvram_jedecnum; 3391adfc5217SJeff Kirsher 3392adfc5217SJeff Kirsher #define JEDEC_ATMEL 0x1f 3393adfc5217SJeff Kirsher #define JEDEC_ST 0x20 3394adfc5217SJeff Kirsher #define JEDEC_SAIFUN 0x4f 3395adfc5217SJeff Kirsher #define JEDEC_SST 0xbf 33968a4816caSPrashant Sreedharan #define JEDEC_MACRONIX 0xc2 3397adfc5217SJeff Kirsher 3398adfc5217SJeff Kirsher #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB 3399adfc5217SJeff Kirsher #define ATMEL_AT24C02_PAGE_SIZE (8) 3400adfc5217SJeff Kirsher 3401adfc5217SJeff Kirsher #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3402adfc5217SJeff Kirsher #define ATMEL_AT24C64_PAGE_SIZE (32) 3403adfc5217SJeff Kirsher 3404adfc5217SJeff Kirsher #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3405adfc5217SJeff Kirsher #define ATMEL_AT24C512_PAGE_SIZE (128) 3406adfc5217SJeff Kirsher 3407adfc5217SJeff Kirsher #define ATMEL_AT45DB0X1B_PAGE_POS 9 3408adfc5217SJeff Kirsher #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3409adfc5217SJeff Kirsher 3410adfc5217SJeff Kirsher #define ATMEL_AT25F512_PAGE_SIZE 256 3411adfc5217SJeff Kirsher 3412adfc5217SJeff Kirsher #define ST_M45PEX0_PAGE_SIZE 256 3413adfc5217SJeff Kirsher 3414adfc5217SJeff Kirsher #define SAIFUN_SA25F0XX_PAGE_SIZE 256 3415adfc5217SJeff Kirsher 3416adfc5217SJeff Kirsher #define SST_25VF0X0_PAGE_SIZE 4098 3417adfc5217SJeff Kirsher 3418adfc5217SJeff Kirsher unsigned int irq_max; 3419adfc5217SJeff Kirsher unsigned int irq_cnt; 3420adfc5217SJeff Kirsher 3421adfc5217SJeff Kirsher struct ethtool_coalesce coal; 3422*d80a5233SHeiner Kallweit struct ethtool_keee eee; 3423adfc5217SJeff Kirsher 3424adfc5217SJeff Kirsher /* firmware info */ 3425adfc5217SJeff Kirsher const char *fw_needed; 3426adfc5217SJeff Kirsher const struct firmware *fw; 3427adfc5217SJeff Kirsher u32 fw_len; /* includes BSS */ 3428aed93e0bSMichael Chan 3429aed93e0bSMichael Chan struct device *hwmon_dev; 3430f4a46d1fSNithin Nayak Sujir bool link_up; 34310486a063SIvan Vecera bool pcierr_recovery; 3432506b0a39SPrashant Sreedharan 3433506b0a39SPrashant Sreedharan u32 ape_hb; 3434506b0a39SPrashant Sreedharan unsigned long ape_hb_interval; 3435506b0a39SPrashant Sreedharan unsigned long ape_hb_jiffies; 3436adfc5217SJeff Kirsher }; 3437adfc5217SJeff Kirsher 34384153577aSJoe Perches /* Accessor macros for chip and asic attributes 34394153577aSJoe Perches * 34404153577aSJoe Perches * nb: Using static inlines equivalent to the accessor macros generates 34414153577aSJoe Perches * larger object code with gcc 4.7. 34424153577aSJoe Perches * Using statement expression macros to check tp with 34434153577aSJoe Perches * typecheck(struct tg3 *, tp) also creates larger objects. 34444153577aSJoe Perches */ 34454153577aSJoe Perches #define tg3_chip_rev_id(tp) \ 34464153577aSJoe Perches ((tp)->pci_chip_rev_id) 34474153577aSJoe Perches #define tg3_asic_rev(tp) \ 34484153577aSJoe Perches ((tp)->pci_chip_rev_id >> 12) 34494153577aSJoe Perches #define tg3_chip_rev(tp) \ 34504153577aSJoe Perches ((tp)->pci_chip_rev_id >> 8) 34514153577aSJoe Perches 3452adfc5217SJeff Kirsher #endif /* !(_T3_H) */ 3453