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/freebsd/sys/x86/include/
H A Dapicreg.h40 * is 0xfee00000.
55 * 0A0 Processor Priority Register R
56 * 0B0 EOI Register W
57 * 0C0 RRR Remote read R
58 * 0D0 Logical Destination R/W
59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W
60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
195 LAPIC_ID = 0x2,
196 LAPIC_VERSION = 0x3,
[all …]
/freebsd/sys/dev/sound/macio/
H A Ddavbusreg.h36 #define DAVBUS_SOUND_CTRL 0x00
37 #define DAVBUS_CODEC_CTRL 0x10
38 #define DAVBUS_CODEC_STATUS 0x20
39 #define DAVBUS_CLIP_COUNT 0x30
40 #define DAVBUS_BYTE_SWAP 0x40
44 * but the controller itself uses subframe 0 to communicate with the codec.
49 #define DAVBUS_INPUT_SUBFRAME0 0x00000001
50 #define DAVBUS_INPUT_SUBFRAME1 0x00000002
51 #define DAVBUS_INPUT_SUBFRAME2 0x00000004
52 #define DAVBUS_INPUT_SUBFRAME3 0x00000008
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/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_init.h114 U8 LUN[8]; /* 0Ch */
125 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
126 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
127 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
129 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
130 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
131 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
133 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
137 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
138 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
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/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DTypeIndex.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
27 None = 0x0000, // uncharacterized type (no type)
28 Void = 0x0003, // void
29 NotTranslated = 0x0007, // type not translated by cvpack
30 HResult = 0x0008, // OLE/COM HRESULT
32 SignedCharacter = 0x0010, // 8 bit signed
33 UnsignedCharacter = 0x0020, // 8 bit unsigned
34 NarrowCharacter = 0x0070, // really a char
35 WideCharacter = 0x0071, // wide char
36 Character16 = 0x007a, // char16_t
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/freebsd/sys/dev/sound/pci/
H A Dallegro_reg.h49 #define PCI_LEGACY_AUDIO_CTRL 0x40
50 #define SOUND_BLASTER_ENABLE 0x00000001
51 #define FM_SYNTHESIS_ENABLE 0x00000002
52 #define GAME_PORT_ENABLE 0x00000004
53 #define MPU401_IO_ENABLE 0x00000008
54 #define MPU401_IRQ_ENABLE 0x00000010
55 #define ALIAS_10BIT_IO 0x00000020
56 #define SB_DMA_MASK 0x000000C0
57 #define SB_DMA_0 0x00000040
58 #define SB_DMA_1 0x00000040
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/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
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/freebsd/sys/dev/ofw/
H A Dofw_pci.h68 #define OFW_PCI_PHYS_HI_NONRELOCATABLE 0x80000000
69 #define OFW_PCI_PHYS_HI_PREFETCHABLE 0x40000000
70 #define OFW_PCI_PHYS_HI_ALIASED 0x20000000
71 #define OFW_PCI_PHYS_HI_SPACEMASK 0x03000000
72 #define OFW_PCI_PHYS_HI_BUSMASK 0x00ff0000
74 #define OFW_PCI_PHYS_HI_DEVICEMASK 0x0000f800
76 #define OFW_PCI_PHYS_HI_FUNCTIONMASK 0x00000700
78 #define OFW_PCI_PHYS_HI_REGISTERMASK 0x000000ff
80 #define OFW_PCI_PHYS_HI_SPACE_CONFIG 0x00000000
81 #define OFW_PCI_PHYS_HI_SPACE_IO 0x01000000
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/freebsd/sys/dev/bhnd/
H A Dbhndreg.h32 #define BHND_DEFAULT_CHIPC_ADDR 0x18000000
38 #define BHND_DEFAULT_CORE_SIZE 0x1000
43 #define BHND_DEFAULT_ENUM_SIZE 0x00100000
56 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
57 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
58 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
59 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
60 #define BHND_CCS_FORCE_MASK 0x0000000F
62 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
63 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
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/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipc_spi.h43 #define CHIPC_SPI_FLASHCTL 0x00
44 #define CHIPC_SPI_FLASHCTL_OPCODE 0x000000ff
45 #define CHIPC_SPI_FLASHCTL_ACTION 0x00000700 //
48 * action 0 - read current MISO byte to data register (interactive mode)
59 #define CHIPC_SPI_FLASHCTL_CSACTIVE 0x00001000
60 #define CHIPC_SPI_FLASHCTL_START 0x80000000 //same as BUSY
61 #define CHIPC_SPI_FLASHCTL_BUSY 0x80000000 //same as BUSY
62 #define CHIPC_SPI_FLASHADDR 0x04
63 #define CHIPC_SPI_FLASHDATA 0x08
75 #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_res, 0, 0, \
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H A Dchipcreg.h46 #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0)
50 #define CHIPC_ID 0x00
51 #define CHIPC_CAPABILITIES 0x04
52 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */
53 #define CHIPC_BIST 0x0C
55 #define CHIPC_OTPST 0x10 /**< otp status */
56 #define CHIPC_OTPCTRL 0x14 /**< otp control */
57 #define CHIPC_OTPPROG 0x18
58 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */
60 #define CHIPC_INTST 0x20 /**< interrupt status */
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/freebsd/sys/dev/rl/
H A Dif_rlreg.h36 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
37 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
38 #define RL_IDR2 0x0002
39 #define RL_IDR3 0x0003
40 #define RL_IDR4 0x0004
41 #define RL_IDR5 0x0005
43 #define RL_MAR0 0x0008 /* Multicast hash table */
44 #define RL_MAR1 0x0009
45 #define RL_MAR2 0x000A
46 #define RL_MAR3 0x000B
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/freebsd/sys/arm/ti/
H A Dti_adcreg.h30 #define ADC_REVISION 0x000
31 #define ADC_REV_SCHEME_MSK 0xc0000000
33 #define ADC_REV_FUNC_MSK 0x0fff0000
35 #define ADC_REV_RTL_MSK 0x0000f800
37 #define ADC_REV_MAJOR_MSK 0x00000700
39 #define ADC_REV_CUSTOM_MSK 0x000000c0
41 #define ADC_REV_MINOR_MSK 0x0000003f
42 #define ADC_SYSCFG 0x010
43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0
45 #define ADC_IRQSTATUS_RAW 0x024
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-vi.yaml15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
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H A Dnvidia,tegra20-host1x.yaml175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
211 - description: host1x syncpoint interrupt 0
235 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
251 reg = <0x50000000 0x00024000>;
252 interrupts = <0 65 0x04>, /* mpcore syncpt */
253 <0 67 0x04>; /* mpcore general */
263 ranges = <0x54000000 0x54000000 0x04000000>;
267 reg = <0x54040000 0x00040000>;
268 interrupts = <0 68 0x04>;
276 reg = <0x54080000 0x00040000>;
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/freebsd/sys/dev/usb/net/
H A Dif_axgereg.h29 #define AXGE_ACCESS_MAC 0x01
30 #define AXGE_ACCESS_PHY 0x02
31 #define AXGE_ACCESS_WAKEUP 0x03
32 #define AXGE_ACCESS_EEPROM 0x04
33 #define AXGE_ACCESS_EFUSE 0x05
34 #define AXGE_RELOAD_EEPROM_EFUSE 0x06
35 #define AXGE_FW_MODE 0x08
36 #define AXGE_WRITE_EFUSE_EN 0x09
37 #define AXGE_WRITE_EFUSE_DIS 0x0A
38 #define AXGE_ACCESS_MFAB 0x10
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9462_2p1_initvals.h63 {0x00000008, 0x00000000},
64 {0x00000030, 0x000e0085},
65 {0x00000034, 0x00000005},
66 {0x00000040, 0x00000000},
67 {0x00000044, 0x00000000},
68 {0x00000048, 0x00000008},
69 {0x0000004c, 0x00000010},
70 {0x00000050, 0x00000000},
71 {0x00001040, 0x002ffc0f},
72 {0x00001044, 0x002ffc0f},
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/freebsd/sys/dev/ath/ath_hal/
H A Dah_btcoex.h26 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
44 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
60 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
71 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
72 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
74 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
76 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
78 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
80 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
81 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
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/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211.h24 #define AR5211_MAGIC 0x19570405
27 #define AC_BK 0
34 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
36 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
38 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
50 #define INIT_CONFIG_STATUS 0x00000000
51 #define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
52 #define INIT_IQCAL_LOG_COUNT_MAX 0xF
53 #define INIT_BCON_CNTRL_REG 0x00000000
55 #define INIT_BEACON_PERIOD 0xffff
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/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210.h22 #define AR5210_MAGIC 0x19980124
24 #if 0
30 #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32 #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36 #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37 #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsampidefs.h36 #define OPC_INB_ECHO 0x001 /* */
38 #define OPC_INB_PHYSTART 0x004 /* */
39 #define OPC_INB_PHYSTOP 0x005 /* */
40 #define OPC_INB_SSPINIIOSTART 0x006 /* */
41 #define OPC_INB_SSPINITMSTART 0x007 /* */
42 #define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */
43 #define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */
44 #define OPC_INB_SSPTGTIOSTART 0x00a /* */
45 #define OPC_INB_SSPTGTRSPSTART 0x00b /* */
46 #define OPC_INB_SSP_ABORT 0x00f /* */
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/freebsd/sys/dev/ste/
H A Dif_stereg.h39 #define ST_VENDORID 0x13F0
40 #define ST_DEVICEID_ST201_1 0x0200
41 #define ST_DEVICEID_ST201_2 0x0201
46 #define DL_VENDORID 0x1186
47 #define DL_DEVICEID_DL10050 0x1002
56 #define STE_DMACTL 0x00
57 #define STE_TX_DMALIST_PTR 0x04
58 #define STE_TX_DMABURST_THRESH 0x08
59 #define STE_TX_DMAURG_THRESH 0x09
60 #define STE_TX_DMAPOLL_PERIOD 0x0A
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/freebsd/sys/dev/mpi3mr/mpi/
H A Dmpi30_transport.h89 U8 Dev; /* 0x00 */
90 U8 Unit; /* 0x01 */
91 U8 Minor; /* 0x02 */
92 U8 Major; /* 0x03 */
105 #define MPI3_VERSION_MINOR (0)
107 #define MPI3_VERSION_DEV (0)
110 #define MPI3_DEVHANDLE_INVALID (0xFFFF)
117 U16 ProducerIndex; /* 0x00 */
118 U16 Reserved02; /* 0x02 */
119 U16 ConsumerIndex; /* 0x04 */
[all …]

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