14ad7e9b0SAdrian Chadd /*- 2*6e778a7eSPedro F. Giffuni * SPDX-License-Identifier: ISC 3*6e778a7eSPedro F. Giffuni * 44e96bf3aSLandon J. Fuller * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 54e96bf3aSLandon J. Fuller * Copyright (c) 2010 Broadcom Corporation 64ad7e9b0SAdrian Chadd * All rights reserved. 74ad7e9b0SAdrian Chadd * 84e96bf3aSLandon J. Fuller * Portions of this file were derived from the sbchipc.h header contributed by 94e96bf3aSLandon J. Fuller * Broadcom to to the Linux staging repository, as well as later revisions of 104e96bf3aSLandon J. Fuller * sbchipc.h distributed with the Asus RT-N16 firmware source code release. 114ad7e9b0SAdrian Chadd * 124e96bf3aSLandon J. Fuller * Permission to use, copy, modify, and/or distribute this software for any 134e96bf3aSLandon J. Fuller * purpose with or without fee is hereby granted, provided that the above 144e96bf3aSLandon J. Fuller * copyright notice and this permission notice appear in all copies. 154e96bf3aSLandon J. Fuller * 164e96bf3aSLandon J. Fuller * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 174e96bf3aSLandon J. Fuller * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 184e96bf3aSLandon J. Fuller * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 194e96bf3aSLandon J. Fuller * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 204e96bf3aSLandon J. Fuller * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 214e96bf3aSLandon J. Fuller * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 224e96bf3aSLandon J. Fuller * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 234ad7e9b0SAdrian Chadd */ 244ad7e9b0SAdrian Chadd 254ad7e9b0SAdrian Chadd #ifndef _BHND_BHNDREG_H_ 264ad7e9b0SAdrian Chadd #define _BHND_BHNDREG_H_ 274ad7e9b0SAdrian Chadd 284ad7e9b0SAdrian Chadd /** 294ad7e9b0SAdrian Chadd * The default address at which the ChipCommon core is mapped on all siba(4) 3089294a78SLandon J. Fuller * devices, and most (all?) bcma(4) devices. 314ad7e9b0SAdrian Chadd */ 324ad7e9b0SAdrian Chadd #define BHND_DEFAULT_CHIPC_ADDR 0x18000000 334ad7e9b0SAdrian Chadd 344ad7e9b0SAdrian Chadd /** 354ad7e9b0SAdrian Chadd * The standard size of a primary BHND_PORT_DEVICE or BHND_PORT_AGENT 364ad7e9b0SAdrian Chadd * register block. 374ad7e9b0SAdrian Chadd */ 384ad7e9b0SAdrian Chadd #define BHND_DEFAULT_CORE_SIZE 0x1000 394ad7e9b0SAdrian Chadd 4089294a78SLandon J. Fuller /** 4189294a78SLandon J. Fuller * The standard size of the siba(4) and bcma(4) enumeration space. 4289294a78SLandon J. Fuller */ 4389294a78SLandon J. Fuller #define BHND_DEFAULT_ENUM_SIZE 0x00100000 444ad7e9b0SAdrian Chadd 454e96bf3aSLandon J. Fuller /* 464e96bf3aSLandon J. Fuller * Common per-core clock control/status register available on PMU-equipped 474e96bf3aSLandon J. Fuller * devices. 484e96bf3aSLandon J. Fuller * 494e96bf3aSLandon J. Fuller * Clock Mode Name Description 504e96bf3aSLandon J. Fuller * High Throughput (HT) Full bandwidth, low latency. Generally supplied 514e96bf3aSLandon J. Fuller * from PLL. 524e96bf3aSLandon J. Fuller * Active Low Power (ALP) Register access, low speed DMA. 534e96bf3aSLandon J. Fuller * Idle Low Power (ILP) No interconnect activity, or if long latency 544e96bf3aSLandon J. Fuller * is permitted. 554e96bf3aSLandon J. Fuller */ 564e96bf3aSLandon J. Fuller #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */ 574e96bf3aSLandon J. Fuller #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */ 584e96bf3aSLandon J. Fuller #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */ 594e96bf3aSLandon J. Fuller #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */ 604e96bf3aSLandon J. Fuller #define BHND_CCS_FORCE_MASK 0x0000000F 614e96bf3aSLandon J. Fuller 624e96bf3aSLandon J. Fuller #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */ 634e96bf3aSLandon J. Fuller #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */ 644e96bf3aSLandon J. Fuller #define BHND_CCS_AREQ_MASK 0x00000018 654e96bf3aSLandon J. Fuller 664e96bf3aSLandon J. Fuller #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */ 674e96bf3aSLandon J. Fuller 684e96bf3aSLandon J. Fuller #define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */ 694e96bf3aSLandon J. Fuller #define BHND_CCS_ERSRC_REQ_SHIFT 8 704e96bf3aSLandon J. Fuller #define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */ 714e96bf3aSLandon J. Fuller 724e96bf3aSLandon J. Fuller #define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */ 734e96bf3aSLandon J. Fuller #define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */ 744e96bf3aSLandon J. Fuller #define BHND_CCS_AVAIL_MASK 0x00030000 754e96bf3aSLandon J. Fuller 764e96bf3aSLandon J. Fuller #define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */ 774e96bf3aSLandon J. Fuller #define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */ 784e96bf3aSLandon J. Fuller #define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */ 794e96bf3aSLandon J. Fuller #define BHND_CCS_ERSRC_STS_SHIFT 24 804e96bf3aSLandon J. Fuller 814e96bf3aSLandon J. Fuller #define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */ 824e96bf3aSLandon J. Fuller #define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */ 834e96bf3aSLandon J. Fuller 844e96bf3aSLandon J. Fuller #define BHND_CCS_GET_FLAG(_value, _flag) \ 854e96bf3aSLandon J. Fuller (((_value) & _flag) != 0) 864e96bf3aSLandon J. Fuller #define BHND_CCS_GET_BITS(_value, _field) \ 874e96bf3aSLandon J. Fuller (((_value) & _field ## _MASK) >> _field ## _SHIFT) 884e96bf3aSLandon J. Fuller #define BHND_CCS_SET_BITS(_value, _field) \ 894e96bf3aSLandon J. Fuller (((_value) << _field ## _SHIFT) & _field ## _MASK) 904e96bf3aSLandon J. Fuller 914ad7e9b0SAdrian Chadd #endif /* _BHND_BHNDREG_H_ */ 92