Lines Matching +full:0 +full:x00000700
114 U8 LUN[8]; /* 0Ch */
125 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
126 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
127 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
129 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
130 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
131 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
133 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
137 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
138 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
139 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
140 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
141 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00)
142 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00)
146 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
147 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
148 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000)
149 #define MPI_SCSIIO_CONTROL_READ (0x02000000)
151 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000)
154 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
155 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
156 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100)
157 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
158 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400)
159 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500)
160 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700)
162 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000)
163 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000)
164 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000)
165 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000)
166 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000)
167 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000)
168 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000)
169 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000)
170 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000)
184 U8 SCSIStatus; /* 0Ch */
185 U8 SCSIState; /* 0Dh */
186 U16 IOCStatus; /* 0Eh */
198 #define MPI_SCSI_STATUS_SUCCESS (0x00)
199 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02)
200 #define MPI_SCSI_STATUS_CONDITION_MET (0x04)
201 #define MPI_SCSI_STATUS_BUSY (0x08)
202 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10)
203 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
204 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
205 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22)
206 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28)
207 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30)
209 #define MPI_SCSI_STATUS_FCPEXT_DEVICE_LOGGED_OUT (0x80)
210 #define MPI_SCSI_STATUS_FCPEXT_NO_LINK (0x81)
211 #define MPI_SCSI_STATUS_FCPEXT_UNASSIGNED (0x82)
215 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01)
216 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02)
217 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04)
218 #define MPI_SCSI_STATE_TERMINATED (0x08)
219 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10)
220 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20)
225 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000)
226 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000)
227 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000)
228 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000)
229 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000)
230 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000)
231 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000)
233 #define MPI_SCSI_TASKTAG_UNKNOWN (0xFFFF)
296 U8 LUN[8]; /* 0Ch */
320 #define MPI_SCSIIO32_MSGFLGS_SENSE_WIDTH (0x01)
321 #define MPI_SCSIIO32_MSGFLGS_32_SENSE_WIDTH (0x00)
322 #define MPI_SCSIIO32_MSGFLGS_64_SENSE_WIDTH (0x01)
324 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOCATION (0x02)
325 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_HOST (0x00)
326 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_IOC (0x02)
328 #define MPI_SCSIIO32_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
329 #define MPI_SCSIIO32_MSGFLGS_SGL_OFFSETS_CHAINS (0x08)
330 #define MPI_SCSIIO32_MSGFLGS_MULTICAST (0x10)
331 #define MPI_SCSIIO32_MSGFLGS_BIDIRECTIONAL (0x20)
332 #define MPI_SCSIIO32_MSGFLGS_LARGE_CDB (0x40)
335 #define MPI_SCSIIO32_FLAGS_FORM_MASK (0x03)
336 #define MPI_SCSIIO32_FLAGS_FORM_SCSIID (0x00)
337 #define MPI_SCSIIO32_FLAGS_FORM_WWID (0x01)
340 #define MPI_SCSIIO32_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
341 #define MPI_SCSIIO32_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
342 #define MPI_SCSIIO32_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
343 #define MPI_SCSIIO32_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
344 #define MPI_SCSIIO32_LUN_LEVEL_1_WORD (0xFF00)
345 #define MPI_SCSIIO32_LUN_LEVEL_1_DWORD (0x0000FF00)
348 #define MPI_SCSIIO32_CONTROL_DATADIRECTION_MASK (0x03000000)
349 #define MPI_SCSIIO32_CONTROL_NODATATRANSFER (0x00000000)
350 #define MPI_SCSIIO32_CONTROL_WRITE (0x01000000)
351 #define MPI_SCSIIO32_CONTROL_READ (0x02000000)
352 #define MPI_SCSIIO32_CONTROL_BIDIRECTIONAL (0x03000000)
354 #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_MASK (0xFC000000)
357 #define MPI_SCSIIO32_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
358 #define MPI_SCSIIO32_CONTROL_SIMPLEQ (0x00000000)
359 #define MPI_SCSIIO32_CONTROL_HEADOFQ (0x00000100)
360 #define MPI_SCSIIO32_CONTROL_ORDEREDQ (0x00000200)
361 #define MPI_SCSIIO32_CONTROL_ACAQ (0x00000400)
362 #define MPI_SCSIIO32_CONTROL_UNTAGGED (0x00000500)
363 #define MPI_SCSIIO32_CONTROL_NO_DISCONNECT (0x00000700)
365 #define MPI_SCSIIO32_CONTROL_TASKMANAGE_MASK (0x00FF0000)
366 #define MPI_SCSIIO32_CONTROL_OBSOLETE (0x00800000)
367 #define MPI_SCSIIO32_CONTROL_CLEAR_ACA_RSV (0x00400000)
368 #define MPI_SCSIIO32_CONTROL_TARGET_RESET (0x00200000)
369 #define MPI_SCSIIO32_CONTROL_LUN_RESET_RSV (0x00100000)
370 #define MPI_SCSIIO32_CONTROL_RESERVED (0x00080000)
371 #define MPI_SCSIIO32_CONTROL_CLR_TASK_SET_RSV (0x00040000)
372 #define MPI_SCSIIO32_CONTROL_ABORT_TASK_SET (0x00020000)
373 #define MPI_SCSIIO32_CONTROL_RESERVED2 (0x00010000)
376 #define MPI_SCSIIO32_EEDPFLAGS_MASK_OP (0x0007)
377 #define MPI_SCSIIO32_EEDPFLAGS_NOOP_OP (0x0000)
378 #define MPI_SCSIIO32_EEDPFLAGS_CHK_OP (0x0001)
379 #define MPI_SCSIIO32_EEDPFLAGS_STRIP_OP (0x0002)
380 #define MPI_SCSIIO32_EEDPFLAGS_CHKRM_OP (0x0003)
381 #define MPI_SCSIIO32_EEDPFLAGS_INSERT_OP (0x0004)
382 #define MPI_SCSIIO32_EEDPFLAGS_REPLACE_OP (0x0006)
383 #define MPI_SCSIIO32_EEDPFLAGS_CHKREGEN_OP (0x0007)
385 #define MPI_SCSIIO32_EEDPFLAGS_PASS_REF_TAG (0x0008)
386 #define MPI_SCSIIO32_EEDPFLAGS_8_9THS_MODE (0x0010)
388 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_MASK (0x0700)
389 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_GUARD (0x0100)
390 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_REFTAG (0x0200)
391 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_LBATAG (0x0400)
394 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
395 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
396 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
397 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
411 U8 SCSIStatus; /* 0Ch */
412 U8 SCSIState; /* 0Dh */
413 U16 IOCStatus; /* 0Eh */
439 U8 LUN[8]; /* 0Ch */
447 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
448 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
449 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
450 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04)
451 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
452 #define MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
453 #define MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
454 #define MPI_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
457 #define MPI_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01)
459 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00)
460 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02)
461 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04)
463 #define MPI_SCSITASKMGMT_MSGFLAGS_SOFT_RESET_OPTION (0x08)
477 U8 Reserved2[2]; /* 0Ch */
478 U16 IOCStatus; /* 0Eh */
485 #define MPI_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
486 #define MPI_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
487 #define MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
488 #define MPI_SCSITASKMGMT_RSP_TM_FAILED (0x05)
489 #define MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
490 #define MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
491 #define MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
508 U32 SlotStatus; /* 0Ch */
518 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00)
519 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01)
522 #define MPI_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01)
523 #define MPI_SEP_REQ_FLAGS_BUS_TARGETID_ADDRESS (0x00)
526 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001)
527 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002)
528 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004)
529 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
530 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
531 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020)
532 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
533 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080)
534 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100)
535 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
536 #define MPI_SEP_REQ_SLOTSTATUS_REQ_CONSISTENCY_CHECK (0x00001000)
537 #define MPI_SEP_REQ_SLOTSTATUS_DISABLE (0x00002000)
538 #define MPI_SEP_REQ_SLOTSTATUS_REQ_RESERVED_DEVICE (0x00004000)
539 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
540 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000)
541 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000)
542 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000)
543 #define MPI_SEP_REQ_SLOTSTATUS_ACTIVE (0x00800000)
544 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000)
545 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000)
546 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000)
547 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000)
560 U16 Reserved3; /* 0Ch */
561 U16 IOCStatus; /* 0Eh */
571 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001)
572 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002)
573 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004)
574 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
575 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
576 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020)
577 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
578 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080)
579 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100)
580 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
581 #define MPI_SEP_REPLY_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000)
582 #define MPI_SEP_REPLY_SLOTSTATUS_DISABLE (0x00002000)
583 #define MPI_SEP_REPLY_SLOTSTATUS_RESERVED_DEVICE (0x00004000)
584 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000)
585 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
586 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000)
587 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000)
588 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000)
589 #define MPI_SEP_REPLY_SLOTSTATUS_ACTIVE (0x00800000)
590 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000)
591 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000)
592 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000)
593 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000)
594 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000)
595 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000)
596 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000)