Lines Matching +full:0 +full:x00000700
32 #define BHND_DEFAULT_CHIPC_ADDR 0x18000000
38 #define BHND_DEFAULT_CORE_SIZE 0x1000
43 #define BHND_DEFAULT_ENUM_SIZE 0x00100000
56 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
57 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
58 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
59 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
60 #define BHND_CCS_FORCE_MASK 0x0000000F
62 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
63 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
64 #define BHND_CCS_AREQ_MASK 0x00000018
66 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
68 #define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */
70 #define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */
72 #define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */
73 #define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */
74 #define BHND_CCS_AVAIL_MASK 0x00030000
76 #define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */
77 #define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */
78 #define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */
81 #define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */
82 #define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */
85 (((_value) & _flag) != 0)