| e7ef4617 | 14-Apr-2026 |
James Clark <james.clark@linaro.org> |
perf arm_spe: Print remaining IMPDEF event numbers
Any IMPDEF events not printed out from a known core's IMPDEF list or for a completely unknown core will still not be shown to the user. Fix this by
perf arm_spe: Print remaining IMPDEF event numbers
Any IMPDEF events not printed out from a known core's IMPDEF list or for a completely unknown core will still not be shown to the user. Fix this by printing the remaining bits as comma separated raw numbers, e.g. "IMPDEF:1,2,3,4".
Suggested-by: Al Grant <al.grant@arm.com> Reviewed-by: Leo Yan <leo.yan@arm.com> Signed-off-by: James Clark <james.clark@linaro.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linux.dev> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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| b566a740 | 14-Apr-2026 |
James Clark <james.clark@linaro.org> |
perf arm_spe: Decode Arm N1 IMPDEF events
>From the TRM [1], N1 has one IMPDEF event which isn't covered by the common list. Add a framework so that more cores can be added in the future and that th
perf arm_spe: Decode Arm N1 IMPDEF events
>From the TRM [1], N1 has one IMPDEF event which isn't covered by the common list. Add a framework so that more cores can be added in the future and that the N1 IMPDEF event can be decoded. Also increase the size of the buffer because we're adding more strings and if it gets truncated it falls back to a hex dump only.
[1]: https://developer.arm.com/documentation/100616/0401/Statistical-Profiling-Extension/implementation-defined-features-of-SPE
Suggested-by: Al Grant <al.grant@arm.com> Reviewed-by: Leo Yan <leo.yan@arm.com> Signed-off-by: James Clark <james.clark@linaro.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linux.dev> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://developer.arm.com/documentation/100616/0401/Statistical-Profiling-Extension/implementation-defined-features-of-SPE Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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| 96b4910c | 14-Apr-2026 |
James Clark <james.clark@linaro.org> |
perf arm_spe: Turn event name mappings into an array
This is so we can have a single function that prints events and can be used with multiple mappings from different CPUs. Remove any bit that was p
perf arm_spe: Turn event name mappings into an array
This is so we can have a single function that prints events and can be used with multiple mappings from different CPUs. Remove any bit that was printed so that later we can print out the remaining unknown impdef bits.
No functional changes intended.
Reviewed-by: Leo Yan <leo.yan@arm.com> Signed-off-by: James Clark <james.clark@linaro.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linux.dev> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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| b70aa410 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Expose SIMD information in other operations
The other operations contain SME data processing, ASE (Advanced SIMD) and floating-point operations. Expose these info in the records.
Sign
perf arm_spe: Expose SIMD information in other operations
The other operations contain SME data processing, ASE (Advanced SIMD) and floating-point operations. Expose these info in the records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| d67835cd | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report GCS in record
Report GCS related info in records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@li
perf arm_spe: Report GCS in record
Report GCS related info in records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| d4b61de4 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report memset and memcpy in records
Expose memset and memcpy related info in records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by
perf arm_spe: Report memset and memcpy in records
Expose memset and memcpy related info in records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| 6d47c32c | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report associated info for SVE / SME operations
SVE / SME operations can be predicated or Gather load / scatter store, save the relevant info into record.
Signed-off-by: Leo Yan <leo.
perf arm_spe: Report associated info for SVE / SME operations
SVE / SME operations can be predicated or Gather load / scatter store, save the relevant info into record.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| f3b9bed7 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report extended memory operations in records
Extended memory operations include atomic (AT), acquire/release (AR), and exclusive (EXCL) operations. Save the relevant information in the
perf arm_spe: Report extended memory operations in records
Extended memory operations include atomic (AT), acquire/release (AR), and exclusive (EXCL) operations. Save the relevant information in the records.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| c462dc70 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report MTE allocation tag in record
Save MTE tag info in memory record.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark
perf arm_spe: Report MTE allocation tag in record
Save MTE tag info in memory record.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| 77e4291e | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Report register access in record
Record register access info for load / store operations.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewe
perf arm_spe: Report register access in record
Record register access info for load / store operations.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| cdc1aff1 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Introduce data processing macro for SVE operations
Introduce the ARM_SPE_OP_DP (data processing) macro as associated information for SVE operations. For SVE register access, only ARM_S
perf arm_spe: Introduce data processing macro for SVE operations
Introduce the ARM_SPE_OP_DP (data processing) macro as associated information for SVE operations. For SVE register access, only ARM_SPE_OP_SVE is set; for SVE data processing, both ARM_SPE_OP_SVE and ARM_SPE_OP_DP are set together.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| b64bf913 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Consolidate operation types
Consolidate operation types in a way:
(a) Extract the second-level types into separate enums. (b) The second-level types for memory and SIMD operations are
perf arm_spe: Consolidate operation types
Consolidate operation types in a way:
(a) Extract the second-level types into separate enums. (b) The second-level types for memory and SIMD operations are classified by modules. E.g., an operation may relate to general register, SIMD/FP, SVE, etc. (c) The associated information tells details. E.g., an operation is load or store, whether it is atomic operation, etc.
Start the enum items for the second-level types from 8 to accommodate more entries within a 32-bit integer.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| c7c198b3 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Remove unused operation types
Remove unused SVE operation types. These operations will be reintroduced in subsequent refactoring, but with a different format.
Signed-off-by: Leo Yan <
perf arm_spe: Remove unused operation types
Remove unused SVE operation types. These operations will be reintroduced in subsequent refactoring, but with a different format.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| c4cfe1bc | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Decode SME data processing packet
For SME data processing, decode its Effective vector length or Tile Size (ETS), and print out if a floating-point operation.
After:
. 00000000:
perf arm_spe: Decode SME data processing packet
For SME data processing, decode its Effective vector length or Tile Size (ETS), and print out if a floating-point operation.
After:
. 00000000: 49 00 SME-OTHER ETS 1024 FP . 00000002: b2 18 3c d7 83 00 80 ff ff VA 0xffff800083d73c18 . 0000000b: 9a 00 00 LAT 0 XLAT . 0000000e: 43 00 DATA-SOURCE 0
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| 876294a6 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Decode ASE and FP fields in other operation
Add a check for other operation, which prevents any incorrectly classifying. Parse the ASE and FP fields.
After:
. 0000002f: 48 06
perf arm_spe: Decode ASE and FP fields in other operation
Add a check for other operation, which prevents any incorrectly classifying. Parse the ASE and FP fields.
After:
. 0000002f: 48 06 OTHER ASE FP INSN-OTHER . 00000031: b2 08 80 48 01 08 00 ff ff VA 0xffff000801488008 . 0000003a: 9a 00 00 LAT 0 XLAT . 0000003d: 42 16 EV RETIRED L1D-ACCESS TLB-ACCESS
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| c8bf2a05 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Rename SPE_OP_PKT_IS_OTHER_SVE_OP macro
Rename the macro to SPE_OP_PKT_OTHER_SUBCLASS_SVE to unify naming.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@go
perf arm_spe: Rename SPE_OP_PKT_IS_OTHER_SVE_OP macro
Rename the macro to SPE_OP_PKT_OTHER_SUBCLASS_SVE to unify naming.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| b4eaece3 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Decode GCS operation
Decode a load or store from a GCS operation and the associated "common" field.
After:
. 00000000: 49 44 LD GCS COMM
perf arm_spe: Decode GCS operation
Decode a load or store from a GCS operation and the associated "common" field.
After:
. 00000000: 49 44 LD GCS COMM . 00000002: b2 18 3c d7 83 00 80 ff ff VA 0xffff800083d73c18 . 0000000b: 9a 00 00 LAT 0 XLAT . 0000000e: 43 00 DATA-SOURCE 0
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| b61ca721 | 12-Nov-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Unify operation naming
Rename extended subclass and SVE/SME register access subclass, so that the naming can be consistent cross all sub classes.
Add an log "SVE-SME-REG" for the SVE/
perf arm_spe: Unify operation naming
Rename extended subclass and SVE/SME register access subclass, so that the naming can be consistent cross all sub classes.
Add an log "SVE-SME-REG" for the SVE/SME register access, this is easier for parsing.
Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Ian Rogers <irogers@google.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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| d5105689 | 12-Sep-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Set HITM flag
Since FEAT_SPEv1p4, Arm SPE provides two extra events: "Cache data modified" and "Data snooped".
Set the snoop mode as:
- If both the "Cache data modified" event and th
perf arm_spe: Set HITM flag
Since FEAT_SPEv1p4, Arm SPE provides two extra events: "Cache data modified" and "Data snooped".
Set the snoop mode as:
- If both the "Cache data modified" event and the "Data snooped" event are set, which indicates a load operation that snooped from a outside cache and hit a modified copy, set the HITM flag to inspect false sharing.
- If the snooped event bit is not set, and the snooped event has been supported by the hardware, set as NONE mode (no snoop operation).
- If the snooped event bit is not set, and the event is not supported or absent the events info in the meta data, set as NA mode (not available).
Don't set any mode for only "Cache data modified" event, as it hits a local modified copy.
Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Leo Yan <leo.yan@arm.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: German Gomez <german.gomez@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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| 786e7e7a | 12-Sep-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Fill memory levels for FEAT_SPEv1p4
Starting with FEAT_SPEv1p4, Arm SPE provides information on Level 2 data cache and recently fetched events. This patch fills in the memory levels fo
perf arm_spe: Fill memory levels for FEAT_SPEv1p4
Starting with FEAT_SPEv1p4, Arm SPE provides information on Level 2 data cache and recently fetched events. This patch fills in the memory levels for these new events.
The recently fetched events are matched to line-fill buffer (LFB). In general, the latency for accessing LFB is higher than accessing L1 cache but lower than accessing L2 cache. Thus, it locates in the memory hierarchy information between L1 cache and L2 cache.
Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Leo Yan <leo.yan@arm.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: German Gomez <german.gomez@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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| e44e2b2b | 12-Sep-2025 |
Leo Yan <leo.yan@arm.com> |
perf arm_spe: Decode event types for new features
Decode new event types introduced by FEAT_SPEv1p4, FEAT_SPE_SME and FEAT_SPE_SME.
The printed event names don't strictly follow the naming in the A
perf arm_spe: Decode event types for new features
Decode new event types introduced by FEAT_SPEv1p4, FEAT_SPE_SME and FEAT_SPE_SME.
The printed event names don't strictly follow the naming in the Arm ARM. For example, the "Cache data modified" event is shown as "HITM", and the "Data snooped" event is printed as "SNOOPED". Shorter names are easier to read while preserving core meanings.
Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Leo Yan <leo.yan@arm.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: German Gomez <german.gomez@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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