| 75fb63ae | 16-Jan-2026 |
Shawn Lin <shawn.lin@rock-chips.com> |
soc: rockchip: grf: Support multiple grf to be handled
Currently, only the first matched node will be handled. This leads
to jtag switching broken for RK3576, as rk3576-sys-grf is found before
rk357
soc: rockchip: grf: Support multiple grf to be handled
Currently, only the first matched node will be handled. This leads
to jtag switching broken for RK3576, as rk3576-sys-grf is found before
rk3576-ioc-grf. Change the code to scan all the possible node to fix
the problem.
Fixes: e1aaecacfa13 ("soc: rockchip: grf: Add rk3576 default GRF values")
Cc: stable@vger.kernel.org
Cc: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
Link: https://patch.msgid.link/1768524932-163929-3-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| 048213a3 | 21-Oct-2025 |
Heiko Stuebner <heiko.stuebner@cherry.de> |
soc: rockchip: grf: Add select correct PWM implementation on RK3368
Similar to the RK3288, the RK3368 has two different implementations of
the PWM block inside the SoC - the newer ones that we have
soc: rockchip: grf: Add select correct PWM implementation on RK3368
Similar to the RK3288, the RK3368 has two different implementations of
the PWM block inside the SoC - the newer ones that we have a driver for
and that is used on every SoC and a previous variant that was likely
left as a fallback if the new one creates problems.
The devicetree is already set up for the new variant, so make sure
we actually use it - similar to the RK3288.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://patch.msgid.link/20251021074254.87065-4-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| e1aaecac | 22-Aug-2024 |
Detlev Casanova <detlev.casanova@collabora.com> |
soc: rockchip: grf: Add rk3576 default GRF values
Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO.
The i3c weak pull up is activated to let all gpio banks be controlled
by
soc: rockchip: grf: Add rk3576 default GRF values
Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO.
The i3c weak pull up is activated to let all gpio banks be controlled
by the pinctrl driver.
Disabling the JTAG function lets the SDMMC core use its full IO width.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20240822195706.920567-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| 7bd76f40 | 23-May-2024 |
Alex Bee <knaerzche@gmail.com> |
soc: rockchip: grf: Set RK3128's vpu main clock
RK3128 has a setting in GRF which selects whether the vpu attached iommu
uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The
default i
soc: rockchip: grf: Set RK3128's vpu main clock
RK3128 has a setting in GRF which selects whether the vpu attached iommu
uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The
default is vepu but some part of the vendor firmware sets it to vdpu.
In order to be independent on whether any of those vendor firmware blobs is
used to boot the SoC reset "vpu main clock" setting to it's default value.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240523185633.71355-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| a10b3841 | 01-May-2023 |
Randy Dunlap <rdunlap@infradead.org> |
soc: rockchip: dtpm: use C99 array init syntax
Eliminate sparse warnings in soc/rockchip/dtpm.c:
drivers/soc/rockchip/dtpm.c:15:12: sparse: warning: obsolete array initializer, use C99 syntax
drive
soc: rockchip: dtpm: use C99 array init syntax
Eliminate sparse warnings in soc/rockchip/dtpm.c:
drivers/soc/rockchip/dtpm.c:15:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:17:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:20:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:23:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:26:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:29:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:32:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:35:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:38:12: sparse: warning: obsolete array initializer, use C99 syntax
drivers/soc/rockchip/dtpm.c:41:12: sparse: warning: obsolete array initializer, use C99 syntax
Fixes: b9d6c47a2be8 ("rockchip/soc/drivers: Add DTPM description for rk3399")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230501024950.31518-1-rdunlap@infradead.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| 6541b424 | 06-Sep-2022 |
Finley Xiao <finley.xiao@rock-chips.com> |
soc: rockchip: power-domain: add power domain support for rk3588
This driver is modified to support RK3588 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
[port of downstream code inc
soc: rockchip: power-domain: add power domain support for rk3588
This driver is modified to support RK3588 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
[port of downstream code incl. merging in fixes]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220906143825.199089-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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| 570ed4e5 | 18-Aug-2022 |
Jianqun Xu <jay.xu@rock-chips.com> |
soc: rockchip: io-domain: Add RV1126 IO domains
Add IO domains support for RV1126 SoC.
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@
soc: rockchip: io-domain: Add RV1126 IO domains
Add IO domains support for RV1126 SoC.
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220818124132.125304-6-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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