1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. 4 * Author: Lin Huang <hl@rock-chips.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/devfreq.h> 12 #include <linux/devfreq-event.h> 13 #include <linux/interrupt.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_opp.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/rwsem.h> 22 #include <linux/suspend.h> 23 24 #include <soc/rockchip/rk3399_grf.h> 25 #include <soc/rockchip/rockchip_sip.h> 26 27 #define NS_TO_CYCLE(NS, MHz) (((NS) * (MHz)) / NSEC_PER_USEC) 28 29 #define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0) 30 #define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8) 31 #define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16) 32 33 #define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0) 34 #define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16) 35 36 #define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0) 37 38 struct rk3399_dmcfreq { 39 struct device *dev; 40 struct devfreq *devfreq; 41 struct devfreq_dev_profile profile; 42 struct devfreq_simple_ondemand_data ondemand_data; 43 struct clk *dmc_clk; 44 struct devfreq_event_dev *edev; 45 struct mutex lock; 46 struct regulator *vdd_center; 47 struct regmap *regmap_pmu; 48 unsigned long rate, target_rate; 49 unsigned long volt, target_volt; 50 unsigned int odt_dis_freq; 51 52 unsigned int pd_idle_ns; 53 unsigned int sr_idle_ns; 54 unsigned int sr_mc_gate_idle_ns; 55 unsigned int srpd_lite_idle_ns; 56 unsigned int standby_idle_ns; 57 unsigned int ddr3_odt_dis_freq; 58 unsigned int lpddr3_odt_dis_freq; 59 unsigned int lpddr4_odt_dis_freq; 60 61 unsigned int pd_idle_dis_freq; 62 unsigned int sr_idle_dis_freq; 63 unsigned int sr_mc_gate_idle_dis_freq; 64 unsigned int srpd_lite_idle_dis_freq; 65 unsigned int standby_idle_dis_freq; 66 }; 67 68 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, 69 u32 flags) 70 { 71 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 72 struct dev_pm_opp *opp; 73 unsigned long old_clk_rate = dmcfreq->rate; 74 unsigned long target_volt, target_rate; 75 unsigned int ddrcon_mhz; 76 struct arm_smccc_res res; 77 int err; 78 79 u32 odt_pd_arg0 = 0; 80 u32 odt_pd_arg1 = 0; 81 u32 odt_pd_arg2 = 0; 82 83 opp = devfreq_recommended_opp(dev, freq, flags); 84 if (IS_ERR(opp)) 85 return PTR_ERR(opp); 86 87 target_rate = dev_pm_opp_get_freq(opp); 88 target_volt = dev_pm_opp_get_voltage(opp); 89 dev_pm_opp_put(opp); 90 91 if (dmcfreq->rate == target_rate) 92 return 0; 93 94 mutex_lock(&dmcfreq->lock); 95 96 /* 97 * Some idle parameters may be based on the DDR controller clock, which 98 * is half of the DDR frequency. 99 * pd_idle and standby_idle are based on the controller clock cycle. 100 * sr_idle_cycle, sr_mc_gate_idle_cycle, and srpd_lite_idle_cycle 101 * are based on the 1024 controller clock cycle 102 */ 103 ddrcon_mhz = target_rate / USEC_PER_SEC / 2; 104 105 u32p_replace_bits(&odt_pd_arg1, 106 NS_TO_CYCLE(dmcfreq->pd_idle_ns, ddrcon_mhz), 107 RK3399_SET_ODT_PD_1_PD_IDLE); 108 u32p_replace_bits(&odt_pd_arg0, 109 NS_TO_CYCLE(dmcfreq->standby_idle_ns, ddrcon_mhz), 110 RK3399_SET_ODT_PD_0_STANDBY_IDLE); 111 u32p_replace_bits(&odt_pd_arg0, 112 DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_idle_ns, 113 ddrcon_mhz), 1024), 114 RK3399_SET_ODT_PD_0_SR_IDLE); 115 u32p_replace_bits(&odt_pd_arg0, 116 DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->sr_mc_gate_idle_ns, 117 ddrcon_mhz), 1024), 118 RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE); 119 u32p_replace_bits(&odt_pd_arg1, 120 DIV_ROUND_UP(NS_TO_CYCLE(dmcfreq->srpd_lite_idle_ns, 121 ddrcon_mhz), 1024), 122 RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE); 123 124 if (dmcfreq->regmap_pmu) { 125 if (target_rate >= dmcfreq->sr_idle_dis_freq) 126 odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_IDLE; 127 128 if (target_rate >= dmcfreq->sr_mc_gate_idle_dis_freq) 129 odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE; 130 131 if (target_rate >= dmcfreq->standby_idle_dis_freq) 132 odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_STANDBY_IDLE; 133 134 if (target_rate >= dmcfreq->pd_idle_dis_freq) 135 odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_PD_IDLE; 136 137 if (target_rate >= dmcfreq->srpd_lite_idle_dis_freq) 138 odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE; 139 140 if (target_rate >= dmcfreq->odt_dis_freq) 141 odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE; 142 143 /* 144 * This makes a SMC call to the TF-A to set the DDR PD 145 * (power-down) timings and to enable or disable the 146 * ODT (on-die termination) resistors. 147 */ 148 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1, 149 ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2, 150 0, 0, 0, &res); 151 } 152 153 /* 154 * If frequency scaling from low to high, adjust voltage first. 155 * If frequency scaling from high to low, adjust frequency first. 156 */ 157 if (old_clk_rate < target_rate) { 158 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 159 target_volt); 160 if (err) { 161 dev_err(dev, "Cannot set voltage %lu uV\n", 162 target_volt); 163 goto out; 164 } 165 } 166 167 err = clk_set_rate(dmcfreq->dmc_clk, target_rate); 168 if (err) { 169 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate, 170 err); 171 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 172 dmcfreq->volt); 173 goto out; 174 } 175 176 /* 177 * Check the dpll rate, 178 * There only two result we will get, 179 * 1. Ddr frequency scaling fail, we still get the old rate. 180 * 2. Ddr frequency scaling sucessful, we get the rate we set. 181 */ 182 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); 183 184 /* If get the incorrect rate, set voltage to old value. */ 185 if (dmcfreq->rate != target_rate) { 186 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n", 187 target_rate, dmcfreq->rate); 188 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 189 dmcfreq->volt); 190 goto out; 191 } else if (old_clk_rate > target_rate) 192 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 193 target_volt); 194 if (err) 195 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt); 196 197 dmcfreq->rate = target_rate; 198 dmcfreq->volt = target_volt; 199 200 out: 201 mutex_unlock(&dmcfreq->lock); 202 return err; 203 } 204 205 static int rk3399_dmcfreq_get_dev_status(struct device *dev, 206 struct devfreq_dev_status *stat) 207 { 208 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 209 struct devfreq_event_data edata; 210 int ret = 0; 211 212 ret = devfreq_event_get_event(dmcfreq->edev, &edata); 213 if (ret < 0) 214 return ret; 215 216 stat->current_frequency = dmcfreq->rate; 217 stat->busy_time = edata.load_count; 218 stat->total_time = edata.total_count; 219 220 return ret; 221 } 222 223 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) 224 { 225 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 226 227 *freq = dmcfreq->rate; 228 229 return 0; 230 } 231 232 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) 233 { 234 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 235 int ret = 0; 236 237 ret = devfreq_event_disable_edev(dmcfreq->edev); 238 if (ret < 0) { 239 dev_err(dev, "failed to disable the devfreq-event devices\n"); 240 return ret; 241 } 242 243 ret = devfreq_suspend_device(dmcfreq->devfreq); 244 if (ret < 0) { 245 dev_err(dev, "failed to suspend the devfreq devices\n"); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) 253 { 254 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 255 int ret = 0; 256 257 ret = devfreq_event_enable_edev(dmcfreq->edev); 258 if (ret < 0) { 259 dev_err(dev, "failed to enable the devfreq-event devices\n"); 260 return ret; 261 } 262 263 ret = devfreq_resume_device(dmcfreq->devfreq); 264 if (ret < 0) { 265 dev_err(dev, "failed to resume the devfreq devices\n"); 266 return ret; 267 } 268 return ret; 269 } 270 271 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, 272 rk3399_dmcfreq_resume); 273 274 static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data, 275 struct device_node *np) 276 { 277 int ret = 0; 278 279 /* 280 * These are all optional, and serve as minimum bounds. Give them large 281 * (i.e., never "disabled") values if the DT doesn't specify one. 282 */ 283 data->pd_idle_dis_freq = 284 data->sr_idle_dis_freq = 285 data->sr_mc_gate_idle_dis_freq = 286 data->srpd_lite_idle_dis_freq = 287 data->standby_idle_dis_freq = UINT_MAX; 288 289 ret |= of_property_read_u32(np, "rockchip,pd-idle-ns", 290 &data->pd_idle_ns); 291 ret |= of_property_read_u32(np, "rockchip,sr-idle-ns", 292 &data->sr_idle_ns); 293 ret |= of_property_read_u32(np, "rockchip,sr-mc-gate-idle-ns", 294 &data->sr_mc_gate_idle_ns); 295 ret |= of_property_read_u32(np, "rockchip,srpd-lite-idle-ns", 296 &data->srpd_lite_idle_ns); 297 ret |= of_property_read_u32(np, "rockchip,standby-idle-ns", 298 &data->standby_idle_ns); 299 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", 300 &data->ddr3_odt_dis_freq); 301 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", 302 &data->lpddr3_odt_dis_freq); 303 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", 304 &data->lpddr4_odt_dis_freq); 305 306 ret |= of_property_read_u32(np, "rockchip,pd-idle-dis-freq-hz", 307 &data->pd_idle_dis_freq); 308 ret |= of_property_read_u32(np, "rockchip,sr-idle-dis-freq-hz", 309 &data->sr_idle_dis_freq); 310 ret |= of_property_read_u32(np, "rockchip,sr-mc-gate-idle-dis-freq-hz", 311 &data->sr_mc_gate_idle_dis_freq); 312 ret |= of_property_read_u32(np, "rockchip,srpd-lite-idle-dis-freq-hz", 313 &data->srpd_lite_idle_dis_freq); 314 ret |= of_property_read_u32(np, "rockchip,standby-idle-dis-freq-hz", 315 &data->standby_idle_dis_freq); 316 317 return ret; 318 } 319 320 static int rk3399_dmcfreq_probe(struct platform_device *pdev) 321 { 322 struct arm_smccc_res res; 323 struct device *dev = &pdev->dev; 324 struct device_node *np = pdev->dev.of_node, *node; 325 struct rk3399_dmcfreq *data; 326 int ret; 327 struct dev_pm_opp *opp; 328 u32 ddr_type; 329 u32 val; 330 331 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); 332 if (!data) 333 return -ENOMEM; 334 335 mutex_init(&data->lock); 336 337 data->vdd_center = devm_regulator_get(dev, "center"); 338 if (IS_ERR(data->vdd_center)) 339 return dev_err_probe(dev, PTR_ERR(data->vdd_center), 340 "Cannot get the regulator \"center\"\n"); 341 342 data->dmc_clk = devm_clk_get(dev, "dmc_clk"); 343 if (IS_ERR(data->dmc_clk)) 344 return dev_err_probe(dev, PTR_ERR(data->dmc_clk), 345 "Cannot get the clk dmc_clk\n"); 346 347 data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0); 348 if (IS_ERR(data->edev)) 349 return -EPROBE_DEFER; 350 351 ret = devfreq_event_enable_edev(data->edev); 352 if (ret < 0) { 353 dev_err(dev, "failed to enable devfreq-event devices\n"); 354 return ret; 355 } 356 357 rk3399_dmcfreq_of_props(data, np); 358 359 node = of_parse_phandle(np, "rockchip,pmu", 0); 360 if (!node) 361 goto no_pmu; 362 363 data->regmap_pmu = syscon_node_to_regmap(node); 364 of_node_put(node); 365 if (IS_ERR(data->regmap_pmu)) { 366 ret = PTR_ERR(data->regmap_pmu); 367 goto err_edev; 368 } 369 370 regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); 371 ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & 372 RK3399_PMUGRF_DDRTYPE_MASK; 373 374 switch (ddr_type) { 375 case RK3399_PMUGRF_DDRTYPE_DDR3: 376 data->odt_dis_freq = data->ddr3_odt_dis_freq; 377 break; 378 case RK3399_PMUGRF_DDRTYPE_LPDDR3: 379 data->odt_dis_freq = data->lpddr3_odt_dis_freq; 380 break; 381 case RK3399_PMUGRF_DDRTYPE_LPDDR4: 382 data->odt_dis_freq = data->lpddr4_odt_dis_freq; 383 break; 384 default: 385 ret = -EINVAL; 386 goto err_edev; 387 } 388 389 no_pmu: 390 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, 391 ROCKCHIP_SIP_CONFIG_DRAM_INIT, 392 0, 0, 0, 0, &res); 393 394 /* 395 * We add a devfreq driver to our parent since it has a device tree node 396 * with operating points. 397 */ 398 if (devm_pm_opp_of_add_table(dev)) { 399 dev_err(dev, "Invalid operating-points in device tree.\n"); 400 ret = -EINVAL; 401 goto err_edev; 402 } 403 404 data->ondemand_data.upthreshold = 25; 405 data->ondemand_data.downdifferential = 15; 406 407 data->rate = clk_get_rate(data->dmc_clk); 408 409 opp = devfreq_recommended_opp(dev, &data->rate, 0); 410 if (IS_ERR(opp)) { 411 ret = PTR_ERR(opp); 412 goto err_edev; 413 } 414 415 data->rate = dev_pm_opp_get_freq(opp); 416 data->volt = dev_pm_opp_get_voltage(opp); 417 dev_pm_opp_put(opp); 418 419 data->profile = (struct devfreq_dev_profile) { 420 .polling_ms = 200, 421 .target = rk3399_dmcfreq_target, 422 .get_dev_status = rk3399_dmcfreq_get_dev_status, 423 .get_cur_freq = rk3399_dmcfreq_get_cur_freq, 424 .initial_freq = data->rate, 425 }; 426 427 data->devfreq = devm_devfreq_add_device(dev, 428 &data->profile, 429 DEVFREQ_GOV_SIMPLE_ONDEMAND, 430 &data->ondemand_data); 431 if (IS_ERR(data->devfreq)) { 432 ret = PTR_ERR(data->devfreq); 433 goto err_edev; 434 } 435 436 devm_devfreq_register_opp_notifier(dev, data->devfreq); 437 438 data->dev = dev; 439 platform_set_drvdata(pdev, data); 440 441 return 0; 442 443 err_edev: 444 devfreq_event_disable_edev(data->edev); 445 446 return ret; 447 } 448 449 static int rk3399_dmcfreq_remove(struct platform_device *pdev) 450 { 451 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); 452 453 devfreq_event_disable_edev(dmcfreq->edev); 454 455 return 0; 456 } 457 458 static const struct of_device_id rk3399dmc_devfreq_of_match[] = { 459 { .compatible = "rockchip,rk3399-dmc" }, 460 { }, 461 }; 462 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match); 463 464 static struct platform_driver rk3399_dmcfreq_driver = { 465 .probe = rk3399_dmcfreq_probe, 466 .remove = rk3399_dmcfreq_remove, 467 .driver = { 468 .name = "rk3399-dmc-freq", 469 .pm = &rk3399_dmcfreq_pm, 470 .of_match_table = rk3399dmc_devfreq_of_match, 471 }, 472 }; 473 module_platform_driver(rk3399_dmcfreq_driver); 474 475 MODULE_LICENSE("GPL v2"); 476 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>"); 477 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); 478