1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Generic Register Files setup 4 * 5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 14 #define HIWORD_UPDATE(val, mask, shift) \ 15 ((val) << (shift) | (mask) << ((shift) + 16)) 16 17 struct rockchip_grf_value { 18 const char *desc; 19 u32 reg; 20 u32 val; 21 }; 22 23 struct rockchip_grf_info { 24 const struct rockchip_grf_value *values; 25 int num_values; 26 }; 27 28 #define RK3036_GRF_SOC_CON0 0x140 29 30 static const struct rockchip_grf_value rk3036_defaults[] __initconst = { 31 /* 32 * Disable auto jtag/sdmmc switching that causes issues with the 33 * clock-framework and the mmc controllers making them unreliable. 34 */ 35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) }, 36 }; 37 38 static const struct rockchip_grf_info rk3036_grf __initconst = { 39 .values = rk3036_defaults, 40 .num_values = ARRAY_SIZE(rk3036_defaults), 41 }; 42 43 #define RK3128_GRF_SOC_CON0 0x140 44 #define RK3128_GRF_SOC_CON1 0x144 45 46 static const struct rockchip_grf_value rk3128_defaults[] __initconst = { 47 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) }, 48 { "vpu main clock", RK3128_GRF_SOC_CON1, HIWORD_UPDATE(0, 1, 10) }, 49 }; 50 51 static const struct rockchip_grf_info rk3128_grf __initconst = { 52 .values = rk3128_defaults, 53 .num_values = ARRAY_SIZE(rk3128_defaults), 54 }; 55 56 #define RK3228_GRF_SOC_CON6 0x418 57 58 static const struct rockchip_grf_value rk3228_defaults[] __initconst = { 59 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) }, 60 }; 61 62 static const struct rockchip_grf_info rk3228_grf __initconst = { 63 .values = rk3228_defaults, 64 .num_values = ARRAY_SIZE(rk3228_defaults), 65 }; 66 67 #define RK3288_GRF_SOC_CON0 0x244 68 #define RK3288_GRF_SOC_CON2 0x24c 69 70 static const struct rockchip_grf_value rk3288_defaults[] __initconst = { 71 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) }, 72 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) }, 73 }; 74 75 static const struct rockchip_grf_info rk3288_grf __initconst = { 76 .values = rk3288_defaults, 77 .num_values = ARRAY_SIZE(rk3288_defaults), 78 }; 79 80 #define RK3328_GRF_SOC_CON4 0x410 81 82 static const struct rockchip_grf_value rk3328_defaults[] __initconst = { 83 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) }, 84 }; 85 86 static const struct rockchip_grf_info rk3328_grf __initconst = { 87 .values = rk3328_defaults, 88 .num_values = ARRAY_SIZE(rk3328_defaults), 89 }; 90 91 #define RK3368_GRF_SOC_CON15 0x43c 92 93 static const struct rockchip_grf_value rk3368_defaults[] __initconst = { 94 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) }, 95 }; 96 97 static const struct rockchip_grf_info rk3368_grf __initconst = { 98 .values = rk3368_defaults, 99 .num_values = ARRAY_SIZE(rk3368_defaults), 100 }; 101 102 #define RK3399_GRF_SOC_CON7 0xe21c 103 104 static const struct rockchip_grf_value rk3399_defaults[] __initconst = { 105 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) }, 106 }; 107 108 static const struct rockchip_grf_info rk3399_grf __initconst = { 109 .values = rk3399_defaults, 110 .num_values = ARRAY_SIZE(rk3399_defaults), 111 }; 112 113 #define RK3566_GRF_USB3OTG0_CON1 0x0104 114 115 static const struct rockchip_grf_value rk3566_defaults[] __initconst = { 116 { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) }, 117 { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) }, 118 { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) }, 119 }; 120 121 static const struct rockchip_grf_info rk3566_pipegrf __initconst = { 122 .values = rk3566_defaults, 123 .num_values = ARRAY_SIZE(rk3566_defaults), 124 }; 125 126 #define RK3588_GRF_SOC_CON6 0x0318 127 128 static const struct rockchip_grf_value rk3588_defaults[] __initconst = { 129 { "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) }, 130 }; 131 132 static const struct rockchip_grf_info rk3588_sysgrf __initconst = { 133 .values = rk3588_defaults, 134 .num_values = ARRAY_SIZE(rk3588_defaults), 135 }; 136 137 138 static const struct of_device_id rockchip_grf_dt_match[] __initconst = { 139 { 140 .compatible = "rockchip,rk3036-grf", 141 .data = (void *)&rk3036_grf, 142 }, { 143 .compatible = "rockchip,rk3128-grf", 144 .data = (void *)&rk3128_grf, 145 }, { 146 .compatible = "rockchip,rk3228-grf", 147 .data = (void *)&rk3228_grf, 148 }, { 149 .compatible = "rockchip,rk3288-grf", 150 .data = (void *)&rk3288_grf, 151 }, { 152 .compatible = "rockchip,rk3328-grf", 153 .data = (void *)&rk3328_grf, 154 }, { 155 .compatible = "rockchip,rk3368-grf", 156 .data = (void *)&rk3368_grf, 157 }, { 158 .compatible = "rockchip,rk3399-grf", 159 .data = (void *)&rk3399_grf, 160 }, { 161 .compatible = "rockchip,rk3566-pipe-grf", 162 .data = (void *)&rk3566_pipegrf, 163 }, { 164 .compatible = "rockchip,rk3588-sys-grf", 165 .data = (void *)&rk3588_sysgrf, 166 }, 167 { /* sentinel */ }, 168 }; 169 170 static int __init rockchip_grf_init(void) 171 { 172 const struct rockchip_grf_info *grf_info; 173 const struct of_device_id *match; 174 struct device_node *np; 175 struct regmap *grf; 176 int ret, i; 177 178 np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match, 179 &match); 180 if (!np) 181 return -ENODEV; 182 if (!match || !match->data) { 183 pr_err("%s: missing grf data\n", __func__); 184 of_node_put(np); 185 return -EINVAL; 186 } 187 188 grf_info = match->data; 189 190 grf = syscon_node_to_regmap(np); 191 of_node_put(np); 192 if (IS_ERR(grf)) { 193 pr_err("%s: could not get grf syscon\n", __func__); 194 return PTR_ERR(grf); 195 } 196 197 for (i = 0; i < grf_info->num_values; i++) { 198 const struct rockchip_grf_value *val = &grf_info->values[i]; 199 200 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, 201 val->desc, val->reg, val->val); 202 ret = regmap_write(grf, val->reg, val->val); 203 if (ret < 0) 204 pr_err("%s: write to %#6x failed with %d\n", 205 __func__, val->reg, ret); 206 } 207 208 return 0; 209 } 210 postcore_initcall(rockchip_grf_init); 211