1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_FOOTBRIDGE 351 bool "FootBridge" 352 depends on CPU_LITTLE_ENDIAN 353 select CPU_SA110 354 select FOOTBRIDGE 355 select NEED_MACH_MEMORY_H 356 help 357 Support for systems based on the DC21285 companion chip 358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 359 360config ARCH_PXA 361 bool "PXA2xx/PXA3xx-based" 362 depends on CPU_LITTLE_ENDIAN 363 select ARCH_MTD_XIP 364 select ARM_CPU_SUSPEND if PM 365 select AUTO_ZRELADDR 366 select COMMON_CLK 367 select CLKSRC_PXA 368 select CLKSRC_MMIO 369 select TIMER_OF 370 select CPU_XSCALE if !CPU_XSC3 371 select GPIO_PXA 372 select GPIOLIB 373 select IRQ_DOMAIN 374 select PLAT_PXA 375 select SPARSE_IRQ 376 help 377 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 378 379config ARCH_RPC 380 bool "RiscPC" 381 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 382 depends on CPU_LITTLE_ENDIAN 383 select ARCH_ACORN 384 select ARCH_MAY_HAVE_PC_FDC 385 select ARCH_SPARSEMEM_ENABLE 386 select ARM_HAS_SG_CHAIN 387 select CPU_SA110 388 select FIQ 389 select HAVE_PATA_PLATFORM 390 select ISA_DMA_API 391 select LEGACY_TIMER_TICK 392 select NEED_MACH_IO_H 393 select NEED_MACH_MEMORY_H 394 select NO_IOPORT_MAP 395 help 396 On the Acorn Risc-PC, Linux can support the internal IDE disk and 397 CD-ROM interface, serial and parallel port, and the floppy drive. 398 399config ARCH_SA1100 400 bool "SA1100-based" 401 depends on CPU_LITTLE_ENDIAN 402 select ARCH_MTD_XIP 403 select ARCH_SPARSEMEM_ENABLE 404 select CLKSRC_MMIO 405 select CLKSRC_PXA 406 select TIMER_OF if OF 407 select COMMON_CLK 408 select CPU_FREQ 409 select CPU_SA1100 410 select GPIOLIB 411 select IRQ_DOMAIN 412 select ISA 413 select NEED_MACH_MEMORY_H 414 select SPARSE_IRQ 415 help 416 Support for StrongARM 11x0 based boards. 417 418config ARCH_OMAP1 419 bool "TI OMAP1" 420 depends on CPU_LITTLE_ENDIAN 421 select CLKSRC_MMIO 422 select FORCE_PCI if PCCARD 423 select GENERIC_IRQ_CHIP 424 select GPIOLIB 425 select HAVE_LEGACY_CLK 426 select IRQ_DOMAIN 427 select SPARSE_IRQ 428 help 429 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 430 431endchoice 432 433menu "Multiple platform selection" 434 depends on ARCH_MULTIPLATFORM 435 436comment "CPU Core family selection" 437 438config ARCH_MULTI_V4 439 bool "ARMv4 based platforms (FA526)" 440 depends on !ARCH_MULTI_V6_V7 441 select ARCH_MULTI_V4_V5 442 select CPU_FA526 443 444config ARCH_MULTI_V4T 445 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 446 depends on !ARCH_MULTI_V6_V7 447 select ARCH_MULTI_V4_V5 448 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 449 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 450 CPU_ARM925T || CPU_ARM940T) 451 452config ARCH_MULTI_V5 453 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 454 depends on !ARCH_MULTI_V6_V7 455 select ARCH_MULTI_V4_V5 456 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 457 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 458 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 459 460config ARCH_MULTI_V4_V5 461 bool 462 463config ARCH_MULTI_V6 464 bool "ARMv6 based platforms (ARM11)" 465 select ARCH_MULTI_V6_V7 466 select CPU_V6K 467 468config ARCH_MULTI_V7 469 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 470 default y 471 select ARCH_MULTI_V6_V7 472 select CPU_V7 473 select HAVE_SMP 474 475config ARCH_MULTI_V6_V7 476 bool 477 select MIGHT_HAVE_CACHE_L2X0 478 479config ARCH_MULTI_CPU_AUTO 480 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 481 select ARCH_MULTI_V5 482 483endmenu 484 485config ARCH_VIRT 486 bool "Dummy Virtual Machine" 487 depends on ARCH_MULTI_V7 488 select ARM_AMBA 489 select ARM_GIC 490 select ARM_GIC_V2M if PCI 491 select ARM_GIC_V3 492 select ARM_GIC_V3_ITS if PCI 493 select ARM_PSCI 494 select HAVE_ARM_ARCH_TIMER 495 496config ARCH_AIROHA 497 bool "Airoha SoC Support" 498 depends on ARCH_MULTI_V7 499 select ARM_AMBA 500 select ARM_GIC 501 select ARM_GIC_V3 502 select ARM_PSCI 503 select HAVE_ARM_ARCH_TIMER 504 select COMMON_CLK 505 help 506 Support for Airoha EN7523 SoCs 507 508# 509# This is sorted alphabetically by mach-* pathname. However, plat-* 510# Kconfigs may be included either alphabetically (according to the 511# plat- suffix) or along side the corresponding mach-* source. 512# 513source "arch/arm/mach-actions/Kconfig" 514 515source "arch/arm/mach-alpine/Kconfig" 516 517source "arch/arm/mach-artpec/Kconfig" 518 519source "arch/arm/mach-asm9260/Kconfig" 520 521source "arch/arm/mach-aspeed/Kconfig" 522 523source "arch/arm/mach-at91/Kconfig" 524 525source "arch/arm/mach-axxia/Kconfig" 526 527source "arch/arm/mach-bcm/Kconfig" 528 529source "arch/arm/mach-berlin/Kconfig" 530 531source "arch/arm/mach-clps711x/Kconfig" 532 533source "arch/arm/mach-cns3xxx/Kconfig" 534 535source "arch/arm/mach-davinci/Kconfig" 536 537source "arch/arm/mach-digicolor/Kconfig" 538 539source "arch/arm/mach-dove/Kconfig" 540 541source "arch/arm/mach-ep93xx/Kconfig" 542 543source "arch/arm/mach-exynos/Kconfig" 544 545source "arch/arm/mach-footbridge/Kconfig" 546 547source "arch/arm/mach-gemini/Kconfig" 548 549source "arch/arm/mach-highbank/Kconfig" 550 551source "arch/arm/mach-hisi/Kconfig" 552 553source "arch/arm/mach-hpe/Kconfig" 554 555source "arch/arm/mach-imx/Kconfig" 556 557source "arch/arm/mach-iop32x/Kconfig" 558 559source "arch/arm/mach-ixp4xx/Kconfig" 560 561source "arch/arm/mach-keystone/Kconfig" 562 563source "arch/arm/mach-lpc32xx/Kconfig" 564 565source "arch/arm/mach-mediatek/Kconfig" 566 567source "arch/arm/mach-meson/Kconfig" 568 569source "arch/arm/mach-milbeaut/Kconfig" 570 571source "arch/arm/mach-mmp/Kconfig" 572 573source "arch/arm/mach-moxart/Kconfig" 574 575source "arch/arm/mach-mstar/Kconfig" 576 577source "arch/arm/mach-mv78xx0/Kconfig" 578 579source "arch/arm/mach-mvebu/Kconfig" 580 581source "arch/arm/mach-mxs/Kconfig" 582 583source "arch/arm/mach-nomadik/Kconfig" 584 585source "arch/arm/mach-npcm/Kconfig" 586 587source "arch/arm/mach-nspire/Kconfig" 588 589source "arch/arm/mach-omap1/Kconfig" 590 591source "arch/arm/mach-omap2/Kconfig" 592 593source "arch/arm/mach-orion5x/Kconfig" 594 595source "arch/arm/mach-oxnas/Kconfig" 596 597source "arch/arm/mach-pxa/Kconfig" 598source "arch/arm/plat-pxa/Kconfig" 599 600source "arch/arm/mach-qcom/Kconfig" 601 602source "arch/arm/mach-rda/Kconfig" 603 604source "arch/arm/mach-realtek/Kconfig" 605 606source "arch/arm/mach-rockchip/Kconfig" 607 608source "arch/arm/mach-s3c/Kconfig" 609 610source "arch/arm/mach-s5pv210/Kconfig" 611 612source "arch/arm/mach-sa1100/Kconfig" 613 614source "arch/arm/mach-shmobile/Kconfig" 615 616source "arch/arm/mach-socfpga/Kconfig" 617 618source "arch/arm/mach-spear/Kconfig" 619 620source "arch/arm/mach-sti/Kconfig" 621 622source "arch/arm/mach-stm32/Kconfig" 623 624source "arch/arm/mach-sunxi/Kconfig" 625 626source "arch/arm/mach-tegra/Kconfig" 627 628source "arch/arm/mach-uniphier/Kconfig" 629 630source "arch/arm/mach-ux500/Kconfig" 631 632source "arch/arm/mach-versatile/Kconfig" 633 634source "arch/arm/mach-vt8500/Kconfig" 635 636source "arch/arm/mach-zynq/Kconfig" 637 638# ARMv7-M architecture 639config ARCH_LPC18XX 640 bool "NXP LPC18xx/LPC43xx" 641 depends on ARM_SINGLE_ARMV7M 642 select ARCH_HAS_RESET_CONTROLLER 643 select ARM_AMBA 644 select CLKSRC_LPC32XX 645 select PINCTRL 646 help 647 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 648 high performance microcontrollers. 649 650config ARCH_MPS2 651 bool "ARM MPS2 platform" 652 depends on ARM_SINGLE_ARMV7M 653 select ARM_AMBA 654 select CLKSRC_MPS2 655 help 656 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 657 with a range of available cores like Cortex-M3/M4/M7. 658 659 Please, note that depends which Application Note is used memory map 660 for the platform may vary, so adjustment of RAM base might be needed. 661 662# Definitions to make life easier 663config ARCH_ACORN 664 bool 665 666config PLAT_ORION 667 bool 668 select CLKSRC_MMIO 669 select COMMON_CLK 670 select GENERIC_IRQ_CHIP 671 select IRQ_DOMAIN 672 673config PLAT_ORION_LEGACY 674 bool 675 select PLAT_ORION 676 677config PLAT_PXA 678 bool 679 680config PLAT_VERSATILE 681 bool 682 683source "arch/arm/mm/Kconfig" 684 685config IWMMXT 686 bool "Enable iWMMXt support" 687 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 688 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 689 help 690 Enable support for iWMMXt context switching at run time if 691 running on a CPU that supports it. 692 693if !MMU 694source "arch/arm/Kconfig-nommu" 695endif 696 697config PJ4B_ERRATA_4742 698 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 699 depends on CPU_PJ4B && MACH_ARMADA_370 700 default y 701 help 702 When coming out of either a Wait for Interrupt (WFI) or a Wait for 703 Event (WFE) IDLE states, a specific timing sensitivity exists between 704 the retiring WFI/WFE instructions and the newly issued subsequent 705 instructions. This sensitivity can result in a CPU hang scenario. 706 Workaround: 707 The software must insert either a Data Synchronization Barrier (DSB) 708 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 709 instruction 710 711config ARM_ERRATA_326103 712 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 713 depends on CPU_V6 714 help 715 Executing a SWP instruction to read-only memory does not set bit 11 716 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 717 treat the access as a read, preventing a COW from occurring and 718 causing the faulting task to livelock. 719 720config ARM_ERRATA_411920 721 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 722 depends on CPU_V6 || CPU_V6K 723 help 724 Invalidation of the Instruction Cache operation can 725 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 726 It does not affect the MPCore. This option enables the ARM Ltd. 727 recommended workaround. 728 729config ARM_ERRATA_430973 730 bool "ARM errata: Stale prediction on replaced interworking branch" 731 depends on CPU_V7 732 help 733 This option enables the workaround for the 430973 Cortex-A8 734 r1p* erratum. If a code sequence containing an ARM/Thumb 735 interworking branch is replaced with another code sequence at the 736 same virtual address, whether due to self-modifying code or virtual 737 to physical address re-mapping, Cortex-A8 does not recover from the 738 stale interworking branch prediction. This results in Cortex-A8 739 executing the new code sequence in the incorrect ARM or Thumb state. 740 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 741 and also flushes the branch target cache at every context switch. 742 Note that setting specific bits in the ACTLR register may not be 743 available in non-secure mode. 744 745config ARM_ERRATA_458693 746 bool "ARM errata: Processor deadlock when a false hazard is created" 747 depends on CPU_V7 748 depends on !ARCH_MULTIPLATFORM 749 help 750 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 751 erratum. For very specific sequences of memory operations, it is 752 possible for a hazard condition intended for a cache line to instead 753 be incorrectly associated with a different cache line. This false 754 hazard might then cause a processor deadlock. The workaround enables 755 the L1 caching of the NEON accesses and disables the PLD instruction 756 in the ACTLR register. Note that setting specific bits in the ACTLR 757 register may not be available in non-secure mode. 758 759config ARM_ERRATA_460075 760 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 761 depends on CPU_V7 762 depends on !ARCH_MULTIPLATFORM 763 help 764 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 765 erratum. Any asynchronous access to the L2 cache may encounter a 766 situation in which recent store transactions to the L2 cache are lost 767 and overwritten with stale memory contents from external memory. The 768 workaround disables the write-allocate mode for the L2 cache via the 769 ACTLR register. Note that setting specific bits in the ACTLR register 770 may not be available in non-secure mode. 771 772config ARM_ERRATA_742230 773 bool "ARM errata: DMB operation may be faulty" 774 depends on CPU_V7 && SMP 775 depends on !ARCH_MULTIPLATFORM 776 help 777 This option enables the workaround for the 742230 Cortex-A9 778 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 779 between two write operations may not ensure the correct visibility 780 ordering of the two writes. This workaround sets a specific bit in 781 the diagnostic register of the Cortex-A9 which causes the DMB 782 instruction to behave as a DSB, ensuring the correct behaviour of 783 the two writes. 784 785config ARM_ERRATA_742231 786 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 787 depends on CPU_V7 && SMP 788 depends on !ARCH_MULTIPLATFORM 789 help 790 This option enables the workaround for the 742231 Cortex-A9 791 (r2p0..r2p2) erratum. Under certain conditions, specific to the 792 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 793 accessing some data located in the same cache line, may get corrupted 794 data due to bad handling of the address hazard when the line gets 795 replaced from one of the CPUs at the same time as another CPU is 796 accessing it. This workaround sets specific bits in the diagnostic 797 register of the Cortex-A9 which reduces the linefill issuing 798 capabilities of the processor. 799 800config ARM_ERRATA_643719 801 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 802 depends on CPU_V7 && SMP 803 default y 804 help 805 This option enables the workaround for the 643719 Cortex-A9 (prior to 806 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 807 register returns zero when it should return one. The workaround 808 corrects this value, ensuring cache maintenance operations which use 809 it behave as intended and avoiding data corruption. 810 811config ARM_ERRATA_720789 812 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 813 depends on CPU_V7 814 help 815 This option enables the workaround for the 720789 Cortex-A9 (prior to 816 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 817 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 818 As a consequence of this erratum, some TLB entries which should be 819 invalidated are not, resulting in an incoherency in the system page 820 tables. The workaround changes the TLB flushing routines to invalidate 821 entries regardless of the ASID. 822 823config ARM_ERRATA_743622 824 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 825 depends on CPU_V7 826 depends on !ARCH_MULTIPLATFORM 827 help 828 This option enables the workaround for the 743622 Cortex-A9 829 (r2p*) erratum. Under very rare conditions, a faulty 830 optimisation in the Cortex-A9 Store Buffer may lead to data 831 corruption. This workaround sets a specific bit in the diagnostic 832 register of the Cortex-A9 which disables the Store Buffer 833 optimisation, preventing the defect from occurring. This has no 834 visible impact on the overall performance or power consumption of the 835 processor. 836 837config ARM_ERRATA_751472 838 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 839 depends on CPU_V7 840 depends on !ARCH_MULTIPLATFORM 841 help 842 This option enables the workaround for the 751472 Cortex-A9 (prior 843 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 844 completion of a following broadcasted operation if the second 845 operation is received by a CPU before the ICIALLUIS has completed, 846 potentially leading to corrupted entries in the cache or TLB. 847 848config ARM_ERRATA_754322 849 bool "ARM errata: possible faulty MMU translations following an ASID switch" 850 depends on CPU_V7 851 help 852 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 853 r3p*) erratum. A speculative memory access may cause a page table walk 854 which starts prior to an ASID switch but completes afterwards. This 855 can populate the micro-TLB with a stale entry which may be hit with 856 the new ASID. This workaround places two dsb instructions in the mm 857 switching code so that no page table walks can cross the ASID switch. 858 859config ARM_ERRATA_754327 860 bool "ARM errata: no automatic Store Buffer drain" 861 depends on CPU_V7 && SMP 862 help 863 This option enables the workaround for the 754327 Cortex-A9 (prior to 864 r2p0) erratum. The Store Buffer does not have any automatic draining 865 mechanism and therefore a livelock may occur if an external agent 866 continuously polls a memory location waiting to observe an update. 867 This workaround defines cpu_relax() as smp_mb(), preventing correctly 868 written polling loops from denying visibility of updates to memory. 869 870config ARM_ERRATA_364296 871 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 872 depends on CPU_V6 873 help 874 This options enables the workaround for the 364296 ARM1136 875 r0p2 erratum (possible cache data corruption with 876 hit-under-miss enabled). It sets the undocumented bit 31 in 877 the auxiliary control register and the FI bit in the control 878 register, thus disabling hit-under-miss without putting the 879 processor into full low interrupt latency mode. ARM11MPCore 880 is not affected. 881 882config ARM_ERRATA_764369 883 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 884 depends on CPU_V7 && SMP 885 help 886 This option enables the workaround for erratum 764369 887 affecting Cortex-A9 MPCore with two or more processors (all 888 current revisions). Under certain timing circumstances, a data 889 cache line maintenance operation by MVA targeting an Inner 890 Shareable memory region may fail to proceed up to either the 891 Point of Coherency or to the Point of Unification of the 892 system. This workaround adds a DSB instruction before the 893 relevant cache maintenance functions and sets a specific bit 894 in the diagnostic control register of the SCU. 895 896config ARM_ERRATA_764319 897 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 898 depends on CPU_V7 899 help 900 This option enables the workaround for the 764319 Cortex A-9 erratum. 901 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 902 unexpected Undefined Instruction exception when the DBGSWENABLE 903 external pin is set to 0, even when the CP14 accesses are performed 904 from a privileged mode. This work around catches the exception in a 905 way the kernel does not stop execution. 906 907config ARM_ERRATA_775420 908 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 909 depends on CPU_V7 910 help 911 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 912 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 913 operation aborts with MMU exception, it might cause the processor 914 to deadlock. This workaround puts DSB before executing ISB if 915 an abort may occur on cache maintenance. 916 917config ARM_ERRATA_798181 918 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 919 depends on CPU_V7 && SMP 920 help 921 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 922 adequately shooting down all use of the old entries. This 923 option enables the Linux kernel workaround for this erratum 924 which sends an IPI to the CPUs that are running the same ASID 925 as the one being invalidated. 926 927config ARM_ERRATA_773022 928 bool "ARM errata: incorrect instructions may be executed from loop buffer" 929 depends on CPU_V7 930 help 931 This option enables the workaround for the 773022 Cortex-A15 932 (up to r0p4) erratum. In certain rare sequences of code, the 933 loop buffer may deliver incorrect instructions. This 934 workaround disables the loop buffer to avoid the erratum. 935 936config ARM_ERRATA_818325_852422 937 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 938 depends on CPU_V7 939 help 940 This option enables the workaround for: 941 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 942 instruction might deadlock. Fixed in r0p1. 943 - Cortex-A12 852422: Execution of a sequence of instructions might 944 lead to either a data corruption or a CPU deadlock. Not fixed in 945 any Cortex-A12 cores yet. 946 This workaround for all both errata involves setting bit[12] of the 947 Feature Register. This bit disables an optimisation applied to a 948 sequence of 2 instructions that use opposing condition codes. 949 950config ARM_ERRATA_821420 951 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 952 depends on CPU_V7 953 help 954 This option enables the workaround for the 821420 Cortex-A12 955 (all revs) erratum. In very rare timing conditions, a sequence 956 of VMOV to Core registers instructions, for which the second 957 one is in the shadow of a branch or abort, can lead to a 958 deadlock when the VMOV instructions are issued out-of-order. 959 960config ARM_ERRATA_825619 961 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 962 depends on CPU_V7 963 help 964 This option enables the workaround for the 825619 Cortex-A12 965 (all revs) erratum. Within rare timing constraints, executing a 966 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 967 and Device/Strongly-Ordered loads and stores might cause deadlock 968 969config ARM_ERRATA_857271 970 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 971 depends on CPU_V7 972 help 973 This option enables the workaround for the 857271 Cortex-A12 974 (all revs) erratum. Under very rare timing conditions, the CPU might 975 hang. The workaround is expected to have a < 1% performance impact. 976 977config ARM_ERRATA_852421 978 bool "ARM errata: A17: DMB ST might fail to create order between stores" 979 depends on CPU_V7 980 help 981 This option enables the workaround for the 852421 Cortex-A17 982 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 983 execution of a DMB ST instruction might fail to properly order 984 stores from GroupA and stores from GroupB. 985 986config ARM_ERRATA_852423 987 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 988 depends on CPU_V7 989 help 990 This option enables the workaround for: 991 - Cortex-A17 852423: Execution of a sequence of instructions might 992 lead to either a data corruption or a CPU deadlock. Not fixed in 993 any Cortex-A17 cores yet. 994 This is identical to Cortex-A12 erratum 852422. It is a separate 995 config option from the A12 erratum due to the way errata are checked 996 for and handled. 997 998config ARM_ERRATA_857272 999 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1000 depends on CPU_V7 1001 help 1002 This option enables the workaround for the 857272 Cortex-A17 erratum. 1003 This erratum is not known to be fixed in any A17 revision. 1004 This is identical to Cortex-A12 erratum 857271. It is a separate 1005 config option from the A12 erratum due to the way errata are checked 1006 for and handled. 1007 1008endmenu 1009 1010source "arch/arm/common/Kconfig" 1011 1012menu "Bus support" 1013 1014config ISA 1015 bool 1016 help 1017 Find out whether you have ISA slots on your motherboard. ISA is the 1018 name of a bus system, i.e. the way the CPU talks to the other stuff 1019 inside your box. Other bus systems are PCI, EISA, MicroChannel 1020 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1021 newer boards don't support it. If you have ISA, say Y, otherwise N. 1022 1023# Select ISA DMA controller support 1024config ISA_DMA 1025 bool 1026 select ISA_DMA_API 1027 1028# Select ISA DMA interface 1029config ISA_DMA_API 1030 bool 1031 1032config PCI_NANOENGINE 1033 bool "BSE nanoEngine PCI support" 1034 depends on SA1100_NANOENGINE 1035 help 1036 Enable PCI on the BSE nanoEngine board. 1037 1038config ARM_ERRATA_814220 1039 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1040 depends on CPU_V7 1041 help 1042 The v7 ARM states that all cache and branch predictor maintenance 1043 operations that do not specify an address execute, relative to 1044 each other, in program order. 1045 However, because of this erratum, an L2 set/way cache maintenance 1046 operation can overtake an L1 set/way cache maintenance operation. 1047 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1048 r0p4, r0p5. 1049 1050endmenu 1051 1052menu "Kernel Features" 1053 1054config HAVE_SMP 1055 bool 1056 help 1057 This option should be selected by machines which have an SMP- 1058 capable CPU. 1059 1060 The only effect of this option is to make the SMP-related 1061 options available to the user for configuration. 1062 1063config SMP 1064 bool "Symmetric Multi-Processing" 1065 depends on CPU_V6K || CPU_V7 1066 depends on HAVE_SMP 1067 depends on MMU || ARM_MPU 1068 select IRQ_WORK 1069 help 1070 This enables support for systems with more than one CPU. If you have 1071 a system with only one CPU, say N. If you have a system with more 1072 than one CPU, say Y. 1073 1074 If you say N here, the kernel will run on uni- and multiprocessor 1075 machines, but will use only one CPU of a multiprocessor machine. If 1076 you say Y here, the kernel will run on many, but not all, 1077 uniprocessor machines. On a uniprocessor machine, the kernel 1078 will run faster if you say N here. 1079 1080 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1081 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1082 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1083 1084 If you don't know what to do here, say N. 1085 1086config SMP_ON_UP 1087 bool "Allow booting SMP kernel on uniprocessor systems" 1088 depends on SMP && !XIP_KERNEL && MMU 1089 default y 1090 help 1091 SMP kernels contain instructions which fail on non-SMP processors. 1092 Enabling this option allows the kernel to modify itself to make 1093 these instructions safe. Disabling it allows about 1K of space 1094 savings. 1095 1096 If you don't know what to do here, say Y. 1097 1098 1099config CURRENT_POINTER_IN_TPIDRURO 1100 def_bool y 1101 depends on CPU_32v6K && !CPU_V6 1102 1103config IRQSTACKS 1104 def_bool y 1105 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1106 select HAVE_SOFTIRQ_ON_OWN_STACK 1107 1108config ARM_CPU_TOPOLOGY 1109 bool "Support cpu topology definition" 1110 depends on SMP && CPU_V7 1111 default y 1112 help 1113 Support ARM cpu topology definition. The MPIDR register defines 1114 affinity between processors which is then used to describe the cpu 1115 topology of an ARM System. 1116 1117config SCHED_MC 1118 bool "Multi-core scheduler support" 1119 depends on ARM_CPU_TOPOLOGY 1120 help 1121 Multi-core scheduler support improves the CPU scheduler's decision 1122 making when dealing with multi-core CPU chips at a cost of slightly 1123 increased overhead in some places. If unsure say N here. 1124 1125config SCHED_SMT 1126 bool "SMT scheduler support" 1127 depends on ARM_CPU_TOPOLOGY 1128 help 1129 Improves the CPU scheduler's decision making when dealing with 1130 MultiThreading at a cost of slightly increased overhead in some 1131 places. If unsure say N here. 1132 1133config HAVE_ARM_SCU 1134 bool 1135 help 1136 This option enables support for the ARM snoop control unit 1137 1138config HAVE_ARM_ARCH_TIMER 1139 bool "Architected timer support" 1140 depends on CPU_V7 1141 select ARM_ARCH_TIMER 1142 help 1143 This option enables support for the ARM architected timer 1144 1145config HAVE_ARM_TWD 1146 bool 1147 help 1148 This options enables support for the ARM timer and watchdog unit 1149 1150config MCPM 1151 bool "Multi-Cluster Power Management" 1152 depends on CPU_V7 && SMP 1153 help 1154 This option provides the common power management infrastructure 1155 for (multi-)cluster based systems, such as big.LITTLE based 1156 systems. 1157 1158config MCPM_QUAD_CLUSTER 1159 bool 1160 depends on MCPM 1161 help 1162 To avoid wasting resources unnecessarily, MCPM only supports up 1163 to 2 clusters by default. 1164 Platforms with 3 or 4 clusters that use MCPM must select this 1165 option to allow the additional clusters to be managed. 1166 1167config BIG_LITTLE 1168 bool "big.LITTLE support (Experimental)" 1169 depends on CPU_V7 && SMP 1170 select MCPM 1171 help 1172 This option enables support selections for the big.LITTLE 1173 system architecture. 1174 1175config BL_SWITCHER 1176 bool "big.LITTLE switcher support" 1177 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1178 select CPU_PM 1179 help 1180 The big.LITTLE "switcher" provides the core functionality to 1181 transparently handle transition between a cluster of A15's 1182 and a cluster of A7's in a big.LITTLE system. 1183 1184config BL_SWITCHER_DUMMY_IF 1185 tristate "Simple big.LITTLE switcher user interface" 1186 depends on BL_SWITCHER && DEBUG_KERNEL 1187 help 1188 This is a simple and dummy char dev interface to control 1189 the big.LITTLE switcher core code. It is meant for 1190 debugging purposes only. 1191 1192choice 1193 prompt "Memory split" 1194 depends on MMU 1195 default VMSPLIT_3G 1196 help 1197 Select the desired split between kernel and user memory. 1198 1199 If you are not absolutely sure what you are doing, leave this 1200 option alone! 1201 1202 config VMSPLIT_3G 1203 bool "3G/1G user/kernel split" 1204 config VMSPLIT_3G_OPT 1205 depends on !ARM_LPAE 1206 bool "3G/1G user/kernel split (for full 1G low memory)" 1207 config VMSPLIT_2G 1208 bool "2G/2G user/kernel split" 1209 config VMSPLIT_1G 1210 bool "1G/3G user/kernel split" 1211endchoice 1212 1213config PAGE_OFFSET 1214 hex 1215 default PHYS_OFFSET if !MMU 1216 default 0x40000000 if VMSPLIT_1G 1217 default 0x80000000 if VMSPLIT_2G 1218 default 0xB0000000 if VMSPLIT_3G_OPT 1219 default 0xC0000000 1220 1221config KASAN_SHADOW_OFFSET 1222 hex 1223 depends on KASAN 1224 default 0x1f000000 if PAGE_OFFSET=0x40000000 1225 default 0x5f000000 if PAGE_OFFSET=0x80000000 1226 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1227 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1228 default 0xffffffff 1229 1230config NR_CPUS 1231 int "Maximum number of CPUs (2-32)" 1232 range 2 16 if DEBUG_KMAP_LOCAL 1233 range 2 32 if !DEBUG_KMAP_LOCAL 1234 depends on SMP 1235 default "4" 1236 help 1237 The maximum number of CPUs that the kernel can support. 1238 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1239 debugging is enabled, which uses half of the per-CPU fixmap 1240 slots as guard regions. 1241 1242config HOTPLUG_CPU 1243 bool "Support for hot-pluggable CPUs" 1244 depends on SMP 1245 select GENERIC_IRQ_MIGRATION 1246 help 1247 Say Y here to experiment with turning CPUs off and on. CPUs 1248 can be controlled through /sys/devices/system/cpu. 1249 1250config ARM_PSCI 1251 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1252 depends on HAVE_ARM_SMCCC 1253 select ARM_PSCI_FW 1254 help 1255 Say Y here if you want Linux to communicate with system firmware 1256 implementing the PSCI specification for CPU-centric power 1257 management operations described in ARM document number ARM DEN 1258 0022A ("Power State Coordination Interface System Software on 1259 ARM processors"). 1260 1261# The GPIO number here must be sorted by descending number. In case of 1262# a multiplatform kernel, we just want the highest value required by the 1263# selected platforms. 1264config ARCH_NR_GPIO 1265 int 1266 default 2048 if ARCH_INTEL_SOCFPGA 1267 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1268 ARCH_ZYNQ || ARCH_ASPEED 1269 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1270 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1271 default 416 if ARCH_SUNXI 1272 default 392 if ARCH_U8500 1273 default 352 if ARCH_VT8500 1274 default 288 if ARCH_ROCKCHIP 1275 default 264 if MACH_H4700 1276 default 0 1277 help 1278 Maximum number of GPIOs in the system. 1279 1280 If unsure, leave the default value. 1281 1282config HZ_FIXED 1283 int 1284 default 128 if SOC_AT91RM9200 1285 default 0 1286 1287choice 1288 depends on HZ_FIXED = 0 1289 prompt "Timer frequency" 1290 1291config HZ_100 1292 bool "100 Hz" 1293 1294config HZ_200 1295 bool "200 Hz" 1296 1297config HZ_250 1298 bool "250 Hz" 1299 1300config HZ_300 1301 bool "300 Hz" 1302 1303config HZ_500 1304 bool "500 Hz" 1305 1306config HZ_1000 1307 bool "1000 Hz" 1308 1309endchoice 1310 1311config HZ 1312 int 1313 default HZ_FIXED if HZ_FIXED != 0 1314 default 100 if HZ_100 1315 default 200 if HZ_200 1316 default 250 if HZ_250 1317 default 300 if HZ_300 1318 default 500 if HZ_500 1319 default 1000 1320 1321config SCHED_HRTICK 1322 def_bool HIGH_RES_TIMERS 1323 1324config THUMB2_KERNEL 1325 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1326 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1327 default y if CPU_THUMBONLY 1328 select ARM_UNWIND 1329 help 1330 By enabling this option, the kernel will be compiled in 1331 Thumb-2 mode. 1332 1333 If unsure, say N. 1334 1335config ARM_PATCH_IDIV 1336 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1337 depends on CPU_32v7 && !XIP_KERNEL 1338 default y 1339 help 1340 The ARM compiler inserts calls to __aeabi_idiv() and 1341 __aeabi_uidiv() when it needs to perform division on signed 1342 and unsigned integers. Some v7 CPUs have support for the sdiv 1343 and udiv instructions that can be used to implement those 1344 functions. 1345 1346 Enabling this option allows the kernel to modify itself to 1347 replace the first two instructions of these library functions 1348 with the sdiv or udiv plus "bx lr" instructions when the CPU 1349 it is running on supports them. Typically this will be faster 1350 and less power intensive than running the original library 1351 code to do integer division. 1352 1353config AEABI 1354 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1355 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1356 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1357 help 1358 This option allows for the kernel to be compiled using the latest 1359 ARM ABI (aka EABI). This is only useful if you are using a user 1360 space environment that is also compiled with EABI. 1361 1362 Since there are major incompatibilities between the legacy ABI and 1363 EABI, especially with regard to structure member alignment, this 1364 option also changes the kernel syscall calling convention to 1365 disambiguate both ABIs and allow for backward compatibility support 1366 (selected with CONFIG_OABI_COMPAT). 1367 1368 To use this you need GCC version 4.0.0 or later. 1369 1370config OABI_COMPAT 1371 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1372 depends on AEABI && !THUMB2_KERNEL 1373 help 1374 This option preserves the old syscall interface along with the 1375 new (ARM EABI) one. It also provides a compatibility layer to 1376 intercept syscalls that have structure arguments which layout 1377 in memory differs between the legacy ABI and the new ARM EABI 1378 (only for non "thumb" binaries). This option adds a tiny 1379 overhead to all syscalls and produces a slightly larger kernel. 1380 1381 The seccomp filter system will not be available when this is 1382 selected, since there is no way yet to sensibly distinguish 1383 between calling conventions during filtering. 1384 1385 If you know you'll be using only pure EABI user space then you 1386 can say N here. If this option is not selected and you attempt 1387 to execute a legacy ABI binary then the result will be 1388 UNPREDICTABLE (in fact it can be predicted that it won't work 1389 at all). If in doubt say N. 1390 1391config ARCH_SELECT_MEMORY_MODEL 1392 bool 1393 1394config ARCH_FLATMEM_ENABLE 1395 bool 1396 1397config ARCH_SPARSEMEM_ENABLE 1398 bool 1399 select SPARSEMEM_STATIC if SPARSEMEM 1400 1401config HIGHMEM 1402 bool "High Memory Support" 1403 depends on MMU 1404 select KMAP_LOCAL 1405 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1406 help 1407 The address space of ARM processors is only 4 Gigabytes large 1408 and it has to accommodate user address space, kernel address 1409 space as well as some memory mapped IO. That means that, if you 1410 have a large amount of physical memory and/or IO, not all of the 1411 memory can be "permanently mapped" by the kernel. The physical 1412 memory that is not permanently mapped is called "high memory". 1413 1414 Depending on the selected kernel/user memory split, minimum 1415 vmalloc space and actual amount of RAM, you may not need this 1416 option which should result in a slightly faster kernel. 1417 1418 If unsure, say n. 1419 1420config HIGHPTE 1421 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1422 depends on HIGHMEM 1423 default y 1424 help 1425 The VM uses one page of physical memory for each page table. 1426 For systems with a lot of processes, this can use a lot of 1427 precious low memory, eventually leading to low memory being 1428 consumed by page tables. Setting this option will allow 1429 user-space 2nd level page tables to reside in high memory. 1430 1431config CPU_SW_DOMAIN_PAN 1432 bool "Enable use of CPU domains to implement privileged no-access" 1433 depends on MMU && !ARM_LPAE 1434 default y 1435 help 1436 Increase kernel security by ensuring that normal kernel accesses 1437 are unable to access userspace addresses. This can help prevent 1438 use-after-free bugs becoming an exploitable privilege escalation 1439 by ensuring that magic values (such as LIST_POISON) will always 1440 fault when dereferenced. 1441 1442 CPUs with low-vector mappings use a best-efforts implementation. 1443 Their lower 1MB needs to remain accessible for the vectors, but 1444 the remainder of userspace will become appropriately inaccessible. 1445 1446config HW_PERF_EVENTS 1447 def_bool y 1448 depends on ARM_PMU 1449 1450config ARM_MODULE_PLTS 1451 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1452 depends on MODULES 1453 default y 1454 help 1455 Allocate PLTs when loading modules so that jumps and calls whose 1456 targets are too far away for their relative offsets to be encoded 1457 in the instructions themselves can be bounced via veneers in the 1458 module's PLT. This allows modules to be allocated in the generic 1459 vmalloc area after the dedicated module memory area has been 1460 exhausted. The modules will use slightly more memory, but after 1461 rounding up to page size, the actual memory footprint is usually 1462 the same. 1463 1464 Disabling this is usually safe for small single-platform 1465 configurations. If unsure, say y. 1466 1467config FORCE_MAX_ZONEORDER 1468 int "Maximum zone order" 1469 default "12" if SOC_AM33XX 1470 default "9" if SA1111 1471 default "11" 1472 help 1473 The kernel memory allocator divides physically contiguous memory 1474 blocks into "zones", where each zone is a power of two number of 1475 pages. This option selects the largest power of two that the kernel 1476 keeps in the memory allocator. If you need to allocate very large 1477 blocks of physically contiguous memory, then you may need to 1478 increase this value. 1479 1480 This config option is actually maximum order plus one. For example, 1481 a value of 11 means that the largest free memory block is 2^10 pages. 1482 1483config ALIGNMENT_TRAP 1484 def_bool CPU_CP15_MMU 1485 select HAVE_PROC_CPU if PROC_FS 1486 help 1487 ARM processors cannot fetch/store information which is not 1488 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1489 address divisible by 4. On 32-bit ARM processors, these non-aligned 1490 fetch/store instructions will be emulated in software if you say 1491 here, which has a severe performance impact. This is necessary for 1492 correct operation of some network protocols. With an IP-only 1493 configuration it is safe to say N, otherwise say Y. 1494 1495config UACCESS_WITH_MEMCPY 1496 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1497 depends on MMU 1498 default y if CPU_FEROCEON 1499 help 1500 Implement faster copy_to_user and clear_user methods for CPU 1501 cores where a 8-word STM instruction give significantly higher 1502 memory write throughput than a sequence of individual 32bit stores. 1503 1504 A possible side effect is a slight increase in scheduling latency 1505 between threads sharing the same address space if they invoke 1506 such copy operations with large buffers. 1507 1508 However, if the CPU data cache is using a write-allocate mode, 1509 this option is unlikely to provide any performance gain. 1510 1511config PARAVIRT 1512 bool "Enable paravirtualization code" 1513 help 1514 This changes the kernel so it can modify itself when it is run 1515 under a hypervisor, potentially improving performance significantly 1516 over full virtualization. 1517 1518config PARAVIRT_TIME_ACCOUNTING 1519 bool "Paravirtual steal time accounting" 1520 select PARAVIRT 1521 help 1522 Select this option to enable fine granularity task steal time 1523 accounting. Time spent executing other tasks in parallel with 1524 the current vCPU is discounted from the vCPU power. To account for 1525 that, there can be a small performance impact. 1526 1527 If in doubt, say N here. 1528 1529config XEN_DOM0 1530 def_bool y 1531 depends on XEN 1532 1533config XEN 1534 bool "Xen guest support on ARM" 1535 depends on ARM && AEABI && OF 1536 depends on CPU_V7 && !CPU_V6 1537 depends on !GENERIC_ATOMIC64 1538 depends on MMU 1539 select ARCH_DMA_ADDR_T_64BIT 1540 select ARM_PSCI 1541 select SWIOTLB 1542 select SWIOTLB_XEN 1543 select PARAVIRT 1544 help 1545 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1546 1547config CC_HAVE_STACKPROTECTOR_TLS 1548 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1549 1550config STACKPROTECTOR_PER_TASK 1551 bool "Use a unique stack canary value for each task" 1552 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1553 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1554 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1555 default y 1556 help 1557 Due to the fact that GCC uses an ordinary symbol reference from 1558 which to load the value of the stack canary, this value can only 1559 change at reboot time on SMP systems, and all tasks running in the 1560 kernel's address space are forced to use the same canary value for 1561 the entire duration that the system is up. 1562 1563 Enable this option to switch to a different method that uses a 1564 different canary value for each task. 1565 1566endmenu 1567 1568menu "Boot options" 1569 1570config USE_OF 1571 bool "Flattened Device Tree support" 1572 select IRQ_DOMAIN 1573 select OF 1574 help 1575 Include support for flattened device tree machine descriptions. 1576 1577config ATAGS 1578 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1579 default y 1580 help 1581 This is the traditional way of passing data to the kernel at boot 1582 time. If you are solely relying on the flattened device tree (or 1583 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1584 to remove ATAGS support from your kernel binary. If unsure, 1585 leave this to y. 1586 1587config DEPRECATED_PARAM_STRUCT 1588 bool "Provide old way to pass kernel parameters" 1589 depends on ATAGS 1590 help 1591 This was deprecated in 2001 and announced to live on for 5 years. 1592 Some old boot loaders still use this way. 1593 1594# Compressed boot loader in ROM. Yes, we really want to ask about 1595# TEXT and BSS so we preserve their values in the config files. 1596config ZBOOT_ROM_TEXT 1597 hex "Compressed ROM boot loader base address" 1598 default 0x0 1599 help 1600 The physical address at which the ROM-able zImage is to be 1601 placed in the target. Platforms which normally make use of 1602 ROM-able zImage formats normally set this to a suitable 1603 value in their defconfig file. 1604 1605 If ZBOOT_ROM is not enabled, this has no effect. 1606 1607config ZBOOT_ROM_BSS 1608 hex "Compressed ROM boot loader BSS address" 1609 default 0x0 1610 help 1611 The base address of an area of read/write memory in the target 1612 for the ROM-able zImage which must be available while the 1613 decompressor is running. It must be large enough to hold the 1614 entire decompressed kernel plus an additional 128 KiB. 1615 Platforms which normally make use of ROM-able zImage formats 1616 normally set this to a suitable value in their defconfig file. 1617 1618 If ZBOOT_ROM is not enabled, this has no effect. 1619 1620config ZBOOT_ROM 1621 bool "Compressed boot loader in ROM/flash" 1622 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1623 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1624 help 1625 Say Y here if you intend to execute your compressed kernel image 1626 (zImage) directly from ROM or flash. If unsure, say N. 1627 1628config ARM_APPENDED_DTB 1629 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1630 depends on OF 1631 help 1632 With this option, the boot code will look for a device tree binary 1633 (DTB) appended to zImage 1634 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1635 1636 This is meant as a backward compatibility convenience for those 1637 systems with a bootloader that can't be upgraded to accommodate 1638 the documented boot protocol using a device tree. 1639 1640 Beware that there is very little in terms of protection against 1641 this option being confused by leftover garbage in memory that might 1642 look like a DTB header after a reboot if no actual DTB is appended 1643 to zImage. Do not leave this option active in a production kernel 1644 if you don't intend to always append a DTB. Proper passing of the 1645 location into r2 of a bootloader provided DTB is always preferable 1646 to this option. 1647 1648config ARM_ATAG_DTB_COMPAT 1649 bool "Supplement the appended DTB with traditional ATAG information" 1650 depends on ARM_APPENDED_DTB 1651 help 1652 Some old bootloaders can't be updated to a DTB capable one, yet 1653 they provide ATAGs with memory configuration, the ramdisk address, 1654 the kernel cmdline string, etc. Such information is dynamically 1655 provided by the bootloader and can't always be stored in a static 1656 DTB. To allow a device tree enabled kernel to be used with such 1657 bootloaders, this option allows zImage to extract the information 1658 from the ATAG list and store it at run time into the appended DTB. 1659 1660choice 1661 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1662 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1663 1664config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1665 bool "Use bootloader kernel arguments if available" 1666 help 1667 Uses the command-line options passed by the boot loader instead of 1668 the device tree bootargs property. If the boot loader doesn't provide 1669 any, the device tree bootargs property will be used. 1670 1671config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1672 bool "Extend with bootloader kernel arguments" 1673 help 1674 The command-line arguments provided by the boot loader will be 1675 appended to the the device tree bootargs property. 1676 1677endchoice 1678 1679config CMDLINE 1680 string "Default kernel command string" 1681 default "" 1682 help 1683 On some architectures (e.g. CATS), there is currently no way 1684 for the boot loader to pass arguments to the kernel. For these 1685 architectures, you should supply some command-line options at build 1686 time by entering them here. As a minimum, you should specify the 1687 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1688 1689choice 1690 prompt "Kernel command line type" if CMDLINE != "" 1691 default CMDLINE_FROM_BOOTLOADER 1692 depends on ATAGS 1693 1694config CMDLINE_FROM_BOOTLOADER 1695 bool "Use bootloader kernel arguments if available" 1696 help 1697 Uses the command-line options passed by the boot loader. If 1698 the boot loader doesn't provide any, the default kernel command 1699 string provided in CMDLINE will be used. 1700 1701config CMDLINE_EXTEND 1702 bool "Extend bootloader kernel arguments" 1703 help 1704 The command-line arguments provided by the boot loader will be 1705 appended to the default kernel command string. 1706 1707config CMDLINE_FORCE 1708 bool "Always use the default kernel command string" 1709 help 1710 Always use the default kernel command string, even if the boot 1711 loader passes other arguments to the kernel. 1712 This is useful if you cannot or don't want to change the 1713 command-line options your boot loader passes to the kernel. 1714endchoice 1715 1716config XIP_KERNEL 1717 bool "Kernel Execute-In-Place from ROM" 1718 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1719 help 1720 Execute-In-Place allows the kernel to run from non-volatile storage 1721 directly addressable by the CPU, such as NOR flash. This saves RAM 1722 space since the text section of the kernel is not loaded from flash 1723 to RAM. Read-write sections, such as the data section and stack, 1724 are still copied to RAM. The XIP kernel is not compressed since 1725 it has to run directly from flash, so it will take more space to 1726 store it. The flash address used to link the kernel object files, 1727 and for storing it, is configuration dependent. Therefore, if you 1728 say Y here, you must know the proper physical address where to 1729 store the kernel image depending on your own flash memory usage. 1730 1731 Also note that the make target becomes "make xipImage" rather than 1732 "make zImage" or "make Image". The final kernel binary to put in 1733 ROM memory will be arch/arm/boot/xipImage. 1734 1735 If unsure, say N. 1736 1737config XIP_PHYS_ADDR 1738 hex "XIP Kernel Physical Location" 1739 depends on XIP_KERNEL 1740 default "0x00080000" 1741 help 1742 This is the physical address in your flash memory the kernel will 1743 be linked for and stored to. This address is dependent on your 1744 own flash usage. 1745 1746config XIP_DEFLATED_DATA 1747 bool "Store kernel .data section compressed in ROM" 1748 depends on XIP_KERNEL 1749 select ZLIB_INFLATE 1750 help 1751 Before the kernel is actually executed, its .data section has to be 1752 copied to RAM from ROM. This option allows for storing that data 1753 in compressed form and decompressed to RAM rather than merely being 1754 copied, saving some precious ROM space. A possible drawback is a 1755 slightly longer boot delay. 1756 1757config KEXEC 1758 bool "Kexec system call (EXPERIMENTAL)" 1759 depends on (!SMP || PM_SLEEP_SMP) 1760 depends on MMU 1761 select KEXEC_CORE 1762 help 1763 kexec is a system call that implements the ability to shutdown your 1764 current kernel, and to start another kernel. It is like a reboot 1765 but it is independent of the system firmware. And like a reboot 1766 you can start any kernel with it, not just Linux. 1767 1768 It is an ongoing process to be certain the hardware in a machine 1769 is properly shutdown, so do not be surprised if this code does not 1770 initially work for you. 1771 1772config ATAGS_PROC 1773 bool "Export atags in procfs" 1774 depends on ATAGS && KEXEC 1775 default y 1776 help 1777 Should the atags used to boot the kernel be exported in an "atags" 1778 file in procfs. Useful with kexec. 1779 1780config CRASH_DUMP 1781 bool "Build kdump crash kernel (EXPERIMENTAL)" 1782 help 1783 Generate crash dump after being started by kexec. This should 1784 be normally only set in special crash dump kernels which are 1785 loaded in the main kernel with kexec-tools into a specially 1786 reserved region and then later executed after a crash by 1787 kdump/kexec. The crash dump kernel must be compiled to a 1788 memory address not used by the main kernel 1789 1790 For more details see Documentation/admin-guide/kdump/kdump.rst 1791 1792config AUTO_ZRELADDR 1793 bool "Auto calculation of the decompressed kernel image address" 1794 help 1795 ZRELADDR is the physical address where the decompressed kernel 1796 image will be placed. If AUTO_ZRELADDR is selected, the address 1797 will be determined at run-time, either by masking the current IP 1798 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1799 This assumes the zImage being placed in the first 128MB from 1800 start of memory. 1801 1802config EFI_STUB 1803 bool 1804 1805config EFI 1806 bool "UEFI runtime support" 1807 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1808 select UCS2_STRING 1809 select EFI_PARAMS_FROM_FDT 1810 select EFI_STUB 1811 select EFI_GENERIC_STUB 1812 select EFI_RUNTIME_WRAPPERS 1813 help 1814 This option provides support for runtime services provided 1815 by UEFI firmware (such as non-volatile variables, realtime 1816 clock, and platform reset). A UEFI stub is also provided to 1817 allow the kernel to be booted as an EFI application. This 1818 is only useful for kernels that may run on systems that have 1819 UEFI firmware. 1820 1821config DMI 1822 bool "Enable support for SMBIOS (DMI) tables" 1823 depends on EFI 1824 default y 1825 help 1826 This enables SMBIOS/DMI feature for systems. 1827 1828 This option is only useful on systems that have UEFI firmware. 1829 However, even with this option, the resultant kernel should 1830 continue to boot on existing non-UEFI platforms. 1831 1832 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1833 i.e., the the practice of identifying the platform via DMI to 1834 decide whether certain workarounds for buggy hardware and/or 1835 firmware need to be enabled. This would require the DMI subsystem 1836 to be enabled much earlier than we do on ARM, which is non-trivial. 1837 1838endmenu 1839 1840menu "CPU Power Management" 1841 1842source "drivers/cpufreq/Kconfig" 1843 1844source "drivers/cpuidle/Kconfig" 1845 1846endmenu 1847 1848menu "Floating point emulation" 1849 1850comment "At least one emulation must be selected" 1851 1852config FPE_NWFPE 1853 bool "NWFPE math emulation" 1854 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1855 help 1856 Say Y to include the NWFPE floating point emulator in the kernel. 1857 This is necessary to run most binaries. Linux does not currently 1858 support floating point hardware so you need to say Y here even if 1859 your machine has an FPA or floating point co-processor podule. 1860 1861 You may say N here if you are going to load the Acorn FPEmulator 1862 early in the bootup. 1863 1864config FPE_NWFPE_XP 1865 bool "Support extended precision" 1866 depends on FPE_NWFPE 1867 help 1868 Say Y to include 80-bit support in the kernel floating-point 1869 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1870 Note that gcc does not generate 80-bit operations by default, 1871 so in most cases this option only enlarges the size of the 1872 floating point emulator without any good reason. 1873 1874 You almost surely want to say N here. 1875 1876config FPE_FASTFPE 1877 bool "FastFPE math emulation (EXPERIMENTAL)" 1878 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1879 help 1880 Say Y here to include the FAST floating point emulator in the kernel. 1881 This is an experimental much faster emulator which now also has full 1882 precision for the mantissa. It does not support any exceptions. 1883 It is very simple, and approximately 3-6 times faster than NWFPE. 1884 1885 It should be sufficient for most programs. It may be not suitable 1886 for scientific calculations, but you have to check this for yourself. 1887 If you do not feel you need a faster FP emulation you should better 1888 choose NWFPE. 1889 1890config VFP 1891 bool "VFP-format floating point maths" 1892 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1893 help 1894 Say Y to include VFP support code in the kernel. This is needed 1895 if your hardware includes a VFP unit. 1896 1897 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1898 release notes and additional status information. 1899 1900 Say N if your target does not have VFP hardware. 1901 1902config VFPv3 1903 bool 1904 depends on VFP 1905 default y if CPU_V7 1906 1907config NEON 1908 bool "Advanced SIMD (NEON) Extension support" 1909 depends on VFPv3 && CPU_V7 1910 help 1911 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1912 Extension. 1913 1914config KERNEL_MODE_NEON 1915 bool "Support for NEON in kernel mode" 1916 depends on NEON && AEABI 1917 help 1918 Say Y to include support for NEON in kernel mode. 1919 1920endmenu 1921 1922menu "Power management options" 1923 1924source "kernel/power/Kconfig" 1925 1926config ARCH_SUSPEND_POSSIBLE 1927 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1928 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1929 def_bool y 1930 1931config ARM_CPU_SUSPEND 1932 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1933 depends on ARCH_SUSPEND_POSSIBLE 1934 1935config ARCH_HIBERNATION_POSSIBLE 1936 bool 1937 depends on MMU 1938 default y if ARCH_SUSPEND_POSSIBLE 1939 1940endmenu 1941 1942if CRYPTO 1943source "arch/arm/crypto/Kconfig" 1944endif 1945 1946source "arch/arm/Kconfig.assembler" 1947