| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 699 struct optc *tgn10 = kzalloc_obj(struct optc); in dcn303_timing_generator_create() local
701 if (!tgn10) in dcn303_timing_generator_create()
704 tgn10->base.inst = instance; in dcn303_timing_generator_create()
705 tgn10->base.ctx = ctx; in dcn303_timing_generator_create()
707 tgn10->tg_regs = &optc_regs[instance]; in dcn303_timing_generator_create()
708 tgn10->tg_shift = &optc_shift; in dcn303_timing_generator_create()
709 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
711 dcn30_timing_generator_init(tgn10); in dcn303_timing_generator_create()
713 return &tgn10->base; in dcn303_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 727 struct optc *tgn10 = kzalloc_obj(struct optc); in dcn302_timing_generator_create() local
729 if (!tgn10) in dcn302_timing_generator_create()
732 tgn10->base.inst = instance; in dcn302_timing_generator_create()
733 tgn10->base.ctx = ctx; in dcn302_timing_generator_create()
735 tgn10->tg_regs = &optc_regs[instance]; in dcn302_timing_generator_create()
736 tgn10->tg_shift = &optc_shift; in dcn302_timing_generator_create()
737 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
739 dcn30_timing_generator_init(tgn10); in dcn302_timing_generator_create()
741 return &tgn10->base; in dcn302_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1124 struct optc *tgn10 = in dcn31_timing_generator_create() local
1127 if (!tgn10) in dcn31_timing_generator_create()
1130 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1131 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1133 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1134 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1135 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1137 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1139 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1189 struct optc *tgn10 = in dcn31_timing_generator_create() local
1192 if (!tgn10) in dcn31_timing_generator_create()
1195 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1196 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1198 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1199 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1200 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1202 dcn314_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1204 return &tgn10->base; in dcn31_timing_generator_create()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1088 struct optc *tgn10 = in dcn35_timing_generator_create() local
1091 if (!tgn10) in dcn35_timing_generator_create()
1101 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1102 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1104 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1105 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1106 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1108 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1110 return &tgn10->base; in dcn35_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1132 struct optc *tgn10 = in dcn31_timing_generator_create() local
1135 if (!tgn10) in dcn31_timing_generator_create()
1138 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1139 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1141 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1142 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1143 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1145 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1147 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1101 struct optc *tgn10 = in dcn35_timing_generator_create() local
1104 if (!tgn10) in dcn35_timing_generator_create()
1114 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1115 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1117 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1118 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1119 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1121 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1123 return &tgn10->base; in dcn35_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1131 struct optc *tgn10 = in dcn31_timing_generator_create() local
1134 if (!tgn10) in dcn31_timing_generator_create()
1137 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1138 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1140 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1141 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1142 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1144 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1146 return &tgn10->base; in dcn31_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1081 struct optc *tgn10 = in dcn35_timing_generator_create() local
1084 if (!tgn10) in dcn35_timing_generator_create()
1094 tgn10->base.inst = instance; in dcn35_timing_generator_create()
1095 tgn10->base.ctx = ctx; in dcn35_timing_generator_create()
1097 tgn10->tg_regs = &optc_regs[instance]; in dcn35_timing_generator_create()
1098 tgn10->tg_shift = &optc_shift; in dcn35_timing_generator_create()
1099 tgn10->tg_mask = &optc_mask; in dcn35_timing_generator_create()
1101 dcn35_timing_generator_init(tgn10); in dcn35_timing_generator_create()
1103 return &tgn10->base; in dcn35_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 1062 struct optc *tgn10 = in dcn321_timing_generator_create() local
1065 if (!tgn10) in dcn321_timing_generator_create()
1075 tgn10->base.inst = instance; in dcn321_timing_generator_create()
1076 tgn10->base.ctx = ctx; in dcn321_timing_generator_create()
1078 tgn10->tg_regs = &optc_regs[instance]; in dcn321_timing_generator_create()
1079 tgn10->tg_shift = &optc_shift; in dcn321_timing_generator_create()
1080 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()
1082 dcn32_timing_generator_init(tgn10); in dcn321_timing_generator_create()
1084 return &tgn10->base; in dcn321_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 1242 struct optc *tgn10 = in dcn60_timing_generator_create() local
1245 if (!tgn10) in dcn60_timing_generator_create()
1254 tgn10->base.inst = instance; in dcn60_timing_generator_create()
1255 tgn10->base.ctx = ctx; in dcn60_timing_generator_create()
1257 tgn10->tg_regs = &optc_regs[instance]; in dcn60_timing_generator_create()
1258 tgn10->tg_shift = &optc_shift; in dcn60_timing_generator_create()
1259 tgn10->tg_mask = &optc_mask; in dcn60_timing_generator_create()
1261 dcn60_timing_generator_init(tgn10); in dcn60_timing_generator_create()
1263 return &tgn10->base; in dcn60_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 1158 struct optc *tgn10 = in dcn42b_timing_generator_create() local
1161 if (!tgn10) in dcn42b_timing_generator_create()
1169 tgn10->base.inst = instance; in dcn42b_timing_generator_create()
1170 tgn10->base.ctx = ctx; in dcn42b_timing_generator_create()
1172 tgn10->tg_regs = &optc_regs[instance]; in dcn42b_timing_generator_create()
1173 tgn10->tg_shift = &optc_shift; in dcn42b_timing_generator_create()
1174 tgn10->tg_mask = &optc_mask; in dcn42b_timing_generator_create()
1176 dcn42_timing_generator_init(tgn10); in dcn42b_timing_generator_create()
1178 return &tgn10->base; in dcn42b_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 1098 struct optc *tgn10 = in dcn42_timing_generator_create() local
1101 if (!tgn10) in dcn42_timing_generator_create()
1109 tgn10->base.inst = instance; in dcn42_timing_generator_create()
1110 tgn10->base.ctx = ctx; in dcn42_timing_generator_create()
1112 tgn10->tg_regs = &optc_regs[instance]; in dcn42_timing_generator_create()
1113 tgn10->tg_shift = &optc_shift; in dcn42_timing_generator_create()
1114 tgn10->tg_mask = &optc_mask; in dcn42_timing_generator_create()
1116 dcn42_timing_generator_init(tgn10); in dcn42_timing_generator_create()
1118 return &tgn10->base; in dcn42_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 1079 struct optc *tgn10 = in dcn401_timing_generator_create() local
1082 if (!tgn10) in dcn401_timing_generator_create()
1091 tgn10->base.inst = instance; in dcn401_timing_generator_create()
1092 tgn10->base.ctx = ctx; in dcn401_timing_generator_create()
1094 tgn10->tg_regs = &optc_regs[instance]; in dcn401_timing_generator_create()
1095 tgn10->tg_shift = &optc_shift; in dcn401_timing_generator_create()
1096 tgn10->tg_mask = &optc_mask; in dcn401_timing_generator_create()
1098 dcn401_timing_generator_init(tgn10); in dcn401_timing_generator_create()
1100 return &tgn10->base; in dcn401_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 965 struct optc *tgn10 = in dcn30_timing_generator_create() local
968 if (!tgn10) in dcn30_timing_generator_create()
971 tgn10->base.inst = instance; in dcn30_timing_generator_create()
972 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
974 tgn10->tg_regs = &optc_regs[instance]; in dcn30_timing_generator_create()
975 tgn10->tg_shift = &optc_shift; in dcn30_timing_generator_create()
976 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
978 dcn30_timing_generator_init(tgn10); in dcn30_timing_generator_create()
980 return &tgn10->base; in dcn30_timing_generator_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1074 struct optc *tgn10 = in dcn32_timing_generator_create() local
1077 if (!tgn10) in dcn32_timing_generator_create()
1087 tgn10->base.inst = instance; in dcn32_timing_generator_create()
1088 tgn10->base.ctx = ctx; in dcn32_timing_generator_create()
1090 tgn10->tg_regs = &optc_regs[instance]; in dcn32_timing_generator_create()
1091 tgn10->tg_shift = &optc_shift; in dcn32_timing_generator_create()
1092 tgn10->tg_mask = &optc_mask; in dcn32_timing_generator_create()
1094 dcn32_timing_generator_init(tgn10); in dcn32_timing_generator_create()
1096 return &tgn10->base; in dcn32_timing_generator_create()
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