1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2026 Advanced Micro Devices, Inc. 4 5 #include "dm_services.h" 6 #include "dc.h" 7 8 #include "dcn32/dcn32_init.h" 9 #include "dcn42/dcn42_init.h" 10 11 #include "resource.h" 12 #include "include/irq_service_interface.h" 13 14 #include "dcn42_resource.h" 15 #include "dcn42_resource_fpu.h" 16 #include "dcn20/dcn20_resource.h" 17 #include "dcn30/dcn30_resource.h" 18 #include "dcn31/dcn31_resource.h" 19 #include "dcn32/dcn32_resource.h" 20 #include "dcn35/dcn35_resource.h" 21 #include "dcn321/dcn321_resource.h" 22 #include "dcn401/dcn401_resource.h" 23 24 #include "dcn10/dcn10_ipp.h" 25 #include "dcn35/dcn35_hubbub.h" 26 #include "dcn42/dcn42_hubbub.h" 27 #include "dcn401/dcn401_mpc.h" 28 #include "dcn42/dcn42_mpc.h" 29 #include "dcn35/dcn35_hubp.h" 30 #include "dcn42/dcn42_hubp.h" 31 #include "irq/dcn42/irq_service_dcn42.h" 32 #include "dcn42/dcn42_dpp.h" 33 #include "dcn401/dcn401_dsc.h" 34 #include "dcn42/dcn42_optc.h" 35 #include "dcn20/dcn20_hwseq.h" 36 #include "dcn30/dcn30_hwseq.h" 37 #include "dce110/dce110_hwseq.h" 38 #include "dcn35/dcn35_opp.h" 39 #include "dcn30/dcn30_vpg.h" 40 #include "dcn31/dcn31_vpg.h" 41 #include "dcn42/dcn42_dio_stream_encoder.h" 42 #include "dcn42/dcn42_pg_cntl.h" 43 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 44 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 45 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 46 #include "dcn42/dcn42_hpo_dp_link_encoder.h" 47 #include "dcn31/dcn31_apg.h" 48 #include "dcn31/dcn31_dio_link_encoder.h" 49 #include "dcn401/dcn401_dio_link_encoder.h" 50 #include "dcn10/dcn10_link_encoder.h" 51 #include "dcn321/dcn321_dio_link_encoder.h" 52 #include "dce/dce_clock_source.h" 53 #include "dce/dce_audio.h" 54 #include "dce/dce_hwseq.h" 55 #include "clk_mgr.h" 56 #include "dio/virtual/virtual_stream_encoder.h" 57 #include "dml/display_mode_vba.h" 58 #include "dcn42/dcn42_dccg.h" 59 #include "dcn10/dcn10_resource.h" 60 #include "link_service.h" 61 #include "dcn31/dcn31_panel_cntl.h" 62 63 #include "dcn30/dcn30_dwb.h" 64 #include "dcn42/dcn42_mmhubbub.h" 65 #include "dcn42/dcn42_dio_link_encoder.h" 66 67 #include "dcn/dcn_4_2_0_offset.h" 68 #include "dcn/dcn_4_2_0_sh_mask.h" 69 #include "dpcs/dpcs_4_0_0_offset.h" 70 #include "dpcs/dpcs_4_0_0_sh_mask.h" 71 72 #include "reg_helper.h" 73 #include "dce/dmub_abm.h" 74 #include "dce/dmub_psr.h" 75 #include "dce/dmub_replay.h" 76 #include "dce/dce_aux.h" 77 #include "dce/dce_i2c.h" 78 79 #include "dml/dcn30/display_mode_vba_30.h" 80 #include "vm_helper.h" 81 #include "dcn20/dcn20_vmid.h" 82 83 #include "dc_state_priv.h" 84 #include "link_enc_cfg.h" 85 86 #include "dml2_0/dml2_wrapper.h" 87 88 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b 89 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 90 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e 91 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 92 93 #define DC_LOGGER_INIT(logger) 94 95 enum dcn401_clk_src_array_id { 96 DCN401_CLK_SRC_PLL0, 97 DCN401_CLK_SRC_PLL1, 98 DCN401_CLK_SRC_PLL2, 99 DCN401_CLK_SRC_PLL3, 100 DCN401_CLK_SRC_PLL4, 101 DCN401_CLK_SRC_TOTAL 102 }; 103 104 /* begin 105 * macros to expend register list macro defined in HW object header file 106 */ 107 108 /* DCN */ 109 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 110 111 #define BASE(seg) BASE_INNER(seg) 112 113 #define SR(reg_name) \ 114 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 115 reg##reg_name 116 #define SR_ARR(reg_name, id) \ 117 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 118 reg##reg_name 119 #define SR_ARR_INIT(reg_name, id, value) \ 120 REG_STRUCT[id].reg_name = value 121 122 #define SRI(reg_name, block, id) \ 123 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 124 reg##block##id##_##reg_name 125 126 #define SRI_ARR(reg_name, block, id) \ 127 REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 128 reg##block##id##_##reg_name 129 130 /* 131 * Used when a reg_name would otherwise begin with an integer 132 */ 133 #define SRI_ARR_US(reg_name, block, id) \ 134 REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ 135 reg##block##id##reg_name 136 #define SR_ARR_I2C(reg_name, id) \ 137 REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 138 139 #define SRI_ARR_I2C(reg_name, block, id) \ 140 REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 141 reg##block##id##_##reg_name 142 143 144 #define SRI_ARR_ALPHABET(reg_name, block, index, id) \ 145 REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 146 reg##block##id##_##reg_name 147 148 #define SRI2(reg_name, block, id) \ 149 .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 150 reg##reg_name 151 #define SRI2_ARR(reg_name, block, id) \ 152 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 153 reg##reg_name 154 155 #define SRIR(var_name, reg_name, block, id) \ 156 .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 157 reg##block##id##_##reg_name 158 159 #define SRII(reg_name, block, id) \ 160 REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 161 reg##block##id##_##reg_name 162 163 #define SRII_ARR_2(reg_name, block, id, inst) \ 164 REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 165 reg##block##id##_##reg_name 166 167 #define SRII_MPC_RMU(reg_name, block, id) \ 168 .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 169 reg##block##id##_##reg_name 170 171 #define SRII_DWB(reg_name, temp_name, block, id) \ 172 REG_STRUCT.reg_name[id] = \ 173 BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ 174 reg##block##id##_##temp_name 175 176 #define DCCG_SRII(reg_name, block, id) \ 177 REG_STRUCT.block##_##reg_name[id] = \ 178 BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 179 reg##block##id##_##reg_name 180 181 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 182 .field_name = reg_name##__##field_name##post_fix 183 184 #define VUPDATE_SRII(reg_name, block, id) \ 185 REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ 186 reg##reg_name##_##block##id 187 188 /* NBIO */ 189 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 190 191 #define NBIO_BASE(seg) \ 192 NBIO_BASE_INNER(seg) 193 194 #define NBIO_SR(reg_name) \ 195 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ 196 regBIF_BX0_##reg_name 197 #define NBIO_SR_ARR(reg_name, id) \ 198 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ 199 regBIF_BX0_##reg_name 200 201 #define CTX ctx 202 #define REG(reg_name) \ 203 (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) 204 205 static struct bios_registers bios_regs; 206 207 #define bios_regs_init() \ 208 NBIO_SR(BIOS_SCRATCH_3), \ 209 NBIO_SR(BIOS_SCRATCH_6) 210 211 #define clk_src_regs_init(index, pllid) \ 212 CS_COMMON_REG_LIST_DCN42_RI(index, pllid) 213 214 static struct dce110_clk_src_regs clk_src_regs[5]; 215 216 static const struct dce110_clk_src_shift cs_shift = { 217 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 218 }; 219 static const struct dce110_clk_src_mask cs_mask = { 220 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 221 }; 222 #define abm_regs_init(id) \ 223 ABM_DCN42_REG_LIST_RI(id) 224 225 static struct dce_abm_registers abm_regs[4]; 226 227 static const struct dce_abm_shift abm_shift = { 228 ABM_MASK_SH_LIST_DCN42(__SHIFT)}; 229 230 static const struct dce_abm_mask abm_mask = { 231 ABM_MASK_SH_LIST_DCN42(_MASK)}; 232 233 #define audio_regs_init(id) \ 234 AUD_COMMON_REG_LIST_RI(id) 235 236 static struct dce_audio_registers audio_regs[5]; 237 238 static const struct dce_audio_shift audio_shift = { 239 DCN42_AUD_COMMON_MASK_SH_LIST(__SHIFT) 240 }; 241 242 static const struct dce_audio_mask audio_mask = { 243 DCN42_AUD_COMMON_MASK_SH_LIST(_MASK) 244 }; 245 246 #define vpg_regs_init(id) \ 247 VPG_DCN401_REG_LIST_RI(id) 248 249 static struct dcn31_vpg_registers vpg_regs[10]; 250 251 static const struct dcn31_vpg_shift vpg_shift = { 252 DCN31_VPG_MASK_SH_LIST(__SHIFT)}; 253 254 static const struct dcn31_vpg_mask vpg_mask = { 255 DCN31_VPG_MASK_SH_LIST(_MASK)}; 256 257 #define apg_regs_init(id) \ 258 APG_DCN31_REG_LIST_RI(id) 259 260 static struct dcn31_apg_registers apg_regs[10]; 261 262 static const struct dcn31_apg_shift apg_shift = { 263 DCN31_APG_MASK_SH_LIST(__SHIFT)}; 264 265 static const struct dcn31_apg_mask apg_mask = { 266 DCN31_APG_MASK_SH_LIST(_MASK)}; 267 268 #define stream_enc_regs_init(id) \ 269 SE_DCN42_REG_LIST_RI(id) 270 271 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 272 273 static const struct dcn10_stream_encoder_shift se_shift = { 274 SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; 275 276 static const struct dcn10_stream_encoder_mask se_mask = { 277 SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; 278 279 #define aux_regs_init(id) \ 280 DCN2_AUX_REG_LIST_RI(id) 281 282 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 283 284 #define hpd_regs_init(id) \ 285 HPD_REG_LIST_RI(id) 286 287 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 288 289 #define link_regs_init(id, phyid) \ 290 LE_DCN401_REG_LIST_RI(id) 291 292 static struct dcn10_link_enc_registers link_enc_regs[5]; 293 294 static const struct dcn10_link_enc_shift le_shift = { 295 LINK_ENCODER_MASK_SH_LIST_DCN42(__SHIFT)}; 296 297 static const struct dcn10_link_enc_mask le_mask = { 298 LINK_ENCODER_MASK_SH_LIST_DCN42(_MASK)}; 299 300 #define hpo_dp_stream_encoder_reg_init(id) \ 301 DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 302 303 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 304 305 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 306 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; 307 308 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 309 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; 310 311 #define hpo_dp_link_encoder_reg_init(id) \ 312 DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) 313 314 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; 315 316 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 317 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; 318 319 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 320 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; 321 322 #define dpp_regs_init(id) \ 323 DPP_REG_LIST_DCN42_COMMON_RI(id) 324 325 static struct dcn42_dpp_registers dpp_regs[4]; 326 327 static const struct dcn42_dpp_shift tf_shift = { 328 DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; 329 330 static const struct dcn42_dpp_mask tf_mask = { 331 DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; 332 333 #define opp_regs_init(id) \ 334 OPP_REG_LIST_DCN401_RI(id) 335 336 static struct dcn20_opp_registers opp_regs[4]; 337 338 static const struct dcn20_opp_shift opp_shift = { 339 OPP_MASK_SH_LIST_DCN20(__SHIFT)}; 340 341 static const struct dcn20_opp_mask opp_mask = { 342 OPP_MASK_SH_LIST_DCN20(_MASK)}; 343 344 #define aux_engine_regs_init(id) \ 345 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 346 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 347 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 348 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) 349 350 static struct dce110_aux_registers aux_engine_regs[5]; 351 352 static const struct dce110_aux_registers_shift aux_shift = { 353 DCN_AUX_MASK_SH_LIST(__SHIFT)}; 354 355 static const struct dce110_aux_registers_mask aux_mask = { 356 DCN_AUX_MASK_SH_LIST(_MASK)}; 357 358 #define dwbc_regs_dcn401_init(id) \ 359 DWBC_COMMON_REG_LIST_DCN30_RI(id) 360 361 static struct dcn30_dwbc_registers dwbc401_regs[1]; 362 363 static const struct dcn30_dwbc_shift dwbc401_shift = { 364 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; 365 366 static const struct dcn30_dwbc_mask dwbc401_mask = { 367 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; 368 369 #define mcif_wb_regs_dcn3_init(id) \ 370 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) 371 372 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; 373 374 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { 375 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; 376 377 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { 378 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; 379 380 #define dsc_regs_init(id) \ 381 DSC_REG_LIST_DCN401_RI(id) 382 383 static struct dcn401_dsc_registers dsc_regs[4]; 384 385 static const struct dcn401_dsc_shift dsc_shift = { 386 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; 387 388 static const struct dcn401_dsc_mask dsc_mask = { 389 DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; 390 391 static struct dcn42_mpc_registers mpc_regs; 392 393 #define dcn_mpc_regs_init() \ 394 MPC_REG_LIST_DCN42(0), \ 395 MPC_REG_LIST_DCN42(1), \ 396 MPC_REG_LIST_DCN42(2), \ 397 MPC_REG_LIST_DCN42(3), \ 398 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ 399 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ 400 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ 401 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ 402 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ 403 MPC_RMCM_REG_LIST_DCN42(0), \ 404 MPC_RMCM_REG_LIST_DCN42(1) 405 406 static const struct dcn42_mpc_shift mpc_shift = { 407 MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; 408 409 static const struct dcn42_mpc_mask mpc_mask = { 410 MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; 411 412 #define optc_regs_init(id) \ 413 OPTC_COMMON_REG_LIST_DCN42_RI(id) 414 415 static struct dcn_optc_registers optc_regs[4]; 416 417 static const struct dcn_optc_shift optc_shift = { 418 OPTC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; 419 420 static const struct dcn_optc_mask optc_mask = { 421 OPTC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; 422 423 #define hubp_regs_init(id) \ 424 HUBP_REG_LIST_DCN42_RI(id) 425 426 static struct dcn_hubp2_registers hubp_regs[4]; 427 428 static const struct dcn_hubp2_shift hubp_shift = { 429 HUBP_MASK_SH_LIST_DCN42(__SHIFT)}; 430 431 static const struct dcn_hubp2_mask hubp_mask = { 432 HUBP_MASK_SH_LIST_DCN42(_MASK)}; 433 434 static struct dcn_hubbub_registers hubbub_reg; 435 436 #define hubbub_reg_init() \ 437 HUBBUB_REG_LIST_DCN42(0) 438 439 static const struct dcn_hubbub_shift hubbub_shift = { 440 HUBBUB_MASK_SH_LIST_DCN4_2(__SHIFT)}; 441 442 static const struct dcn_hubbub_mask hubbub_mask = { 443 HUBBUB_MASK_SH_LIST_DCN4_2(_MASK)}; 444 445 static struct dccg_registers dccg_regs; 446 447 #define dccg_regs_init() \ 448 DCCG_REG_LIST_DCN42_RI() 449 450 static const struct dccg_shift dccg_shift = { 451 DCCG_MASK_SH_LIST_DCN42(__SHIFT)}; 452 453 static const struct dccg_mask dccg_mask = { 454 DCCG_MASK_SH_LIST_DCN42(_MASK)}; 455 456 static struct pg_cntl_registers pg_cntl_regs; 457 458 #define pg_cntl_dcn42_regs_init() \ 459 PG_CNTL_REG_LIST_DCN42() 460 461 static const struct pg_cntl_shift pg_cntl_shift = { 462 PG_CNTL_MASK_SH_LIST_DCN42(__SHIFT) 463 }; 464 465 static const struct pg_cntl_mask pg_cntl_mask = { 466 PG_CNTL_MASK_SH_LIST_DCN42(_MASK) 467 }; 468 #define SRII2(reg_name_pre, reg_name_post, id) \ 469 .reg_name_pre##_##reg_name_post[id] = \ 470 BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ 471 reg##reg_name_pre##id##_##reg_name_post 472 473 #define HWSEQ_DCN42_REG_LIST() \ 474 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 475 SR(DIO_MEM_PWR_CTRL), \ 476 SR(ODM_MEM_PWR_CTRL3), \ 477 SR(MMHUBBUB_MEM_PWR_CNTL), \ 478 SR(DCCG_GATE_DISABLE_CNTL), \ 479 SR(DCCG_GATE_DISABLE_CNTL2), \ 480 SR(DCFCLK_CNTL), \ 481 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 482 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 483 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 484 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 485 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 486 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ 487 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ 488 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ 489 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 490 SR(MICROSECOND_TIME_BASE_DIV), \ 491 SR(MILLISECOND_TIME_BASE_DIV), \ 492 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 493 SR(RBBMIF_TIMEOUT_DIS), \ 494 SR(RBBMIF_TIMEOUT_DIS_2), \ 495 SR(DCHUBBUB_CRC_CTRL), \ 496 SR(DPP_TOP0_DPP_CRC_CTRL), \ 497 SR(DPP_TOP0_DPP_CRC_VAL_R), \ 498 SR(DPP_TOP0_DPP_CRC_VAL_G), \ 499 SR(DPP_TOP0_DPP_CRC_VAL_B), \ 500 SR(MPC_CRC_CTRL), \ 501 SR(MPC_CRC_RESULT_R), \ 502 SR(MPC_CRC_RESULT_G), \ 503 SR(MPC_CRC_RESULT_B), \ 504 SR(MPC_CRC_RESULT_A), \ 505 SR(DOMAIN0_PG_CONFIG), \ 506 SR(DOMAIN1_PG_CONFIG), \ 507 SR(DOMAIN2_PG_CONFIG), \ 508 SR(DOMAIN3_PG_CONFIG), \ 509 SR(DOMAIN16_PG_CONFIG), \ 510 SR(DOMAIN17_PG_CONFIG), \ 511 SR(DOMAIN18_PG_CONFIG), \ 512 SR(DOMAIN19_PG_CONFIG), \ 513 SR(DOMAIN22_PG_CONFIG), \ 514 SR(DOMAIN23_PG_CONFIG), \ 515 SR(DOMAIN24_PG_CONFIG), \ 516 SR(DOMAIN25_PG_CONFIG), \ 517 SR(DOMAIN26_PG_CONFIG), \ 518 SR(DOMAIN0_PG_STATUS), \ 519 SR(DOMAIN1_PG_STATUS), \ 520 SR(DOMAIN2_PG_STATUS), \ 521 SR(DOMAIN3_PG_STATUS), \ 522 SR(DOMAIN16_PG_STATUS), \ 523 SR(DOMAIN17_PG_STATUS), \ 524 SR(DOMAIN18_PG_STATUS), \ 525 SR(DOMAIN19_PG_STATUS), \ 526 SR(DOMAIN22_PG_STATUS), \ 527 SR(DOMAIN23_PG_STATUS), \ 528 SR(DOMAIN24_PG_STATUS), \ 529 SR(DOMAIN25_PG_STATUS), \ 530 SR(DOMAIN26_PG_STATUS), \ 531 SR(DC_IP_REQUEST_CNTL), \ 532 SR(AZALIA_AUDIO_DTO), \ 533 SR(HPO_TOP_HW_CONTROL), \ 534 SR(AZALIA_CONTROLLER_CLOCK_GATING) 535 536 static struct dce_hwseq_registers hwseq_reg; 537 538 #define hwseq_reg_init() \ 539 HWSEQ_DCN42_REG_LIST() 540 541 #define HWSEQ_DCN42_MASK_SH_LIST(mask_sh) \ 542 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 543 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 544 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 545 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 546 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 547 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 548 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 549 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 550 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 551 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 552 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 553 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 554 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 555 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 556 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 557 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 558 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 559 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 560 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 561 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 562 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 563 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 564 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 565 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 566 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 567 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 568 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 569 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 570 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 571 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 572 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 573 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 574 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 575 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 576 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 577 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 578 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 579 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 580 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 581 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 582 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 583 HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 584 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 585 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 586 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 587 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ 588 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 589 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 590 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 591 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ 592 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ 593 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ 594 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 595 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 596 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 597 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 598 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 599 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ 600 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 601 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 602 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 603 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ 610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 613 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 614 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 615 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 616 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ 620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ 621 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 622 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 623 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 624 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 625 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 626 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 627 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ 628 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ 629 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ 630 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ 631 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh),\ 632 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh),\ 633 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh) 634 635 static const struct dce_hwseq_shift hwseq_shift = { 636 HWSEQ_DCN42_MASK_SH_LIST(__SHIFT)}; 637 638 static const struct dce_hwseq_mask hwseq_mask = { 639 HWSEQ_DCN42_MASK_SH_LIST(_MASK)}; 640 641 #define vmid_regs_init(id) \ 642 DCN20_VMID_REG_LIST_RI(id) 643 644 static struct dcn_vmid_registers vmid_regs[16]; 645 646 static const struct dcn20_vmid_shift vmid_shifts = { 647 DCN20_VMID_MASK_SH_LIST(__SHIFT)}; 648 649 static const struct dcn20_vmid_mask vmid_masks = { 650 DCN20_VMID_MASK_SH_LIST(_MASK)}; 651 652 static const struct resource_caps res_cap_dcn42 = { 653 .num_timing_generator = 4, 654 .num_opp = 4, 655 .num_dpp = 4, 656 .num_video_plane = 4, 657 .num_audio = 5, 658 .num_stream_encoder = 5, 659 .num_dig_link_enc = 5, 660 .num_usb4_dpia = 6, 661 .num_hpo_dp_stream_encoder = 4, 662 .num_hpo_dp_link_encoder = 4, 663 .num_pll = 5, 664 .num_dwb = 1, 665 .num_ddc = 5, 666 .num_vmid = 16, 667 .num_mpc_3dlut = 2, 668 .num_dsc = 4, 669 .num_rmcm = 2, 670 }; 671 672 static const struct dc_plane_cap plane_cap = { 673 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 674 .per_pixel_alpha = true, 675 676 .pixel_format_support = { 677 .argb8888 = true, 678 .nv12 = true, 679 .fp16 = true, 680 .p010 = true, 681 .ayuv = false, 682 }, 683 684 .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, 685 686 // 6:1 downscaling ratio: 1000/6 = 166.666 687 .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, 688 689 .min_width = 64, 690 .min_height = 64}; 691 692 static const struct dc_debug_options debug_defaults_drv = { 693 .disable_dmcu = true, 694 .force_abm_enable = false, 695 .clock_trace = true, 696 .disable_pplib_clock_request = false, 697 .disable_dpp_power_gate = true, 698 .disable_hubp_power_gate = true, 699 .disable_optc_power_gate = true, 700 .pipe_split_policy = MPC_SPLIT_AVOID, 701 .force_single_disp_pipe_split = false, 702 .disable_dcc = DCC_ENABLE, 703 .vsr_support = true, 704 .performance_trace = false, 705 .max_downscale_src_width = 4096, /*up to 4K for APU*/ 706 .disable_pplib_wm_range = false, 707 .scl_reset_length10 = true, 708 .sanity_checks = false, 709 .underflow_assert_delay_us = 0xFFFFFFFF, 710 .dwb_fi_phase = -1, // -1 = disable, 711 .dmub_command_table = true, 712 .pstate_enabled = true, 713 .enable_mem_low_power = { 714 .bits = { 715 .vga = false, 716 .i2c = true, 717 .dscl = true, 718 .cm = true, 719 .mpc = true, 720 .optc = true, 721 .vpg = true, 722 }}, 723 .root_clock_optimization = { 724 .bits = { 725 .dpp = true, 726 .dsc = true,/*dscclk and dsc pg*/ 727 .hdmistream = false, 728 .hdmichar = true, 729 .dpstream = true, 730 .symclk32_se = true, 731 .symclk32_le = true, 732 .symclk_fe = true, 733 .physymclk = false, 734 .dpiasymclk = true, 735 } 736 }, 737 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 738 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 739 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ 740 .support_eDP1_5 = true, 741 .use_max_lb = true, 742 .force_disable_subvp = false, 743 .exit_idle_opt_for_cursor_updates = true, 744 .using_dml2 = true, 745 .using_dml21 = true, 746 .enable_single_display_2to1_odm_policy = true, 747 748 // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 749 .enable_double_buffered_dsc_pg_support = true, 750 .enable_dp_dig_pixel_rate_div_policy = 1, 751 .allow_sw_cursor_fallback = false, 752 .psp_disabled_wa = true, 753 .alloc_extra_way_for_cursor = true, 754 .min_prefetch_in_strobe_ns = 60000, // 60us 755 .disable_unbounded_requesting = false, 756 .dcc_meta_propagation_delay_us = 10, 757 .disable_timeout = true, 758 .min_disp_clk_khz = 50000, 759 .static_screen_wait_frames = 2, 760 .disable_z10 = false, 761 .ignore_pg = true, 762 .disable_stutter_for_wm_program = true, 763 .min_deep_sleep_dcfclk_khz = 8000, 764 .replay_skip_crtc_disabled = true, 765 .psr_skip_crtc_disable = true, 766 }; 767 768 static const struct dc_check_config config_defaults = { 769 .enable_legacy_fast_update = false, 770 }; 771 772 static struct dce_aux *dcn42_aux_engine_create( 773 struct dc_context *ctx, 774 uint32_t inst) 775 { 776 struct aux_engine_dce110 *aux_engine = 777 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 778 779 if (!aux_engine) 780 return NULL; 781 782 #undef REG_STRUCT 783 #define REG_STRUCT aux_engine_regs 784 aux_engine_regs_init(0), 785 aux_engine_regs_init(1), 786 aux_engine_regs_init(2), 787 aux_engine_regs_init(3), 788 aux_engine_regs_init(4); 789 790 dce110_aux_engine_construct(aux_engine, ctx, inst, 791 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 792 &aux_engine_regs[inst], 793 &aux_mask, 794 &aux_shift, 795 ctx->dc->caps.extended_aux_timeout_support); 796 797 return &aux_engine->base; 798 } 799 800 #define i2c_inst_regs_init(id) \ 801 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 802 803 static struct dce_i2c_registers i2c_hw_regs[5]; 804 805 static const struct dce_i2c_shift i2c_shifts = { 806 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 807 }; 808 static const struct dce_i2c_mask i2c_masks = { 809 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) 810 }; 811 812 /* ========================================================== */ 813 814 /* 815 * DPIA index | Preferred Encoder | Host Router 816 * 0 | C | 0 817 * 1 | First Available | 0 818 * 2 | D | 1 819 * 3 | First Available | 1 820 * 4 | E | 2 821 * 5 | First Available | 2 822 */ 823 /* ========================================================== */ 824 static const enum engine_id dpia_to_preferred_enc_id_table[] = { 825 ENGINE_ID_DIGC, 826 ENGINE_ID_DIGC, 827 ENGINE_ID_DIGD, 828 ENGINE_ID_DIGD, 829 ENGINE_ID_DIGE, 830 ENGINE_ID_DIGE 831 }; 832 833 static enum engine_id dcn42_get_preferred_eng_id_dpia(unsigned int dpia_index) 834 { 835 return dpia_to_preferred_enc_id_table[dpia_index]; 836 } 837 838 static struct dce_i2c_hw *dcn42_i2c_hw_create( 839 struct dc_context *ctx, 840 uint32_t inst) 841 { 842 struct dce_i2c_hw *dce_i2c_hw = 843 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 844 845 if (!dce_i2c_hw) 846 return NULL; 847 848 #undef REG_STRUCT 849 #define REG_STRUCT i2c_hw_regs 850 i2c_inst_regs_init(1), 851 i2c_inst_regs_init(2), 852 i2c_inst_regs_init(3), 853 i2c_inst_regs_init(4), 854 i2c_inst_regs_init(5); 855 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 856 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 857 858 return dce_i2c_hw; 859 } 860 861 static struct clock_source *dcn42_clock_source_create( 862 struct dc_context *ctx, 863 struct dc_bios *bios, 864 enum clock_source_id id, 865 const struct dce110_clk_src_regs *regs, 866 bool dp_clk_src) 867 { 868 struct dce110_clk_src *clk_src = 869 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 870 871 if (!clk_src) 872 return NULL; 873 874 if (dcn401_clk_src_construct(clk_src, ctx, bios, id, 875 regs, &cs_shift, &cs_mask)) { 876 clk_src->base.dp_clk_src = dp_clk_src; 877 return &clk_src->base; 878 } 879 880 kfree(clk_src); 881 BREAK_TO_DEBUGGER(); 882 return NULL; 883 } 884 885 static struct hubbub *dcn42_hubbub_create(struct dc_context *ctx) 886 { 887 int i; 888 889 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 890 GFP_KERNEL); 891 892 if (!hubbub3) 893 return NULL; 894 895 #undef REG_STRUCT 896 #define REG_STRUCT hubbub_reg 897 hubbub_reg_init(); 898 899 #undef REG_STRUCT 900 #define REG_STRUCT vmid_regs 901 vmid_regs_init(0), 902 vmid_regs_init(1), 903 vmid_regs_init(2), 904 vmid_regs_init(3), 905 vmid_regs_init(4), 906 vmid_regs_init(5), 907 vmid_regs_init(6), 908 vmid_regs_init(7), 909 vmid_regs_init(8), 910 vmid_regs_init(9), 911 vmid_regs_init(10), 912 vmid_regs_init(11), 913 vmid_regs_init(12), 914 vmid_regs_init(13), 915 vmid_regs_init(14), 916 vmid_regs_init(15); 917 918 hubbub42_construct(hubbub3, ctx, 919 &hubbub_reg, 920 &hubbub_shift, 921 &hubbub_mask, 922 DCN42_DEFAULT_DET_SIZE, 923 8, 924 DCN42_CRB_SIZE_KB); 925 for (i = 0; i < res_cap_dcn42.num_vmid; i++) { 926 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 927 928 vmid->ctx = ctx; 929 930 vmid->regs = &vmid_regs[i]; 931 vmid->shifts = &vmid_shifts; 932 vmid->masks = &vmid_masks; 933 } 934 935 return &hubbub3->base; 936 } 937 938 static struct hubp *dcn42_hubp_create( 939 struct dc_context *ctx, 940 uint32_t inst) 941 { 942 struct dcn20_hubp *hubp2 = 943 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 944 945 if (!hubp2) 946 return NULL; 947 948 #undef REG_STRUCT 949 #define REG_STRUCT hubp_regs 950 hubp_regs_init(0), 951 hubp_regs_init(1), 952 hubp_regs_init(2), 953 hubp_regs_init(3); 954 955 if (hubp42_construct(hubp2, ctx, inst, 956 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 957 return &hubp2->base; 958 959 BREAK_TO_DEBUGGER(); 960 kfree(hubp2); 961 return NULL; 962 } 963 static const struct dc_panel_config dcn42_panel_config_defaults = { 964 .psr = { 965 .disable_psr = false, 966 .disallow_psrsu = false, 967 .disallow_replay = false, 968 }, 969 .ilr = { 970 .optimize_edp_link_rate = true, 971 }, 972 }; 973 974 static void dcn42_dpp_destroy(struct dpp **dpp) 975 { 976 kfree(TO_DCN42_DPP(*dpp)); 977 *dpp = NULL; 978 } 979 980 static struct dpp *dcn42_dpp_create( 981 struct dc_context *ctx, 982 uint32_t inst) 983 { 984 struct dcn42_dpp *dpp42 = 985 kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); 986 987 if (!dpp42) 988 return NULL; 989 990 #undef REG_STRUCT 991 #define REG_STRUCT dpp_regs 992 dpp_regs_init(0), 993 dpp_regs_init(1), 994 dpp_regs_init(2), 995 dpp_regs_init(3); 996 997 if (dpp42_construct(dpp42, ctx, inst, 998 &dpp_regs[inst], &tf_shift, &tf_mask)) 999 return &dpp42->base; 1000 1001 BREAK_TO_DEBUGGER(); 1002 kfree(dpp42); 1003 return NULL; 1004 } 1005 1006 static struct mpc *dcn42_mpc_create( 1007 struct dc_context *ctx, 1008 int num_mpcc, 1009 int num_rmu) 1010 { 1011 struct dcn42_mpc *mpc401 = kzalloc(sizeof(struct dcn42_mpc), 1012 GFP_KERNEL); 1013 1014 if (!mpc401) 1015 return NULL; 1016 1017 #undef REG_STRUCT 1018 #define REG_STRUCT mpc_regs 1019 dcn_mpc_regs_init(); 1020 1021 dcn42_mpc_construct(mpc401, ctx, 1022 &mpc_regs, 1023 &mpc_shift, 1024 &mpc_mask, 1025 num_mpcc, 1026 num_rmu); 1027 1028 return &mpc401->base; 1029 } 1030 1031 static struct output_pixel_processor *dcn42_opp_create( 1032 struct dc_context *ctx, uint32_t inst) 1033 { 1034 struct dcn20_opp *opp4 = 1035 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1036 1037 if (!opp4) { 1038 BREAK_TO_DEBUGGER(); 1039 return NULL; 1040 } 1041 1042 #undef REG_STRUCT 1043 #define REG_STRUCT opp_regs 1044 opp_regs_init(0), 1045 opp_regs_init(1), 1046 opp_regs_init(2), 1047 opp_regs_init(3); 1048 dcn20_opp_construct(opp4, ctx, inst, 1049 &opp_regs[inst], &opp_shift, &opp_mask); 1050 return &opp4->base; 1051 } 1052 1053 static struct timing_generator *dcn42_timing_generator_create( 1054 struct dc_context *ctx, 1055 uint32_t instance) 1056 { 1057 struct optc *tgn10 = 1058 kzalloc(sizeof(struct optc), GFP_KERNEL); 1059 1060 if (!tgn10) 1061 return NULL; 1062 #undef REG_STRUCT 1063 #define REG_STRUCT optc_regs 1064 optc_regs_init(0), 1065 optc_regs_init(1), 1066 optc_regs_init(2), 1067 optc_regs_init(3); 1068 tgn10->base.inst = instance; 1069 tgn10->base.ctx = ctx; 1070 1071 tgn10->tg_regs = &optc_regs[instance]; 1072 tgn10->tg_shift = &optc_shift; 1073 tgn10->tg_mask = &optc_mask; 1074 1075 dcn42_timing_generator_init(tgn10); 1076 1077 return &tgn10->base; 1078 } 1079 1080 static const struct encoder_feature_support link_enc_feature = { 1081 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1082 .max_hdmi_pixel_clock = 600000, 1083 .hdmi_ycbcr420_supported = true, 1084 .dp_ycbcr420_supported = true, 1085 .fec_supported = true, 1086 .flags.bits.IS_HBR2_CAPABLE = true, 1087 .flags.bits.IS_HBR3_CAPABLE = true, 1088 .flags.bits.IS_TPS3_CAPABLE = true, 1089 .flags.bits.IS_TPS4_CAPABLE = true}; 1090 1091 static struct link_encoder *dcn42_link_encoder_create( 1092 struct dc_context *ctx, 1093 const struct encoder_init_data *enc_init_data) 1094 { 1095 struct dcn20_link_encoder *enc20 = 1096 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1097 1098 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1099 return NULL; 1100 1101 #undef REG_STRUCT 1102 #define REG_STRUCT link_enc_aux_regs 1103 aux_regs_init(0), 1104 aux_regs_init(1), 1105 aux_regs_init(2), 1106 aux_regs_init(3), 1107 aux_regs_init(4); 1108 #undef REG_STRUCT 1109 #define REG_STRUCT link_enc_hpd_regs 1110 hpd_regs_init(0), 1111 hpd_regs_init(1), 1112 hpd_regs_init(2), 1113 hpd_regs_init(3), 1114 hpd_regs_init(4); 1115 #undef REG_STRUCT 1116 #define REG_STRUCT link_enc_regs 1117 link_regs_init(0, A), 1118 link_regs_init(1, B), 1119 link_regs_init(2, C), 1120 link_regs_init(3, D), 1121 link_regs_init(4, E); 1122 1123 dcn42_link_encoder_construct(enc20, 1124 enc_init_data, 1125 &link_enc_feature, 1126 &link_enc_regs[enc_init_data->transmitter], 1127 &link_enc_aux_regs[enc_init_data->channel - 1], 1128 &link_enc_hpd_regs[enc_init_data->hpd_source], 1129 &le_shift, 1130 &le_mask); 1131 return &enc20->enc10.base; 1132 } 1133 1134 static void read_dce_straps( 1135 struct dc_context *ctx, 1136 struct resource_straps *straps) 1137 { 1138 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1139 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1140 } 1141 1142 static struct audio *dcn42_create_audio( 1143 struct dc_context *ctx, unsigned int inst) 1144 { 1145 1146 #undef REG_STRUCT 1147 #define REG_STRUCT audio_regs 1148 audio_regs_init(0), 1149 audio_regs_init(1), 1150 audio_regs_init(2), 1151 audio_regs_init(3), 1152 audio_regs_init(4); 1153 1154 return dce_audio_create(ctx, inst, 1155 &audio_regs[inst], &audio_shift, &audio_mask); 1156 } 1157 1158 static struct vpg *dcn42_vpg_create( 1159 struct dc_context *ctx, 1160 uint32_t inst) 1161 { 1162 struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1163 1164 if (!vpg4) 1165 return NULL; 1166 1167 #undef REG_STRUCT 1168 #define REG_STRUCT vpg_regs 1169 vpg_regs_init(0), 1170 vpg_regs_init(1), 1171 vpg_regs_init(2), 1172 vpg_regs_init(3), 1173 vpg_regs_init(4), 1174 vpg_regs_init(5), 1175 vpg_regs_init(6), 1176 vpg_regs_init(7), 1177 vpg_regs_init(8), 1178 vpg_regs_init(9); 1179 vpg31_construct(vpg4, ctx, inst, 1180 &vpg_regs[inst], 1181 &vpg_shift, 1182 &vpg_mask); 1183 1184 return &vpg4->base; 1185 } 1186 1187 static struct apg *dcn42_apg_create( 1188 struct dc_context *ctx, 1189 uint32_t inst) 1190 { 1191 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1192 1193 if (!apg31) 1194 return NULL; 1195 1196 #undef REG_STRUCT 1197 #define REG_STRUCT apg_regs 1198 apg_regs_init(0), 1199 apg_regs_init(1), 1200 apg_regs_init(2), 1201 apg_regs_init(3), 1202 apg_regs_init(4), 1203 apg_regs_init(5), 1204 apg_regs_init(6), 1205 apg_regs_init(7), 1206 apg_regs_init(8), 1207 apg_regs_init(9); 1208 1209 apg31_construct(apg31, ctx, inst, 1210 &apg_regs[inst], 1211 &apg_shift, 1212 &apg_mask); 1213 1214 return &apg31->base; 1215 } 1216 1217 static struct stream_encoder *dcn42_stream_encoder_create( 1218 enum engine_id eng_id, 1219 struct dc_context *ctx) 1220 { 1221 struct dcn10_stream_encoder *enc1; 1222 struct vpg *vpg; 1223 struct apg *apg; 1224 1225 uint32_t vpg_inst; 1226 uint32_t apg_inst; 1227 1228 /* Mapping of VPG, DME register blocks to DIO block instance */ 1229 if (eng_id <= ENGINE_ID_DIGE) { 1230 vpg_inst = eng_id; 1231 apg_inst = eng_id; 1232 } else 1233 return NULL; 1234 1235 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1236 vpg = dcn42_vpg_create(ctx, vpg_inst); 1237 apg = dcn42_apg_create(ctx, apg_inst); 1238 1239 if (!enc1 || !vpg || !apg) { 1240 kfree(enc1); 1241 kfree(vpg); 1242 kfree(apg); 1243 return NULL; 1244 } 1245 #undef REG_STRUCT 1246 #define REG_STRUCT stream_enc_regs 1247 stream_enc_regs_init(0), 1248 stream_enc_regs_init(1), 1249 stream_enc_regs_init(2), 1250 stream_enc_regs_init(3), 1251 stream_enc_regs_init(4); 1252 1253 dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1254 eng_id, vpg, apg, 1255 &stream_enc_regs[eng_id], 1256 &se_shift, &se_mask); 1257 return &enc1->base; 1258 } 1259 1260 static struct hpo_dp_stream_encoder *dcn42_hpo_dp_stream_encoder_create( 1261 enum engine_id eng_id, 1262 struct dc_context *ctx) 1263 { 1264 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1265 struct vpg *vpg; 1266 struct apg *apg; 1267 uint32_t hpo_dp_inst; 1268 uint32_t vpg_inst; 1269 uint32_t apg_inst; 1270 1271 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1272 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1273 1274 /* Mapping of VPG register blocks to HPO DP block instance: 1275 * VPG[5] -> HPO_DP[0] 1276 * VPG[6] -> HPO_DP[1] 1277 * VPG[7] -> HPO_DP[2] 1278 * VPG[8] -> HPO_DP[3] 1279 */ 1280 vpg_inst = hpo_dp_inst + 5; 1281 1282 /* Mapping of APG register blocks to HPO DP block instance: 1283 * APG[6] -> HPO_DP[0] 1284 * APG[7] -> HPO_DP[1] 1285 * APG[8] -> HPO_DP[2] 1286 * APG[9] -> HPO_DP[3] 1287 */ 1288 apg_inst = hpo_dp_inst + 5; 1289 1290 /* allocate HPO stream encoder and create VPG sub-block */ 1291 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1292 vpg = dcn42_vpg_create(ctx, vpg_inst); 1293 apg = dcn42_apg_create(ctx, apg_inst); 1294 1295 if (!hpo_dp_enc31 || !vpg || !apg) { 1296 kfree(hpo_dp_enc31); 1297 kfree(vpg); 1298 kfree(apg); 1299 return NULL; 1300 } 1301 1302 #undef REG_STRUCT 1303 #define REG_STRUCT hpo_dp_stream_enc_regs 1304 hpo_dp_stream_encoder_reg_init(0), 1305 hpo_dp_stream_encoder_reg_init(1), 1306 hpo_dp_stream_encoder_reg_init(2), 1307 hpo_dp_stream_encoder_reg_init(3); 1308 1309 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1310 hpo_dp_inst, eng_id, vpg, apg, 1311 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1312 &hpo_dp_se_shift, &hpo_dp_se_mask); 1313 1314 return &hpo_dp_enc31->base; 1315 } 1316 1317 static struct hpo_dp_link_encoder *dcn42_hpo_dp_link_encoder_create( 1318 uint8_t inst, 1319 struct dc_context *ctx) 1320 { 1321 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1322 1323 /* allocate HPO link encoder */ 1324 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1325 if (!hpo_dp_enc31) 1326 return NULL; /* out of memory */ 1327 1328 #undef REG_STRUCT 1329 #define REG_STRUCT hpo_dp_link_enc_regs 1330 hpo_dp_link_encoder_reg_init(0), 1331 hpo_dp_link_encoder_reg_init(1), 1332 hpo_dp_link_encoder_reg_init(2), 1333 hpo_dp_link_encoder_reg_init(3); 1334 1335 hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, 1336 &hpo_dp_link_enc_regs[inst], 1337 &hpo_dp_le_shift, &hpo_dp_le_mask); 1338 1339 return &hpo_dp_enc31->base; 1340 } 1341 1342 static struct dce_hwseq *dcn42_hwseq_create( 1343 struct dc_context *ctx) 1344 { 1345 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1346 1347 #undef REG_STRUCT 1348 #define REG_STRUCT hwseq_reg 1349 hwseq_reg_init(); 1350 1351 if (hws) { 1352 hws->ctx = ctx; 1353 hws->regs = &hwseq_reg; 1354 hws->shifts = &hwseq_shift; 1355 hws->masks = &hwseq_mask; 1356 } 1357 1358 return hws; 1359 } 1360 1361 static const struct resource_create_funcs res_create_funcs = { 1362 .read_dce_straps = read_dce_straps, 1363 .create_audio = dcn42_create_audio, 1364 .create_stream_encoder = dcn42_stream_encoder_create, 1365 .create_hpo_dp_stream_encoder = dcn42_hpo_dp_stream_encoder_create, 1366 .create_hpo_dp_link_encoder = dcn42_hpo_dp_link_encoder_create, 1367 .create_hwseq = dcn42_hwseq_create, 1368 }; 1369 1370 static void dcn42_dsc_destroy(struct display_stream_compressor **dsc) 1371 { 1372 kfree(container_of(*dsc, struct dcn401_dsc, base)); 1373 *dsc = NULL; 1374 } 1375 1376 static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) 1377 { 1378 unsigned int i; 1379 1380 for (i = 0; i < pool->base.stream_enc_count; i++) { 1381 if (pool->base.stream_enc[i] != NULL) { 1382 if (pool->base.stream_enc[i]->vpg != NULL) { 1383 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1384 pool->base.stream_enc[i]->vpg = NULL; 1385 } 1386 if (pool->base.stream_enc[i]->apg != NULL) { 1387 kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); 1388 pool->base.stream_enc[i]->apg = NULL; 1389 } 1390 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1391 pool->base.stream_enc[i] = NULL; 1392 } 1393 } 1394 1395 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1396 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1397 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1398 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1399 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1400 } 1401 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1402 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1403 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1404 } 1405 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1406 pool->base.hpo_dp_stream_enc[i] = NULL; 1407 } 1408 } 1409 1410 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1411 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1412 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1413 pool->base.hpo_dp_link_enc[i] = NULL; 1414 } 1415 } 1416 1417 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1418 if (pool->base.dscs[i] != NULL) 1419 dcn42_dsc_destroy(&pool->base.dscs[i]); 1420 } 1421 1422 if (pool->base.mpc != NULL) { 1423 kfree(TO_DCN20_MPC(pool->base.mpc)); 1424 pool->base.mpc = NULL; 1425 } 1426 if (pool->base.hubbub != NULL) { 1427 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1428 pool->base.hubbub = NULL; 1429 } 1430 for (i = 0; i < pool->base.pipe_count; i++) { 1431 if (pool->base.dpps[i] != NULL) 1432 dcn42_dpp_destroy(&pool->base.dpps[i]); 1433 1434 if (pool->base.ipps[i] != NULL) 1435 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1436 1437 if (pool->base.hubps[i] != NULL) { 1438 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1439 pool->base.hubps[i] = NULL; 1440 } 1441 1442 if (pool->base.irqs != NULL) 1443 dal_irq_service_destroy(&pool->base.irqs); 1444 } 1445 1446 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1447 if (pool->base.engines[i] != NULL) 1448 dce110_engine_destroy(&pool->base.engines[i]); 1449 if (pool->base.hw_i2cs[i] != NULL) { 1450 kfree(pool->base.hw_i2cs[i]); 1451 pool->base.hw_i2cs[i] = NULL; 1452 } 1453 if (pool->base.sw_i2cs[i] != NULL) { 1454 kfree(pool->base.sw_i2cs[i]); 1455 pool->base.sw_i2cs[i] = NULL; 1456 } 1457 } 1458 1459 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1460 if (pool->base.opps[i] != NULL) 1461 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1462 } 1463 1464 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1465 if (pool->base.timing_generators[i] != NULL) { 1466 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1467 pool->base.timing_generators[i] = NULL; 1468 } 1469 } 1470 1471 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1472 if (pool->base.dwbc[i] != NULL) { 1473 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1474 pool->base.dwbc[i] = NULL; 1475 } 1476 if (pool->base.mcif_wb[i] != NULL) { 1477 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1478 pool->base.mcif_wb[i] = NULL; 1479 } 1480 } 1481 1482 for (i = 0; i < pool->base.audio_count; i++) { 1483 if (pool->base.audios[i]) 1484 dce_aud_destroy(&pool->base.audios[i]); 1485 } 1486 1487 for (i = 0; i < pool->base.clk_src_count; i++) { 1488 if (pool->base.clock_sources[i] != NULL) { 1489 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1490 pool->base.clock_sources[i] = NULL; 1491 } 1492 } 1493 1494 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1495 if (pool->base.mpc_lut[i] != NULL) { 1496 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1497 pool->base.mpc_lut[i] = NULL; 1498 } 1499 if (pool->base.mpc_shaper[i] != NULL) { 1500 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1501 pool->base.mpc_shaper[i] = NULL; 1502 } 1503 } 1504 1505 if (pool->base.dp_clock_source != NULL) { 1506 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1507 pool->base.dp_clock_source = NULL; 1508 } 1509 1510 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1511 if (pool->base.multiple_abms[i] != NULL) 1512 dce_abm_destroy(&pool->base.multiple_abms[i]); 1513 } 1514 1515 if (pool->base.psr != NULL) 1516 dmub_psr_destroy(&pool->base.psr); 1517 1518 if (pool->base.pg_cntl != NULL) 1519 dcn_pg_cntl_destroy(&pool->base.pg_cntl); 1520 if (pool->base.dccg != NULL) 1521 dcn_dccg_destroy(&pool->base.dccg); 1522 1523 if (pool->base.oem_device != NULL) { 1524 struct dc *dc = pool->base.oem_device->ctx->dc; 1525 1526 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1527 } 1528 } 1529 1530 static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) 1531 { 1532 const struct dc_stream_state *stream = pipe_ctx->stream; 1533 struct dc_link *link = stream->link; 1534 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 1535 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; 1536 1537 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1538 1539 if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) 1540 pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; 1541 1542 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 1543 link_enc = link_enc_cfg_get_link_enc(link); 1544 if (link_enc) 1545 pixel_clk_params->encoder_object_id = link_enc->id; 1546 1547 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1548 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1549 /* TODO: un-hardcode*/ 1550 1551 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ 1552 1553 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1554 LINK_RATE_REF_FREQ_IN_KHZ; 1555 pixel_clk_params->flags.ENABLE_SS = 0; 1556 pixel_clk_params->color_depth = 1557 stream->timing.display_color_depth; 1558 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1559 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1560 1561 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1562 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1563 1564 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1565 pixel_clk_params->requested_pix_clk_100hz *= 2; 1566 if (dc_is_tmds_signal(stream->signal) && 1567 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1568 pixel_clk_params->requested_pix_clk_100hz /= 2; 1569 1570 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1571 pipe_ctx->clock_source, 1572 &pipe_ctx->stream_res.pix_clk_params, 1573 &pipe_ctx->pll_settings); 1574 1575 pixel_clk_params->dio_se_pix_per_cycle = 1; 1576 if (dc_is_tmds_signal(stream->signal) && 1577 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1578 pixel_clk_params->dio_se_pix_per_cycle = 2; 1579 } else if (dc_is_dp_signal(stream->signal)) { 1580 /* round up to nearest power of 2, or max at 8 pixels per cycle */ 1581 if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { 1582 pixel_clk_params->dio_se_pix_per_cycle = 8; 1583 } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { 1584 pixel_clk_params->dio_se_pix_per_cycle = 4; 1585 } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { 1586 pixel_clk_params->dio_se_pix_per_cycle = 2; 1587 } else { 1588 pixel_clk_params->dio_se_pix_per_cycle = 1; 1589 } 1590 } 1591 } 1592 1593 static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1594 { 1595 int i; 1596 uint32_t dwb_count = pool->res_cap->num_dwb; 1597 1598 for (i = 0; i < dwb_count; i++) { 1599 struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), 1600 GFP_KERNEL); 1601 1602 if (!dwbc42) { 1603 dm_error("DC: failed to create dwbc42!\n"); 1604 return false; 1605 } 1606 1607 #undef REG_STRUCT 1608 #define REG_STRUCT dwbc401_regs 1609 dwbc_regs_dcn401_init(0); 1610 1611 dcn30_dwbc_construct(dwbc42, ctx, 1612 &dwbc401_regs[i], 1613 &dwbc401_shift, 1614 &dwbc401_mask, 1615 i); 1616 1617 pool->dwbc[i] = &dwbc42->base; 1618 } 1619 return true; 1620 } 1621 1622 static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, 1623 struct dc_context *ctx) 1624 { 1625 dcn42_mmhubbub_set_fgcg( 1626 mcif_wb30, 1627 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); 1628 } 1629 1630 static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1631 { 1632 int i; 1633 uint32_t pipe_count = pool->res_cap->num_dwb; 1634 1635 for (i = 0; i < pipe_count; i++) { 1636 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1637 GFP_KERNEL); 1638 1639 if (!mcif_wb30) { 1640 dm_error("DC: failed to create mcif_wb30!\n"); 1641 return false; 1642 } 1643 1644 #undef REG_STRUCT 1645 #define REG_STRUCT mcif_wb35_regs 1646 mcif_wb_regs_dcn3_init(0); 1647 1648 dcn35_mmhubbub_construct(mcif_wb30, ctx, 1649 &mcif_wb35_regs[i], 1650 &mcif_wb35_shift, 1651 &mcif_wb35_mask, 1652 i); 1653 1654 dcn42_mmhubbub_init(mcif_wb30, ctx); 1655 1656 pool->mcif_wb[i] = &mcif_wb30->base; 1657 } 1658 return true; 1659 } 1660 1661 static struct display_stream_compressor *dcn42_dsc_create( 1662 struct dc_context *ctx, uint32_t inst) 1663 { 1664 struct dcn401_dsc *dsc = 1665 kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); 1666 1667 if (!dsc) { 1668 BREAK_TO_DEBUGGER(); 1669 return NULL; 1670 } 1671 1672 #undef REG_STRUCT 1673 #define REG_STRUCT dsc_regs 1674 dsc_regs_init(0), 1675 dsc_regs_init(1), 1676 dsc_regs_init(2), 1677 dsc_regs_init(3); 1678 1679 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1680 dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); 1681 1682 dsc->max_image_width = 5760; 1683 1684 return &dsc->base; 1685 } 1686 1687 static void dcn42_destroy_resource_pool(struct resource_pool **pool) 1688 { 1689 struct dcn42_resource_pool *dcn42_pool = TO_DCN42_RES_POOL(*pool); 1690 1691 dcn42_resource_destruct(dcn42_pool); 1692 kfree(dcn42_pool); 1693 *pool = NULL; 1694 } 1695 1696 static struct dc_cap_funcs cap_funcs = { 1697 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; 1698 1699 static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 1700 { 1701 (void)bw_params; 1702 dc_assert_fp_enabled(); 1703 1704 if (dc->current_state && dc->current_state->bw_ctx.dml2) 1705 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); 1706 } 1707 1708 static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1709 { 1710 DC_FP_START(); 1711 dcn42_update_bw_bounding_box_fpu(dc, bw_params); 1712 DC_FP_END(); 1713 } 1714 enum dc_status dcn42_validate_bandwidth(struct dc *dc, 1715 struct dc_state *context, 1716 enum dc_validate_mode validate_mode) 1717 { 1718 bool out = false; 1719 1720 DC_FP_START(); 1721 1722 out = dml2_validate(dc, context, context->bw_ctx.dml2, 1723 validate_mode); 1724 1725 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { 1726 /*not required for mode enumeration*/ 1727 dcn42_decide_zstate_support(dc, context); 1728 } 1729 1730 DC_FP_END(); 1731 1732 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1733 } 1734 void dcn42_prepare_mcache_programming(struct dc *dc, 1735 struct dc_state *context) 1736 { 1737 if (dc->debug.using_dml21) { 1738 DC_FP_START(); 1739 dml2_prepare_mcache_programming(dc, context, 1740 context->power_source == DC_POWER_SOURCE_DC ? 1741 context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); 1742 DC_FP_END(); 1743 } 1744 } 1745 /* Create a minimal link encoder object not associated with a particular 1746 * physical connector. 1747 * resource_funcs.link_enc_create_minimal 1748 */ 1749 static struct link_encoder *dcn42_link_enc_create_minimal( 1750 struct dc_context *ctx, enum engine_id eng_id) 1751 { 1752 struct dcn20_link_encoder *enc20; 1753 1754 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1755 return NULL; 1756 1757 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1758 if (!enc20) 1759 return NULL; 1760 1761 dcn31_link_encoder_construct_minimal( 1762 enc20, 1763 ctx, 1764 &link_enc_feature, 1765 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1766 eng_id); 1767 1768 return &enc20->enc10.base; 1769 } 1770 static void dcn42_get_panel_config_defaults(struct dc_panel_config *panel_config) 1771 { 1772 *panel_config = dcn42_panel_config_defaults; 1773 } 1774 static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc, 1775 struct dc_state *state, 1776 const struct dc_stream_state *stream) 1777 { 1778 (void)state; 1779 (void)stream; 1780 return dc->caps.max_cursor_size; 1781 } 1782 static struct resource_funcs dcn42_res_pool_funcs = { 1783 .destroy = dcn42_destroy_resource_pool, 1784 .link_enc_create = dcn42_link_encoder_create, 1785 .link_enc_create_minimal = dcn42_link_enc_create_minimal, 1786 .link_encs_assign = link_enc_cfg_link_encs_assign, 1787 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1788 .panel_cntl_create = dcn32_panel_cntl_create, 1789 .validate_bandwidth = dcn42_validate_bandwidth, 1790 .calculate_wm_and_dlg = NULL, 1791 .populate_dml_pipes = NULL, 1792 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, 1793 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, 1794 .release_pipe = dcn20_release_pipe, 1795 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1796 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1797 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1798 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1799 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1800 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1801 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1802 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1803 .update_bw_bounding_box = dcn42_update_bw_bounding_box, 1804 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, 1805 .get_panel_config_defaults = dcn42_get_panel_config_defaults, 1806 .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, 1807 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1808 .add_phantom_pipes = dcn32_add_phantom_pipes, 1809 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, 1810 .prepare_mcache_programming = dcn42_prepare_mcache_programming, 1811 .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, 1812 .get_power_profile = dcn401_get_power_profile, 1813 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, 1814 .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, 1815 .get_default_tiling_info = dcn10_get_default_tiling_info 1816 }; 1817 1818 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1819 { 1820 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1821 1822 if (value == 0 && ctx->dce_environment == DCE_ENV_DIAG) 1823 value = 0xF; 1824 /* DCN401 support max 4 pipes */ 1825 value = value & 0xf; 1826 return value; 1827 } 1828 1829 static bool dcn42_resource_construct( 1830 uint8_t num_virtual_links, 1831 struct dc *dc, 1832 struct dcn42_resource_pool *pool) 1833 { 1834 int i, j; 1835 struct dc_context *ctx = dc->ctx; 1836 struct irq_service_init_data init_data; 1837 uint32_t pipe_fuses; 1838 uint32_t num_pipes; 1839 1840 #undef REG_STRUCT 1841 #define REG_STRUCT bios_regs 1842 bios_regs_init(); 1843 1844 #undef REG_STRUCT 1845 #define REG_STRUCT clk_src_regs 1846 clk_src_regs_init(0, A), 1847 clk_src_regs_init(1, B), 1848 clk_src_regs_init(2, C), 1849 clk_src_regs_init(3, D), 1850 clk_src_regs_init(4, E); 1851 1852 #undef REG_STRUCT 1853 #define REG_STRUCT abm_regs 1854 abm_regs_init(0), 1855 abm_regs_init(1), 1856 abm_regs_init(2), 1857 abm_regs_init(3); 1858 #undef REG_STRUCT 1859 #define REG_STRUCT dccg_regs 1860 dccg_regs_init(); 1861 1862 ctx->dc_bios->regs = &bios_regs; 1863 1864 pool->base.res_cap = &res_cap_dcn42; 1865 1866 /* max number of pipes for ASIC before checking for pipe fuses */ 1867 num_pipes = pool->base.res_cap->num_dpp; 1868 pipe_fuses = read_pipe_fuses(ctx); 1869 1870 for (i = 0; i < pool->base.res_cap->num_dpp; i++) 1871 if (pipe_fuses & 1 << i) 1872 num_pipes--; 1873 1874 if (pipe_fuses & 1) 1875 ASSERT(0); // Unexpected - Pipe 0 should always be fully functional! 1876 1877 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 1878 ASSERT(0); // Entire DCN is harvested! 1879 1880 pool->base.funcs = &dcn42_res_pool_funcs; 1881 1882 /************************************************* 1883 * Resource + asic cap harcoding * 1884 *************************************************/ 1885 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; 1886 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1887 pool->base.pipe_count = num_pipes; 1888 pool->base.mpcc_count = num_pipes; 1889 dc->caps.ips_v2_support = true; 1890 dc->caps.max_downscale_ratio = 600; 1891 dc->caps.i2c_speed_in_khz = 100; 1892 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1893 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1894 dc->caps.max_cursor_size = 64; 1895 dc->caps.max_buffered_cursor_size = 64; 1896 dc->caps.cursor_not_scaled = true; 1897 dc->caps.min_horizontal_blanking_period = 80; 1898 dc->caps.dmdata_alloc_size = 2048; 1899 dc->caps.mall_size_per_mem_channel = 4; 1900 /* total size = mall per channel * num channels * 1024 * 1024 */ 1901 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1902 dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1903 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1904 dc->caps.cache_line_size = 64; 1905 dc->caps.cache_num_ways = 16; 1906 1907 /* Calculate the available MALL space */ 1908 dc->caps.max_cab_allocation_bytes = 1909 dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * 1910 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1911 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1912 1913 dc->caps.subvp_fw_processing_delay_us = 15; 1914 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1915 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1916 dc->caps.subvp_swath_height_margin_lines = 16; 1917 dc->caps.subvp_pstate_allow_width_us = 20; 1918 dc->caps.subvp_vertical_int_margin_us = 30; 1919 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1920 1921 dc->caps.max_slave_planes = 2; 1922 dc->caps.max_slave_yuv_planes = 2; 1923 dc->caps.max_slave_rgb_planes = 2; 1924 dc->caps.post_blend_color_processing = true; 1925 dc->caps.force_dp_tps4_for_cp2520 = true; 1926 if (dc->config.forceHBR2CP2520) 1927 dc->caps.force_dp_tps4_for_cp2520 = false; 1928 dc->caps.dp_hdmi21_pcon_support = true; 1929 dc->caps.dp_hpo = true; 1930 dc->caps.edp_dsc_support = true; 1931 dc->caps.extended_aux_timeout_support = true; 1932 dc->caps.dmcub_support = true; 1933 dc->caps.is_apu = true; 1934 dc->caps.seamless_odm = true; 1935 dc->caps.zstate_support = true; 1936 dc->caps.ips_support = true; 1937 dc->caps.max_v_total = (1 << 15) - 1; 1938 dc->caps.vtotal_limited_by_fp2 = true; 1939 1940 dc->caps.seamless_odm = true; 1941 dc->caps.zstate_support = true; 1942 dc->caps.ips_support = true; 1943 dc->caps.max_v_total = (1 << 15) - 1; 1944 dc->caps.vtotal_limited_by_fp2 = true; 1945 1946 /* Color pipeline capabilities */ 1947 dc->caps.color.dpp.dcn_arch = 1; 1948 dc->caps.color.dpp.input_lut_shared = 0; 1949 dc->caps.color.dpp.icsc = 1; 1950 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1951 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1952 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1953 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1954 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1955 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1956 dc->caps.color.dpp.post_csc = 1; 1957 dc->caps.color.dpp.gamma_corr = 1; 1958 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1959 1960 dc->caps.color.dpp.hw_3d_lut = 0; 1961 dc->caps.color.dpp.ogam_ram = 0; 1962 // no OGAM ROM on DCN2 and later ASICs 1963 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1964 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1965 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1966 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1967 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1968 dc->caps.color.dpp.ocsc = 0; 1969 1970 dc->caps.color.mpc.gamut_remap = 1; 1971 //configurable to be before or after BLND in MPCC 1972 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; 1973 dc->caps.color.mpc.num_rmcm_3dluts = 2; 1974 dc->caps.color.mpc.ogam_ram = 1; 1975 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1976 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1977 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1978 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1979 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1980 dc->caps.color.mpc.ocsc = 1; 1981 dc->caps.color.mpc.preblend = true; 1982 dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; 1983 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; 1984 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; 1985 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; 1986 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; 1987 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; 1988 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; 1989 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; 1990 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; 1991 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; 1992 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; 1993 dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; 1994 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; 1995 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; 1996 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; 1997 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; 1998 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; 1999 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; 2000 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; 2001 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; 2002 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; 2003 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; 2004 2005 dc->caps.num_of_host_routers = 3; 2006 dc->caps.num_of_dpias_per_host_router = 2; 2007 2008 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 2009 * to provide some margin. 2010 * It's expected for furture ASIC to have equal or higher value, in order to 2011 * have determinstic power improvement from generate to genration. 2012 * (i.e., we should not expect new ASIC generation with lower vmin rate) 2013 */ 2014 dc->caps.max_disp_clock_khz_at_vmin = 650000; 2015 dc->config.use_spl = true; 2016 dc->config.prefer_easf = true; 2017 2018 dc->config.dcn_sharpness_range.sdr_rgb_min = 0; 2019 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; 2020 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; 2021 dc->config.dcn_sharpness_range.sdr_yuv_min = 0; 2022 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; 2023 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; 2024 dc->config.dcn_sharpness_range.hdr_rgb_min = 0; 2025 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; 2026 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; 2027 2028 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; 2029 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; 2030 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; 2031 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; 2032 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; 2033 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; 2034 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; 2035 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; 2036 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; 2037 2038 dc->config.use_pipe_ctx_sync_logic = true; 2039 dc->config.dc_mode_clk_limit_support = false; 2040 dc->config.enable_windowed_mpo_odm = true; 2041 /* Use psp mailbox to enable assr */ 2042 dc->config.use_assr_psp_message = true; 2043 /* dcn42 and afterward always support external panel replay */ 2044 dc->config.frame_update_cmd_version2 = true; 2045 2046 /* read VBIOS LTTPR caps */ 2047 { 2048 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2049 enum bp_result bp_query_result; 2050 uint8_t is_vbios_lttpr_enable = 0; 2051 2052 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2053 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2054 } 2055 2056 dc->caps.vbios_lttpr_aware = true; 2057 } 2058 dc->check_config = config_defaults; 2059 2060 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2061 dc->debug = debug_defaults_drv; 2062 2063 /*HW default is to have all the FGCG enabled, SW no need to program them*/ 2064 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; 2065 // Init the vm_helper 2066 if (dc->vm_helper) 2067 vm_helper_init(dc->vm_helper, 16); 2068 2069 /************************************************* 2070 * Create resources * 2071 *************************************************/ 2072 2073 /* Clock Sources for Pixel Clock*/ 2074 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = 2075 dcn42_clock_source_create(ctx, ctx->dc_bios, 2076 CLOCK_SOURCE_COMBO_PHY_PLL0, 2077 &clk_src_regs[0], false); 2078 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = 2079 dcn42_clock_source_create(ctx, ctx->dc_bios, 2080 CLOCK_SOURCE_COMBO_PHY_PLL1, 2081 &clk_src_regs[1], false); 2082 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = 2083 dcn42_clock_source_create(ctx, ctx->dc_bios, 2084 CLOCK_SOURCE_COMBO_PHY_PLL2, 2085 &clk_src_regs[2], false); 2086 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] = 2087 dcn42_clock_source_create(ctx, ctx->dc_bios, 2088 CLOCK_SOURCE_COMBO_PHY_PLL3, 2089 &clk_src_regs[3], false); 2090 pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = 2091 dcn42_clock_source_create(ctx, ctx->dc_bios, 2092 CLOCK_SOURCE_COMBO_PHY_PLL4, 2093 &clk_src_regs[4], false); 2094 2095 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; 2096 2097 /* todo: not reuse phy_pll registers */ 2098 pool->base.dp_clock_source = 2099 dcn42_clock_source_create(ctx, ctx->dc_bios, 2100 CLOCK_SOURCE_ID_DP_DTO, 2101 &clk_src_regs[0], true); 2102 2103 for (i = 0; i < pool->base.clk_src_count; i++) { 2104 if (pool->base.clock_sources[i] == NULL) { 2105 dm_error("DC: failed to create clock sources!\n"); 2106 BREAK_TO_DEBUGGER(); 2107 goto create_fail; 2108 } 2109 } 2110 2111 /* DCCG */ 2112 pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2113 if (pool->base.dccg == NULL) { 2114 dm_error("DC: failed to create dccg!\n"); 2115 BREAK_TO_DEBUGGER(); 2116 goto create_fail; 2117 } 2118 2119 #undef REG_STRUCT 2120 #define REG_STRUCT pg_cntl_regs 2121 pg_cntl_dcn42_regs_init(); 2122 2123 pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); 2124 if (pool->base.pg_cntl == NULL) { 2125 dm_error("DC: failed to create power gate control!\n"); 2126 BREAK_TO_DEBUGGER(); 2127 goto create_fail; 2128 } 2129 /* IRQ Service */ 2130 init_data.ctx = dc->ctx; 2131 pool->base.irqs = dal_irq_service_dcn42_create(&init_data); 2132 if (!pool->base.irqs) 2133 goto create_fail; 2134 2135 /* HUBBUB */ 2136 pool->base.hubbub = dcn42_hubbub_create(ctx); 2137 if (pool->base.hubbub == NULL) { 2138 BREAK_TO_DEBUGGER(); 2139 dm_error("DC: failed to create hubbub!\n"); 2140 goto create_fail; 2141 } 2142 2143 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2144 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2145 /* if pipe is disabled, skip instance of HW pipe, 2146 * i.e, skip ASIC register instance 2147 */ 2148 if (pipe_fuses & 1 << i) 2149 continue; 2150 2151 pool->base.hubps[j] = dcn42_hubp_create(ctx, i); 2152 if (pool->base.hubps[j] == NULL) { 2153 BREAK_TO_DEBUGGER(); 2154 dm_error( 2155 "DC: failed to create hubps!\n"); 2156 goto create_fail; 2157 } 2158 2159 pool->base.dpps[j] = dcn42_dpp_create(ctx, i); 2160 if (pool->base.dpps[j] == NULL) { 2161 BREAK_TO_DEBUGGER(); 2162 dm_error( 2163 "DC: failed to create dpps!\n"); 2164 goto create_fail; 2165 } 2166 2167 pool->base.opps[j] = dcn42_opp_create(ctx, i); 2168 if (pool->base.opps[j] == NULL) { 2169 BREAK_TO_DEBUGGER(); 2170 dm_error( 2171 "DC: failed to create output pixel processor!\n"); 2172 goto create_fail; 2173 } 2174 2175 pool->base.timing_generators[j] = dcn42_timing_generator_create( 2176 ctx, i); 2177 if (pool->base.timing_generators[j] == NULL) { 2178 BREAK_TO_DEBUGGER(); 2179 dm_error("DC: failed to create tg!\n"); 2180 goto create_fail; 2181 } 2182 2183 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2184 &abm_regs[i], 2185 &abm_shift, 2186 &abm_mask); 2187 if (pool->base.multiple_abms[j] == NULL) { 2188 dm_error("DC: failed to create abm for pipe %d!\n", i); 2189 BREAK_TO_DEBUGGER(); 2190 goto create_fail; 2191 } 2192 2193 /* index for resource pool arrays for next valid pipe */ 2194 j++; 2195 } 2196 2197 /* PSR */ 2198 pool->base.psr = dmub_psr_create(ctx); 2199 if (pool->base.psr == NULL) { 2200 dm_error("DC: failed to create psr obj!\n"); 2201 BREAK_TO_DEBUGGER(); 2202 goto create_fail; 2203 } 2204 2205 /* Replay */ 2206 pool->base.replay = dmub_replay_create(ctx); 2207 if (pool->base.replay == NULL) { 2208 dm_error("DC: failed to create replay obj!\n"); 2209 BREAK_TO_DEBUGGER(); 2210 goto create_fail; 2211 } 2212 2213 /* MPCCs */ 2214 pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator, 2215 pool->base.res_cap->num_mpc_3dlut); 2216 if (pool->base.mpc == NULL) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error("DC: failed to create mpc!\n"); 2219 goto create_fail; 2220 } 2221 2222 /* DSCs */ 2223 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2224 pool->base.dscs[i] = dcn42_dsc_create(ctx, i); 2225 if (pool->base.dscs[i] == NULL) { 2226 BREAK_TO_DEBUGGER(); 2227 dm_error("DC: failed to create display stream compressor %d!\n", i); 2228 goto create_fail; 2229 } 2230 } 2231 2232 /* DWB */ 2233 if (!dcn42_dwbc_create(ctx, &pool->base)) { 2234 BREAK_TO_DEBUGGER(); 2235 dm_error("DC: failed to create dwbc!\n"); 2236 goto create_fail; 2237 } 2238 2239 /* MMHUBBUB */ 2240 if (!dcn42_mmhubbub_create(ctx, &pool->base)) { 2241 BREAK_TO_DEBUGGER(); 2242 dm_error("DC: failed to create mcif_wb!\n"); 2243 goto create_fail; 2244 } 2245 2246 /* AUX and I2C */ 2247 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2248 pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); 2249 2250 if (pool->base.engines[i] == NULL) { 2251 BREAK_TO_DEBUGGER(); 2252 dm_error( 2253 "DC:failed to create aux engine!!\n"); 2254 goto create_fail; 2255 } 2256 pool->base.hw_i2cs[i] = dcn42_i2c_hw_create(ctx, i); 2257 if (pool->base.hw_i2cs[i] == NULL) { 2258 BREAK_TO_DEBUGGER(); 2259 dm_error( 2260 "DC:failed to create hw i2c!!\n"); 2261 goto create_fail; 2262 } 2263 pool->base.sw_i2cs[i] = NULL; 2264 } 2265 /* DCN4.2 has 6 DPIA */ 2266 pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; 2267 if (dc->debug.dpia_debug.bits.disable_dpia) 2268 pool->base.usb4_dpia_count = 0; 2269 2270 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2271 if (!resource_construct(num_virtual_links, dc, &pool->base, 2272 &res_create_funcs)) 2273 goto create_fail; 2274 2275 /* HW Sequencer init functions and Plane caps */ 2276 dcn42_hw_sequencer_init_functions(dc); 2277 2278 dc->caps.max_planes = pool->base.pipe_count; 2279 2280 for (i = 0; i < dc->caps.max_planes; ++i) 2281 dc->caps.planes[i] = plane_cap; 2282 2283 dc->caps.max_odm_combine_factor = 4; 2284 2285 dc->cap_funcs = cap_funcs; 2286 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 2287 2288 // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided 2289 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2290 dc->config.sdpif_request_limit_words_per_umc = 16; 2291 2292 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2293 /*this will use real soc clock table*/ 2294 dc->dml2_options.use_native_soc_bb_construction = true; 2295 dc->dml2_options.minimize_dispclk_using_odm = false; 2296 if (dc->config.EnableMinDispClkODM) 2297 dc->dml2_options.minimize_dispclk_using_odm = true; 2298 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; 2299 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2300 dc->dml2_options.force_tdlut_enable = true; 2301 2302 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2303 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = 2304 &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2305 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; 2306 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = 2307 pool->base.funcs->calculate_mall_ways_from_bytes; 2308 2309 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; 2310 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; 2311 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 2312 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; 2313 2314 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; 2315 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; 2316 2317 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; 2318 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; 2319 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = 2320 dc->caps.max_cab_allocation_bytes; 2321 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; 2322 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; 2323 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; 2324 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; 2325 2326 dc->dml2_options.max_segments_per_hubp = 24; 2327 dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; 2328 dc->dml2_options.gpuvm_enable = true; 2329 dc->dml2_options.hostvm_enable = true; 2330 2331 /* SPL */ 2332 dc->caps.scl_caps.sharpener_support = true; 2333 2334 return true; 2335 2336 create_fail: 2337 2338 dcn42_resource_destruct(pool); 2339 2340 return false; 2341 } 2342 struct resource_pool *dcn42_create_resource_pool( 2343 const struct dc_init_data *init_data, 2344 struct dc *dc) 2345 { 2346 struct dcn42_resource_pool *pool = 2347 kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL); 2348 2349 if (!pool) 2350 return NULL; 2351 2352 if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) 2353 return &pool->base; 2354 2355 BREAK_TO_DEBUGGER(); 2356 kfree(pool); 2357 return NULL; 2358 } 2359