1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10 #include "dcn60/dcn60_init.h"
11
12 #include "resource.h"
13 #include "include/irq_service_interface.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn32/dcn32_resource.h"
18 #include "dcn321/dcn321_resource.h"
19 #include "dcn401/dcn401_resource.h"
20 #include "dcn42/dcn42_resource.h"
21 #include "dcn60_resource.h"
22
23 #include "dcn10/dcn10_ipp.h"
24 #include "dcn60/dcn60_hubbub.h"
25 #include "dcn60/dcn60_mpc.h"
26 #include "dcn60/dcn60_hubp.h"
27 #include "irq/dcn60/irq_service_dcn60.h"
28 #include "dcn60/dcn60_dpp.h"
29 #include "dcn60/dcn60_optc.h"
30 #include "dcn20/dcn20_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dcn10/dcn10_hwseq.h"
33 #include "dcn60/dcn60_opp.h"
34 #include "dcn60/dcn60_dsc.h"
35 #include "dcn30/dcn30_vpg.h"
36 #include "dcn31/dcn31_vpg.h"
37 #include "dcn30/dcn30_dio_stream_encoder.h"
38 #include "dcn401/dcn401_dio_stream_encoder.h"
39 #include "dcn60/dcn60_dio_stream_encoder.h"
40 #include "dcn401/dcn401_hpo_frl_stream_encoder.h"
41 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
42 #include "dcn60/dcn60_hpo_frl_link_encoder.h"
43 #include "dcn60/dcn60_hpo_frl_stream_encoder.h"
44 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
45 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
46 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
47 #include "dcn31/dcn31_dio_link_encoder.h"
48 #include "dcn401/dcn401_dio_link_encoder.h"
49 #include "dcn60/dcn60_dio_link_encoder.h"
50 #include "dcn10/dcn10_link_encoder.h"
51 #include "dcn321/dcn321_dio_link_encoder.h"
52 #include "dce/dce_clock_source.h"
53 #include "dce/dce_audio.h"
54 #include "dce/dce_hwseq.h"
55 #include "clk_mgr.h"
56 #include "dio/virtual/virtual_stream_encoder.h"
57 #include "dml/display_mode_vba.h"
58 #include "dcn60/dcn60_dccg.h"
59 #include "dcn10/dcn10_resource.h"
60 #include "link_service.h"
61 #include "link_enc_cfg.h"
62 #include "dcn31/dcn31_panel_cntl.h"
63
64 #include "dcn30/dcn30_dwb.h"
65 #include "dcn32/dcn32_mmhubbub.h"
66
67 #include "dcn/dcn_6_0_0_offset.h"
68 #include "dcn/dcn_6_0_0_sh_mask.h"
69 #include "dpcs/dpcs_6_0_0_offset.h"
70 #include "dpcs/dpcs_6_0_0_sh_mask.h"
71
72 #include "reg_helper.h"
73 #include "dce/dmub_abm.h"
74 #include "dce/dmub_psr.h"
75 #include "dce/dce_aux.h"
76 #include "dce/dce_i2c.h"
77
78 #include "dml/dcn30/display_mode_vba_30.h"
79 #include "vm_helper.h"
80 #include "dcn20/dcn20_vmid.h"
81
82 #include "dc_state_priv.h"
83
84 #include "dml2_0/dml2_wrapper.h"
85 #include "dml2_0/dml21/dml21_wrapper.h"
86
87 #define DC_LOGGER_INIT(logger)
88
89 /* begin *********************
90 * macros to expend register list macro defined in HW object header file
91 */
92
93 enum dcn60_clk_src_array_id {
94 DCN60_CLK_SRC_PLL0,
95 DCN60_CLK_SRC_PLL1,
96 DCN60_CLK_SRC_PLL2,
97 DCN60_CLK_SRC_PLL3,
98 //DCN60_CLK_SRC_PLL4,
99 DCN60_CLK_SRC_TOTAL
100 };
101
102 static const uint32_t MCACHE_ID_UNASSIGNED = 0xF;
103 static const uint32_t SPLIT_LOCATION_UNDEFINED = 0xFFFF;
104
105 /* DCN */
106 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
107
108 #define BASE(seg) BASE_INNER(seg)
109
110 #define SR(reg_name)\
111 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
112 reg ## reg_name
113 #define SR_ARR(reg_name, id)\
114 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
115 reg ## reg_name
116 #define SR_ARR_INIT(reg_name, id, value)\
117 REG_STRUCT[id].reg_name = value
118
119 #define SRI(reg_name, block, id)\
120 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 reg ## block ## id ## _ ## reg_name
122
123 #define SRI_ARR(reg_name, block, id)\
124 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
125 reg ## block ## id ## _ ## reg_name
126
127 #define SRI_ARR_DDC(reg_name, block, id)\
128 REG_STRUCT[id-1].reg_name = BASE(reg ## reg_name ## id ## _ ## block ## _BASE_IDX) + \
129 reg ## reg_name ## id ## _ ## block
130
131 /*
132 * Used when a reg_name would otherwise begin with an integer
133 */
134 #define SRI_ARR_US(reg_name, block, id)\
135 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
136 reg ## block ## id ## reg_name
137 #define SR_ARR_I2C(reg_name, id) \
138 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
139
140 #define SRI_ARR_I2C(reg_name, block, id)\
141 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRI_ARR_DME(reg_name, block, id, offset)\
145 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 reg ## block ## id ## _ ## reg_name
147
148 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
149 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRI2(reg_name, block, id)\
153 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
154 reg ## reg_name
155 #define SRI2_ARR(reg_name, block, id)\
156 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
157 reg ## reg_name
158
159 #define SRIR(var_name, reg_name, block, id)\
160 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## reg_name
162
163 #define SRII(reg_name, block, id)\
164 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SRII_ARR_2(reg_name, block, id, inst)\
168 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## reg_name
170
171 #define SRII_MPC_RMU(reg_name, block, id)\
172 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
174
175 #define SRII_DWB(reg_name, temp_name, block, id)\
176 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
177 reg ## block ## id ## _ ## temp_name
178
179 #define DCCG_SRII(reg_name, block, id)\
180 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
182
183 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
184 .field_name = reg_name ## __ ## field_name ## post_fix
185
186 #define VUPDATE_SRII(reg_name, block, id)\
187 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
188 reg ## reg_name ## _ ## block ## id
189
190 /* bringup_nbif_7_10_0_offset registers */
191 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b
192 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1
193 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e
194 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1
195
196 /* NBIO */
197 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
198
199 #define NBIO_BASE(seg) \
200 NBIO_BASE_INNER(seg)
201
202 #define NBIO_SR(reg_name)\
203 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
204 regBIF_BX0_ ## reg_name
205 #define NBIO_SR_ARR(reg_name, id)\
206 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
207 regBIF_BX0_ ## reg_name
208
209 #define CTX ctx
210 #define REG(reg_name) \
211 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
212
213 static struct bios_registers bios_regs;
214
215 #define bios_regs_init() \
216 NBIO_SR(BIOS_SCRATCH_3),\
217 NBIO_SR(BIOS_SCRATCH_6)
218
219 #define clk_src_regs_init(index, pllid)\
220 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
221
222 static struct dce110_clk_src_regs clk_src_regs[5];
223
224 static const struct dce110_clk_src_shift cs_shift = {
225 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
226 };
227
228 static const struct dce110_clk_src_mask cs_mask = {
229 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
230 };
231
232 #define abm_regs_init(id)\
233 ABM_DCN42_REG_LIST_RI(id)
234
235 static struct dce_abm_registers abm_regs[4];
236
237 static const struct dce_abm_shift abm_shift = {
238 ABM_MASK_SH_LIST_DCN42(__SHIFT)
239 };
240
241 static const struct dce_abm_mask abm_mask = {
242 ABM_MASK_SH_LIST_DCN42(_MASK)
243 };
244
245 #define audio_regs_init(id)\
246 AUD_COMMON_REG_LIST_RI(id)
247
248 static struct dce_audio_registers audio_regs[5];
249
250 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
251 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
252 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
253 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
254 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
255 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
256 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
257 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
258 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
259 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
260 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
261 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
262 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
263 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
264
265 static const struct dce_audio_shift audio_shift = {
266 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
267 };
268
269 static const struct dce_audio_mask audio_mask = {
270 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
271 };
272
273 #define vpg_regs_init(id)\
274 VPG_DCN401_REG_LIST_RI(id)
275
276 static struct dcn31_vpg_registers vpg_regs[9];
277
278 static const struct dcn31_vpg_shift vpg_shift = {
279 DCN31_VPG_MASK_SH_LIST(__SHIFT)
280 };
281
282 static const struct dcn31_vpg_mask vpg_mask = {
283 DCN31_VPG_MASK_SH_LIST(_MASK)
284 };
285
286 #define apg_regs_init(id)\
287 APG_DCN31_REG_LIST_RI(id)
288
289 static struct dcn31_apg_registers apg_regs[4];
290
291 static const struct dcn31_apg_shift apg_shift = {
292 DCN31_APG_MASK_SH_LIST(__SHIFT)
293 };
294
295 static const struct dcn31_apg_mask apg_mask = {
296 DCN31_APG_MASK_SH_LIST(_MASK)
297 };
298
299 #define stream_enc_regs_init(id)\
300 SE_REG_LIST_DCN60_RI(id)
301
302 static struct dcn10_stream_enc_registers stream_enc_regs[4];
303
304 static const struct dcn10_stream_encoder_shift se_shift = {
305 SE_COMMON_MASK_SH_LIST_DCN60(__SHIFT)
306 };
307
308 static const struct dcn10_stream_encoder_mask se_mask = {
309 SE_COMMON_MASK_SH_LIST_DCN60(_MASK)
310 };
311
312 #define aux_regs_init(id, ddc_id)\
313 DCN60_AUX_REG_LIST_RI(id, ddc_id)
314
315 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
316
317 #define hpd_regs_init(id)\
318 HPD_REG_LIST_DCN60_RI(id)
319
320 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
321
322 #define link_regs_init(id, phyid)\
323 LE_DCN401_REG_LIST_RI(id), \
324 LE_DCN60_REG_LIST_RI(id)
325
326 static struct dcn10_link_enc_registers link_enc_regs[4];
327
328 static const struct dcn10_link_enc_shift le_shift = {
329 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT), \
330 LINK_ENCODER_MASK_SH_LIST_DCN60(__SHIFT)
331 };
332
333 static const struct dcn10_link_enc_mask le_mask = {
334 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK), \
335 LINK_ENCODER_MASK_SH_LIST_DCN60(_MASK)
336 };
337
338 #define hpo_frl_stream_encoder_reg_list(id)\
339 DCN60_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
340
341 #define hpo_frl_stream_encoder_dme_reg_list(id)\
342 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 4)
343
344 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
345
346 static const struct dcn401_hpo_frl_stream_encoder_shift hpo_se_shift = {
347 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT),
348 DCN60_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT)
349 };
350
351 static const struct dcn401_hpo_frl_stream_encoder_mask hpo_se_mask = {
352 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(_MASK),
353 DCN60_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK)
354 };
355
356 #define hpo_frl_link_encoder_reg_list(id)\
357 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
358
359 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
360
361 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
362 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
363 };
364
365 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
366 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
367 };
368
369 #define hpo_dp_stream_encoder_reg_init(id)\
370 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
371
372 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
373
374 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
375 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
376 };
377
378 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
379 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
380 };
381
382 #define hpo_dp_link_encoder_reg_init(id)\
383 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
384 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
385 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
386 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
387 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
388
389 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
390
391 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
392 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
393 };
394
395 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
396 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
397 };
398
399 #define dpp_regs_init(id)\
400 DPP_REG_LIST_DCN60_RI(id)
401
402 static struct dcn60_dpp_registers dpp_regs[4];
403
404 static const struct dcn60_dpp_shift tf_shift = {
405 DPP_REG_LIST_SH_MASK_DCN60(__SHIFT)
406 };
407
408 static const struct dcn60_dpp_mask tf_mask = {
409 DPP_REG_LIST_SH_MASK_DCN60(_MASK)
410 };
411
412 #define opp_regs_init(id)\
413 OPP_REG_LIST_DCN401_RI(id)
414
415 static struct dcn60_opp_registers opp_regs[4];
416
417 static const struct dcn60_opp_shift opp_shift = {
418 OPP_MASK_SH_LIST_DCN60(__SHIFT)
419 };
420
421 static const struct dcn60_opp_mask opp_mask = {
422 OPP_MASK_SH_LIST_DCN60(_MASK)
423 };
424
425 #define aux_engine_regs_init(id) \
426 AUX_COMMON_REG_LIST0_RI(id), \
427 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
428 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
429 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
430
431 static struct dce110_aux_registers aux_engine_regs[4];
432
433 static const struct dce110_aux_registers_shift aux_shift = {
434 DCN_AUX_MASK_SH_LIST(__SHIFT)
435 };
436
437 static const struct dce110_aux_registers_mask aux_mask = {
438 DCN_AUX_MASK_SH_LIST(_MASK)
439 };
440
441 #define dsc_regs_init(id)\
442 DSC_REG_LIST_DCN60_RI(id)
443
444 static struct dcn401_dsc_registers dsc_regs[4];
445
446 static const struct dcn60_dsc_shift dsc_shift = {
447 DSC_REG_LIST_SH_MASK_DCN60(__SHIFT)
448 };
449
450 static const struct dcn60_dsc_mask dsc_mask = {
451 DSC_REG_LIST_SH_MASK_DCN60(_MASK)
452 };
453
454 static struct dcn60_mpc_registers mpc_regs;
455
456 #define dcn_mpc_regs_init()\
457 MPC_REG_LIST_DCN6_0_RI(0),\
458 MPC_REG_LIST_DCN6_0_RI(1),\
459 MPC_REG_LIST_DCN6_0_RI(2),\
460 MPC_REG_LIST_DCN6_0_RI(3),\
461 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
462 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
463 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
464 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
465 MPC_RMCM_REG_LIST_DCN42(0),\
466 MPC_RMCM_REG_LIST_DCN42(1)
467
468 static const struct dcn60_mpc_shift mpc_shift = {
469 MPC_COMMON_MASK_SH_LIST_DCN6_0(__SHIFT)
470 };
471
472 static const struct dcn60_mpc_mask mpc_mask = {
473 MPC_COMMON_MASK_SH_LIST_DCN6_0(_MASK)
474 };
475
476 #define optc_regs_init(id)\
477 OPTC_COMMON_REG_LIST_DCN60_RI(id)
478
479 static struct dcn_optc_registers optc_regs[4];
480
481 static const struct dcn_optc_shift optc_shift = {
482 OPTC_COMMON_MASK_SH_LIST_DCN60(__SHIFT)
483 };
484
485 static const struct dcn_optc_mask optc_mask = {
486 OPTC_COMMON_MASK_SH_LIST_DCN60(_MASK)
487 };
488
489 static struct dcn_hubp2_registers hubp_regs[4];
490
491 #define hubp_regs_init(id)\
492 HUBP_REG_LIST_DCN60_RI(id)
493
494 static const struct dcn_hubp2_shift hubp_shift = {
495 HUBP_MASK_SH_LIST_DCN60(__SHIFT)
496 };
497
498 static const struct dcn_hubp2_mask hubp_mask = {
499 HUBP_MASK_SH_LIST_DCN60(_MASK)
500 };
501
502 static struct dcn_hubbub_registers hubbub_reg;
503 #define hubbub_reg_init()\
504 HUBBUB_REG_LIST_DCN60_RI(0)
505
506 static const struct dcn_hubbub_shift hubbub_shift = {
507 HUBBUB_MASK_SH_LIST_DCN6_0(__SHIFT)
508 };
509
510 static const struct dcn_hubbub_mask hubbub_mask = {
511 HUBBUB_MASK_SH_LIST_DCN6_0(_MASK)
512 };
513
514 static struct dccg_registers dccg_regs;
515
516 #define dccg_regs_init()\
517 DCCG_REG_LIST_DCN60_RI()
518
519 static const struct dccg_shift dccg_shift = {
520 DCCG_MASK_SH_LIST_DCN60(__SHIFT)
521 };
522
523 static const struct dccg_mask dccg_mask = {
524 DCCG_MASK_SH_LIST_DCN60(_MASK)
525 };
526
527 #define SRII2(reg_name_pre, reg_name_post, id)\
528 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
529 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
530 reg ## reg_name_pre ## id ## _ ## reg_name_post
531
532 static struct dce_hwseq_registers hwseq_reg;
533
534 #define hwseq_reg_init()\
535 HWSEQ_DCN60_REG_LIST()
536
537 #define HWSEQ_DCN60_MASK_SH_LIST(mask_sh)\
538 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
539 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
540 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
541 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
542 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
543 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
544 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
545 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
546 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
547 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
548 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh),
549
550 static const struct dce_hwseq_shift hwseq_shift = {
551 HWSEQ_DCN60_MASK_SH_LIST(__SHIFT)
552 };
553
554 static const struct dce_hwseq_mask hwseq_mask = {
555 HWSEQ_DCN60_MASK_SH_LIST(_MASK)
556 };
557
558 #define vmid_regs_init(id)\
559 DCN20_VMID_REG_LIST_RI(id)
560
561 static struct dcn_vmid_registers vmid_regs[16];
562
563 static const struct dcn20_vmid_shift vmid_shifts = {
564 DCN20_VMID_MASK_SH_LIST(__SHIFT)
565 };
566
567 static const struct dcn20_vmid_mask vmid_masks = {
568 DCN20_VMID_MASK_SH_LIST(_MASK)
569 };
570
571 static const struct resource_caps res_cap_dcn6_0 = {
572 .num_timing_generator = 4,
573 .num_opp = 4,
574 .num_video_plane = 4,
575 .num_audio = 4,
576 .num_stream_encoder = 4,
577 .num_hpo_frl = 1,
578 .num_hpo_dp_stream_encoder = 4,
579 .num_hpo_dp_link_encoder = 4,
580 .num_pll = 4,
581 .num_dwb = 0,
582 .num_ddc = 2,
583 .num_vmid = 16,
584 .num_mpc_3dlut = 4,
585 .num_dsc = 4,
586 .num_aux = 4,
587 .num_rmcm = 2,
588 };
589
590 static const struct dc_plane_cap plane_cap = {
591 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
592 .per_pixel_alpha = true,
593
594 .pixel_format_support = {
595 .argb8888 = true,
596 .nv12 = true,
597 .fp16 = true,
598 .p010 = true,
599 .ayuv = false,
600 },
601
602 .max_upscale_factor = {
603 .argb8888 = 16000,
604 .nv12 = 16000,
605 .fp16 = 16000
606 },
607
608 // 6:1 downscaling ratio: 1000/6 = 166.666
609 .max_downscale_factor = {
610 .argb8888 = 167,
611 .nv12 = 167,
612 .fp16 = 167
613 },
614 64,
615 64
616 };
617
618 static const struct dc_debug_options debug_defaults_drv = {
619 .limit_ffe = 7,
620 .disable_dmcu = true,
621 .force_abm_enable = false,
622 .clock_trace = true,
623 .disable_pplib_clock_request = false,
624 .pipe_split_policy = MPC_SPLIT_AVOID,
625 .force_single_disp_pipe_split = false,
626 .disable_dcc = DCC_ENABLE,
627 .vsr_support = true,
628 .performance_trace = false,
629 .max_downscale_src_width = 7680,/*upto 8K*/
630 .disable_pplib_wm_range = false,
631 .scl_reset_length10 = true,
632 .sanity_checks = false,
633 .underflow_assert_delay_us = 0xFFFFFFFF,
634 .dwb_fi_phase = -1, // -1 = disable,
635 .dmub_command_table = true,
636 .enable_mem_low_power = {
637 .bits = {
638 .vga = false,
639 .i2c = false,
640 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
641 .dscl = false,
642 .cm = false,
643 .mpc = false,
644 .optc = true,
645 }
646 },
647 .use_max_lb = true,
648 .exit_idle_opt_for_cursor_updates = true,
649 .using_dml2 = true,
650 .using_dml21 = true,
651 .enable_single_display_2to1_odm_policy = true,
652
653 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
654 .enable_double_buffered_dsc_pg_support = true,
655 .enable_dp_dig_pixel_rate_div_policy = 1,
656 .allow_sw_cursor_fallback = false,
657 .alloc_extra_way_for_cursor = true,
658 .min_prefetch_in_strobe_ns = 60000, // 60us
659 .disable_unbounded_requesting = false,
660 .dcc_meta_propagation_delay_us = 10,
661 .fams_version = {
662 .minor = 0,
663 .major = 3,
664 }, // v3.0
665 .fams2_config = {
666 .bits = {
667 .enable = true,
668 .enable_ppt_check = true,
669 .enable_offload_flip = true,
670 .enable_stall_recovery = true,
671 }
672 },
673 .force_cositing = CHROMA_COSITING_NONE + 1,
674 };
675
676 static const struct dc_check_config config_defaults = {
677 .enable_legacy_fast_update = false,
678 };
679
is_plane1_enabled(enum surface_pixel_format format)680 static bool is_plane1_enabled(enum surface_pixel_format format)
681 {
682 return (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA ||
683 format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb ||
684 format == SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb);
685 }
686
reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs * pipe_mcache_regs)687 static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *pipe_mcache_regs)
688 {
689 // Initialize all entries to special valid MCache ID and special valid split coordinate
690 pipe_mcache_regs->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
691 pipe_mcache_regs->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
692 pipe_mcache_regs->main.p0.split_location = SPLIT_LOCATION_UNDEFINED;
693
694 pipe_mcache_regs->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
695 pipe_mcache_regs->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
696 pipe_mcache_regs->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED;
697
698 pipe_mcache_regs->main.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
699 pipe_mcache_regs->main.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
700 pipe_mcache_regs->main.p1.split_location = SPLIT_LOCATION_UNDEFINED;
701
702 pipe_mcache_regs->mall.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
703 pipe_mcache_regs->mall.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
704 pipe_mcache_regs->mall.p1.split_location = SPLIT_LOCATION_UNDEFINED;
705 }
706
get_plane_count(struct dc_state * context,unsigned int * plane_count)707 static void get_plane_count(struct dc_state *context, unsigned int *plane_count)
708 {
709 int i;
710 *plane_count = 0;
711 for (i = 0; i < context->stream_count; i++) {
712 *plane_count += context->stream_status[i].plane_count;
713 }
714 }
715
get_plane_index(struct dc_state * context,struct dc_plane_state * plane_state,unsigned int * plane_idx)716 static bool get_plane_index(struct dc_state *context, struct dc_plane_state *plane_state, unsigned int *plane_idx)
717 {
718 int i, j;
719 *plane_idx = 0;
720 for (i = 0; i < context->stream_count; i++) {
721 for (j = 0; j < context->stream_status[i].plane_count; j++) {
722 if (plane_state == context->stream_status[i].plane_states[j]) {
723 return true;
724 }
725 (*plane_idx)++;
726 }
727 }
728 // No planes have been mapped to this pipe, so just return false
729 return false;
730 }
731
assign_global_mcache_ids(struct dc_state * context,const struct dc_mcache_params * mcache_params,struct dc_mcache_allocations * mcache_allocations)732 static void assign_global_mcache_ids(struct dc_state *context, const struct dc_mcache_params *mcache_params, struct dc_mcache_allocations *mcache_allocations)
733 {
734 unsigned int plane_count = 0;
735 unsigned int i;
736 unsigned int plane_idx;
737 uint32_t next_unused_cache_id = 0;
738
739 //Get plane count
740 get_plane_count(context, &plane_count);
741
742 //Assign global_mcache id
743 for (plane_idx = 0; plane_idx < plane_count; plane_idx++) {
744 if (!mcache_params[plane_idx].valid)
745 continue;
746
747 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane0; i++) {
748 mcache_allocations[plane_idx].global_mcache_ids_plane0[i] = next_unused_cache_id++;
749 }
750 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane1; i++) {
751 mcache_allocations[plane_idx].global_mcache_ids_plane1[i] = next_unused_cache_id++;
752 }
753
754 // The "psuedo-last" slice is always wrapped around
755 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0] =
756 mcache_allocations[plane_idx].global_mcache_ids_plane0[0];
757 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1] =
758 mcache_allocations[plane_idx].global_mcache_ids_plane1[0];
759
760 // If we need dedicated caches for mall requesting, then we assign them here.
761 if (mcache_params[plane_idx].requires_dedicated_mall_mcache) {
762 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane0; i++) {
763 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[i] = next_unused_cache_id++;
764 }
765 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane1; i++) {
766 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[i] = next_unused_cache_id++;
767 }
768
769 // The "psuedo-last" slice is always wrapped around
770 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0] =
771 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[0];
772 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1] =
773 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[0];
774 }
775
776 // If P0 and P1 are sharing caches, then it means the largest mcache IDs for p0 and p1 can be the same
777 // since mcache IDs are always ascending, then it means the largest mcacheID of p1 should be the
778 // largest mcacheID of P0
779 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].num_mcaches_plane1 > 0 &&
780 mcache_params[plane_idx].last_slice_sharing.plane0_plane1) {
781 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] =
782 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1];
783 }
784
785 // If we need dedicated caches handle last slice sharing
786 if (mcache_params[plane_idx].requires_dedicated_mall_mcache) {
787 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].num_mcaches_plane1 > 0 &&
788 mcache_params[plane_idx].last_slice_sharing.plane0_plane1) {
789 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] =
790 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1];
791 }
792 // If mall_comb_mcache_l is set then it means that largest mcache ID for MALL p0 can be same as regular read p0
793 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].last_slice_sharing.mall_comb_mcache_p0) {
794 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1] =
795 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1];
796 }
797 // If mall_comb_mcache_c is set then it means that largest mcache ID for MALL p1 can be same as regular
798 // read p1 (which can be same as regular read p0 if plane0_plane1 is also set)
799 if (mcache_params[plane_idx].num_mcaches_plane1 > 0 && mcache_params[plane_idx].last_slice_sharing.mall_comb_mcache_p1) {
800 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] =
801 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1];
802 }
803 }
804
805 // If you don't need dedicated mall mcaches, the mall mcache assignments are identical to the normal requesting
806 if (!mcache_params[plane_idx].requires_dedicated_mall_mcache) {
807 memcpy(mcache_allocations[plane_idx].global_mcache_ids_mall_plane0, mcache_allocations[plane_idx].global_mcache_ids_plane0,
808 sizeof(mcache_allocations[plane_idx].global_mcache_ids_mall_plane0));
809 memcpy(mcache_allocations[plane_idx].global_mcache_ids_mall_plane1, mcache_allocations[plane_idx].global_mcache_ids_plane1,
810 sizeof(mcache_allocations[plane_idx].global_mcache_ids_mall_plane1));
811 }
812 }
813 }
814
dc_calculate_first_second_splitting(const int * mcache_boundaries,int num_boundaries,int shift,int pipe_h_vp_start,int pipe_h_vp_end,int * first_offset,int * second_offset)815 static bool dc_calculate_first_second_splitting(const int *mcache_boundaries, int num_boundaries, int shift,
816 int pipe_h_vp_start, int pipe_h_vp_end, int *first_offset, int *second_offset)
817 {
818 const int MAX_VP = 0xFFFFFF;
819 int left_cache_id;
820 int right_cache_id;
821 int range_start;
822 int range_end;
823 bool success = false;
824
825 if (num_boundaries <= 1) {
826 if (first_offset && second_offset) {
827 *first_offset = 0;
828 *second_offset = -1;
829 }
830 success = true;
831 return success;
832 } else {
833 range_start = 0;
834 for (left_cache_id = 0; left_cache_id < num_boundaries; left_cache_id++) {
835 range_end = mcache_boundaries[left_cache_id] - shift - 1;
836
837 if (range_start <= pipe_h_vp_start && pipe_h_vp_start <= range_end)
838 break;
839
840 range_start = range_end + 1;
841 }
842
843 range_end = MAX_VP;
844 for (right_cache_id = num_boundaries - 1; right_cache_id >= -1; right_cache_id--) {
845 if (right_cache_id >= 0)
846 range_start = mcache_boundaries[right_cache_id] - shift;
847 else
848 range_start = 0;
849
850 if (range_start <= pipe_h_vp_end && pipe_h_vp_end <= range_end) {
851 break;
852 }
853 range_end = range_start - 1;
854 }
855 right_cache_id = (right_cache_id + 1) % num_boundaries;
856
857 if (right_cache_id == left_cache_id) {
858 if (first_offset && second_offset) {
859 *first_offset = left_cache_id;
860 *second_offset = -1;
861 }
862 success = true;
863 } else if (right_cache_id == (left_cache_id + 1) % num_boundaries) {
864 if (first_offset && second_offset) {
865 *first_offset = left_cache_id;
866 *second_offset = right_cache_id;
867 }
868 success = true;
869 }
870 }
871
872 return success;
873 }
874
build_mcache_pipe_regs_config(struct dc_state * context,const struct dc_mcache_params * mcache_params,struct dc_mcache_allocations * mcache_allocations)875 static bool build_mcache_pipe_regs_config(struct dc_state *context, const struct dc_mcache_params *mcache_params, struct dc_mcache_allocations *mcache_allocations)
876 {
877 bool success = true;
878 int first_offset, second_offset;
879 unsigned int plane_idx;
880 int pipe_idx;
881
882 for (pipe_idx = 0; pipe_idx < MAX_PIPES; pipe_idx++) {
883 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
884 if (get_plane_index(context, pipe_ctx->plane_state, &plane_idx) && pipe_ctx->plane_res.hubp) {
885 reset_mcache_allocations(&pipe_ctx->mcache_regs);
886 if (pipe_ctx->plane_state->dcc.enable) {
887 // P0 always enabled
888 if (!dc_calculate_first_second_splitting(mcache_params[plane_idx].mcache_x_offsets_plane0,
889 mcache_params[plane_idx].num_mcaches_plane0,
890 0,
891 pipe_ctx->plane_res.scl_data.viewport.x,
892 pipe_ctx->plane_res.scl_data.viewport.x +
893 pipe_ctx->plane_res.scl_data.viewport.width - 1,
894 &first_offset, &second_offset)) {
895 success = false;
896 break;
897 }
898
899 pipe_ctx->mcache_regs.main.p0.mcache_id_first =
900 mcache_allocations[plane_idx].global_mcache_ids_plane0[first_offset];
901
902 pipe_ctx->mcache_regs.mall.p0.mcache_id_first =
903 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[first_offset];
904
905 if (second_offset >= 0) {
906 pipe_ctx->mcache_regs.main.p0.mcache_id_second =
907 mcache_allocations[plane_idx].global_mcache_ids_plane0[second_offset];
908 pipe_ctx->mcache_regs.main.p0.split_location =
909 mcache_params[plane_idx].mcache_x_offsets_plane0[first_offset] - 1;
910
911 pipe_ctx->mcache_regs.mall.p0.mcache_id_second =
912 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[second_offset];
913 pipe_ctx->mcache_regs.mall.p0.split_location =
914 mcache_params[plane_idx].mcache_x_offsets_plane0[first_offset] - 1;
915 }
916
917 // Populate P1 if enabled
918 if (is_plane1_enabled(pipe_ctx->plane_state->format)) {
919 if (!dc_calculate_first_second_splitting(mcache_params[plane_idx].mcache_x_offsets_plane1,
920 mcache_params[plane_idx].num_mcaches_plane1,
921 0,
922 pipe_ctx->plane_res.scl_data.viewport_c.x,
923 pipe_ctx->plane_res.scl_data.viewport_c.x +
924 pipe_ctx->plane_res.scl_data.viewport_c.width - 1,
925 &first_offset, &second_offset)) {
926 success = false;
927 break;
928 }
929
930 pipe_ctx->mcache_regs.main.p1.mcache_id_first =
931 mcache_allocations[plane_idx].global_mcache_ids_plane1[first_offset];
932
933 pipe_ctx->mcache_regs.mall.p1.mcache_id_first =
934 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[first_offset];
935
936 if (second_offset >= 0) {
937 pipe_ctx->mcache_regs.main.p1.mcache_id_second =
938 mcache_allocations[plane_idx].global_mcache_ids_plane1[second_offset];
939 pipe_ctx->mcache_regs.main.p1.split_location =
940 mcache_params[plane_idx].mcache_x_offsets_plane1[first_offset] - 1;
941
942 pipe_ctx->mcache_regs.mall.p1.mcache_id_second =
943 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[second_offset];
944 pipe_ctx->mcache_regs.mall.p1.split_location =
945 mcache_params[plane_idx].mcache_x_offsets_plane1[first_offset] - 1;
946 }
947 }
948 }
949 }
950 }
951 return success;
952 }
953
dcn60_program_mcache_pipe_config(struct dc_state * context,const struct dc_mcache_params * mcache_params)954 bool dcn60_program_mcache_pipe_config(struct dc_state *context, const struct dc_mcache_params *mcache_params)
955 {
956 struct dc_mcache_allocations mcache_allocations[MAX_PLANES] = {0};
957 if (!mcache_params) {
958 return false;
959 }
960
961 // Step 1: Assign global mcache IDs for each plane
962 assign_global_mcache_ids(context, mcache_params, mcache_allocations);
963
964 // Step 2: Build the mcache pipe configuration
965 if (!build_mcache_pipe_regs_config(context, mcache_params, mcache_allocations)) {
966 return false;
967 }
968
969 return true;
970 }
971
dcn50_program_mcache_pipe_config(struct dc_state * context,const struct dc_mcache_params * mcache_params)972 bool dcn50_program_mcache_pipe_config(struct dc_state *context, const struct dc_mcache_params *mcache_params)
973 {
974 int pipe_idx;
975
976 if (!mcache_params) {
977 return false;
978 }
979
980 for (pipe_idx = 0; pipe_idx < MAX_PIPES; pipe_idx++) {
981 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
982 reset_mcache_allocations(&pipe_ctx->mcache_regs);
983 if (pipe_ctx->plane_state && pipe_ctx->plane_state->dcc.enable) {
984 pipe_ctx->mcache_regs.main.p0.mcache_id_first = pipe_ctx->pipe_idx;
985 pipe_ctx->mcache_regs.mall.p0.mcache_id_first = pipe_ctx->pipe_idx;
986 // Populate P1 if enabled
987 if (is_plane1_enabled(pipe_ctx->plane_state->format)) {
988 pipe_ctx->mcache_regs.main.p1.mcache_id_first = pipe_ctx->pipe_idx;
989 pipe_ctx->mcache_regs.mall.p1.mcache_id_first = pipe_ctx->pipe_idx;
990 }
991 }
992 }
993 return true;
994 }
995
dcn60_aux_engine_create(struct dc_context * ctx,uint32_t inst)996 static struct dce_aux *dcn60_aux_engine_create(
997 struct dc_context *ctx,
998 uint32_t inst)
999 {
1000 struct aux_engine_dce110 *aux_engine =
1001 kzalloc_obj(struct aux_engine_dce110);
1002
1003 if (!aux_engine)
1004 return NULL;
1005
1006 #undef REG_STRUCT
1007 #define REG_STRUCT aux_engine_regs
1008 aux_engine_regs_init(0),
1009 aux_engine_regs_init(1),
1010 aux_engine_regs_init(2),
1011 aux_engine_regs_init(3);
1012
1013 dce110_aux_engine_construct(aux_engine, ctx, inst,
1014 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1015 &aux_engine_regs[inst],
1016 &aux_mask,
1017 &aux_shift,
1018 ctx->dc->caps.extended_aux_timeout_support);
1019
1020 return &aux_engine->base;
1021 }
1022 #define i2c_inst_regs_init(id)\
1023 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
1024
1025 static struct dce_i2c_registers i2c_hw_regs[2];
1026
1027 static const struct dce_i2c_shift i2c_shifts = {
1028 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
1029 };
1030
1031 static const struct dce_i2c_mask i2c_masks = {
1032 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
1033 };
1034
dcn60_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1035 static struct dce_i2c_hw *dcn60_i2c_hw_create(
1036 struct dc_context *ctx,
1037 uint32_t inst)
1038 {
1039 struct dce_i2c_hw *dce_i2c_hw =
1040 kzalloc_obj(struct dce_i2c_hw);
1041
1042 if (!dce_i2c_hw)
1043 return NULL;
1044
1045 #undef REG_STRUCT
1046 #define REG_STRUCT i2c_hw_regs
1047 i2c_inst_regs_init(1),
1048 i2c_inst_regs_init(2);
1049
1050 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1051 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1052
1053 return dce_i2c_hw;
1054 }
1055
dcn60_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1056 static struct clock_source *dcn60_clock_source_create(
1057 struct dc_context *ctx,
1058 struct dc_bios *bios,
1059 enum clock_source_id id,
1060 const struct dce110_clk_src_regs *regs,
1061 bool dp_clk_src)
1062 {
1063 struct dce110_clk_src *clk_src =
1064 kzalloc_obj(struct dce110_clk_src);
1065
1066 if (!clk_src)
1067 return NULL;
1068
1069 if (dcn50_clk_src_construct(clk_src, ctx, bios, id,
1070 regs, &cs_shift, &cs_mask)) {
1071 clk_src->base.dp_clk_src = dp_clk_src;
1072 return &clk_src->base;
1073 }
1074
1075 kfree(clk_src);
1076 BREAK_TO_DEBUGGER();
1077 return NULL;
1078 }
1079
dcn60_hubbub_create(struct dc_context * ctx)1080 static struct hubbub *dcn60_hubbub_create(struct dc_context *ctx)
1081 {
1082 int i;
1083
1084 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
1085
1086 if (!hubbub2)
1087 return NULL;
1088
1089 #undef REG_STRUCT
1090 #define REG_STRUCT hubbub_reg
1091 hubbub_reg_init();
1092
1093 #undef REG_STRUCT
1094 #define REG_STRUCT vmid_regs
1095 vmid_regs_init(0),
1096 vmid_regs_init(1),
1097 vmid_regs_init(2),
1098 vmid_regs_init(3),
1099 vmid_regs_init(4),
1100 vmid_regs_init(5),
1101 vmid_regs_init(6),
1102 vmid_regs_init(7),
1103 vmid_regs_init(8),
1104 vmid_regs_init(9),
1105 vmid_regs_init(10),
1106 vmid_regs_init(11),
1107 vmid_regs_init(12),
1108 vmid_regs_init(13),
1109 vmid_regs_init(14),
1110 vmid_regs_init(15);
1111
1112 hubbub60_construct(hubbub2, ctx,
1113 &hubbub_reg,
1114 &hubbub_shift,
1115 &hubbub_mask,
1116 DCN6_0_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
1117 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
1118 DCN6_0_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
1119
1120 for (i = 0; i < res_cap_dcn6_0.num_vmid; i++) {
1121 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
1122
1123 vmid->ctx = ctx;
1124
1125 vmid->regs = &vmid_regs[i];
1126 vmid->shifts = &vmid_shifts;
1127 vmid->masks = &vmid_masks;
1128 }
1129
1130 return &hubbub2->base;
1131 }
1132
dcn60_hubp_create(struct dc_context * ctx,uint32_t inst)1133 static struct hubp *dcn60_hubp_create(
1134 struct dc_context *ctx,
1135 uint32_t inst)
1136 {
1137 struct dcn20_hubp *hubp2 =
1138 kzalloc_obj(struct dcn20_hubp);
1139
1140 if (!hubp2)
1141 return NULL;
1142
1143 #undef REG_STRUCT
1144 #define REG_STRUCT hubp_regs
1145 hubp_regs_init(0),
1146 hubp_regs_init(1),
1147 hubp_regs_init(2),
1148 hubp_regs_init(3);
1149
1150 if (hubp60_construct(hubp2, ctx, inst,
1151 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1152 return &hubp2->base;
1153
1154 BREAK_TO_DEBUGGER();
1155 kfree(hubp2);
1156 return NULL;
1157 }
1158
dcn60_dpp_destroy(struct dpp ** dpp)1159 static void dcn60_dpp_destroy(struct dpp **dpp)
1160 {
1161 kfree(TO_DCN60_DPP(*dpp));
1162 *dpp = NULL;
1163 }
1164
dcn60_dpp_create(struct dc_context * ctx,uint32_t inst)1165 static struct dpp *dcn60_dpp_create(
1166 struct dc_context *ctx,
1167 uint32_t inst)
1168 {
1169 struct dcn60_dpp *dpp60 =
1170 kzalloc_obj(struct dcn60_dpp);
1171
1172 if (!dpp60)
1173 return NULL;
1174
1175 #undef REG_STRUCT
1176 #define REG_STRUCT dpp_regs
1177 dpp_regs_init(0),
1178 dpp_regs_init(1),
1179 dpp_regs_init(2),
1180 dpp_regs_init(3);
1181
1182 if (dpp60_construct(dpp60, ctx, inst,
1183 &dpp_regs[inst], &tf_shift, &tf_mask))
1184 return &dpp60->base;
1185
1186 BREAK_TO_DEBUGGER();
1187 kfree(dpp60);
1188 return NULL;
1189 }
1190
dcn60_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1191 static struct mpc *dcn60_mpc_create(
1192 struct dc_context *ctx,
1193 int num_mpcc,
1194 int num_rmu)
1195 {
1196 struct dcn60_mpc *mpc60 = kzalloc_obj(struct dcn60_mpc);
1197
1198 if (!mpc60)
1199 return NULL;
1200
1201 #undef REG_STRUCT
1202 #define REG_STRUCT mpc_regs
1203 dcn_mpc_regs_init();
1204
1205 dcn60_mpc_construct(mpc60, ctx,
1206 &mpc_regs,
1207 &mpc_shift,
1208 &mpc_mask,
1209 num_mpcc,
1210 num_rmu);
1211
1212 return &mpc60->base;
1213 }
1214
dcn60_opp_create(struct dc_context * ctx,uint32_t inst)1215 static struct output_pixel_processor *dcn60_opp_create(
1216 struct dc_context *ctx, uint32_t inst)
1217 {
1218 struct dcn20_opp *opp2 =
1219 kzalloc_obj(struct dcn20_opp);
1220
1221 if (!opp2) {
1222 BREAK_TO_DEBUGGER();
1223 return NULL;
1224 }
1225
1226 #undef REG_STRUCT
1227 #define REG_STRUCT opp_regs
1228 opp_regs_init(0),
1229 opp_regs_init(1),
1230 opp_regs_init(2),
1231 opp_regs_init(3);
1232
1233 dcn60_opp_construct(opp2, ctx, inst,
1234 &opp_regs[inst], &opp_shift, &opp_mask);
1235 return &opp2->base;
1236 }
1237
dcn60_timing_generator_create(struct dc_context * ctx,uint32_t instance)1238 static struct timing_generator *dcn60_timing_generator_create(
1239 struct dc_context *ctx,
1240 uint32_t instance)
1241 {
1242 struct optc *tgn10 =
1243 kzalloc_obj(struct optc);
1244
1245 if (!tgn10)
1246 return NULL;
1247 #undef REG_STRUCT
1248 #define REG_STRUCT optc_regs
1249 optc_regs_init(0),
1250 optc_regs_init(1),
1251 optc_regs_init(2),
1252 optc_regs_init(3);
1253
1254 tgn10->base.inst = instance;
1255 tgn10->base.ctx = ctx;
1256
1257 tgn10->tg_regs = &optc_regs[instance];
1258 tgn10->tg_shift = &optc_shift;
1259 tgn10->tg_mask = &optc_mask;
1260
1261 dcn60_timing_generator_init(tgn10);
1262
1263 return &tgn10->base;
1264 }
1265
1266 static const struct encoder_feature_support link_enc_feature = {
1267 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1268 .max_hdmi_pixel_clock = 600000,
1269 .hdmi_ycbcr420_supported = true,
1270 .dp_ycbcr420_supported = true,
1271 .fec_supported = true,
1272 .flags.bits.IS_HBR2_CAPABLE = true,
1273 .flags.bits.IS_HBR3_CAPABLE = true,
1274 .flags.bits.IS_TPS3_CAPABLE = true,
1275 .flags.bits.IS_TPS4_CAPABLE = true
1276 };
1277
dcn60_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1278 static struct link_encoder *dcn60_link_encoder_create(
1279 struct dc_context *ctx,
1280 const struct encoder_init_data *enc_init_data)
1281 {
1282 struct dcn20_link_encoder *enc20 =
1283 kzalloc_obj(struct dcn20_link_encoder);
1284
1285 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) {
1286 kfree(enc20);
1287 return NULL;
1288 }
1289
1290 #undef REG_STRUCT
1291 #define REG_STRUCT link_enc_aux_regs
1292 aux_regs_init(0, 1),
1293 aux_regs_init(1, 2),
1294 aux_regs_init(2, 3),
1295 aux_regs_init(3, 4);
1296
1297 #undef REG_STRUCT
1298 #define REG_STRUCT link_enc_hpd_regs
1299 hpd_regs_init(0),
1300 hpd_regs_init(1),
1301 hpd_regs_init(2),
1302 hpd_regs_init(3);
1303 #undef REG_STRUCT
1304 #define REG_STRUCT link_enc_regs
1305 link_regs_init(0, A),
1306 link_regs_init(1, B),
1307 link_regs_init(2, C),
1308 link_regs_init(3, D);
1309
1310 dcn60_link_encoder_construct(enc20,
1311 enc_init_data,
1312 &link_enc_feature,
1313 &link_enc_regs[enc_init_data->transmitter],
1314 &link_enc_aux_regs[enc_init_data->channel - 1],
1315 &link_enc_hpd_regs[enc_init_data->hpd_source],
1316 &le_shift,
1317 &le_mask);
1318 return &enc20->enc10.base;
1319 }
1320
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1321 static void read_dce_straps(
1322 struct dc_context *ctx,
1323 struct resource_straps *straps)
1324 {
1325 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1326 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1327
1328 }
1329
dcn60_create_audio(struct dc_context * ctx,unsigned int inst)1330 static struct audio *dcn60_create_audio(
1331 struct dc_context *ctx, unsigned int inst)
1332 {
1333
1334 #undef REG_STRUCT
1335 #define REG_STRUCT audio_regs
1336 audio_regs_init(0),
1337 audio_regs_init(1),
1338 audio_regs_init(2),
1339 audio_regs_init(3),
1340 audio_regs_init(4);
1341
1342 return dce_audio_create(ctx, inst,
1343 &audio_regs[inst], &audio_shift, &audio_mask);
1344 }
1345
dcn60_vpg_create(struct dc_context * ctx,uint32_t inst)1346 static struct vpg *dcn60_vpg_create(
1347 struct dc_context *ctx,
1348 uint32_t inst)
1349 {
1350 struct dcn31_vpg *vpg6 = kzalloc_obj(struct dcn31_vpg);
1351
1352 if (!vpg6)
1353 return NULL;
1354
1355 #undef REG_STRUCT
1356 #define REG_STRUCT vpg_regs
1357 vpg_regs_init(0),
1358 vpg_regs_init(1),
1359 vpg_regs_init(2),
1360 vpg_regs_init(3),
1361 vpg_regs_init(4),
1362 vpg_regs_init(5),
1363 vpg_regs_init(6),
1364 vpg_regs_init(7),
1365 vpg_regs_init(8);
1366
1367 vpg31_construct(vpg6, ctx, inst,
1368 &vpg_regs[inst],
1369 &vpg_shift,
1370 &vpg_mask);
1371
1372 return &vpg6->base;
1373 }
1374
dcn60_apg_create(struct dc_context * ctx,uint32_t inst)1375 static struct apg *dcn60_apg_create(
1376 struct dc_context *ctx,
1377 uint32_t inst)
1378 {
1379 struct dcn31_apg *apg60 = kzalloc_obj(struct dcn31_apg);
1380
1381 if (!apg60)
1382 return NULL;
1383
1384 #undef REG_STRUCT
1385 #define REG_STRUCT apg_regs
1386 apg_regs_init(0),
1387 apg_regs_init(1),
1388 apg_regs_init(2),
1389 apg_regs_init(3);
1390
1391 apg31_construct(apg60, ctx, inst,
1392 &apg_regs[inst],
1393 &apg_shift,
1394 &apg_mask);
1395
1396 return &apg60->base;
1397 }
1398
dcn60_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1399 static struct stream_encoder *dcn60_stream_encoder_create(
1400 enum engine_id eng_id,
1401 struct dc_context *ctx)
1402 {
1403 struct dcn10_stream_encoder *enc1;
1404 struct vpg *vpg;
1405 struct apg *apg;
1406 int vpg_inst;
1407 uint32_t apg_inst;
1408
1409 /* Mapping of VPG, APG, DME register blocks to DIO block instance */
1410 if (eng_id <= ENGINE_ID_DIGF) {
1411 vpg_inst = eng_id;
1412 apg_inst = eng_id;
1413 } else
1414 return NULL;
1415
1416 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1417 vpg = dcn60_vpg_create(ctx, vpg_inst);
1418 apg = dcn60_apg_create(ctx, apg_inst);
1419
1420 if (!enc1 || !vpg || !apg || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1421 kfree(enc1);
1422 kfree(vpg);
1423 kfree(apg);
1424 return NULL;
1425 }
1426 #undef REG_STRUCT
1427 #define REG_STRUCT stream_enc_regs
1428 stream_enc_regs_init(0),
1429 stream_enc_regs_init(1),
1430 stream_enc_regs_init(2),
1431 stream_enc_regs_init(3);
1432
1433 dcn60_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1434 eng_id, vpg, apg,
1435 &stream_enc_regs[eng_id],
1436 &se_shift, &se_mask);
1437 return &enc1->base;
1438 }
1439
dcn60_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1440 static struct hpo_frl_stream_encoder *dcn60_hpo_frl_stream_encoder_create(
1441 enum engine_id eng_id,
1442 struct dc_context *ctx)
1443 {
1444 struct dcn401_hpo_frl_stream_encoder *hpo_enc60;
1445 struct vpg *vpg;
1446 struct apg *apg;
1447 int vpg_inst;
1448 int apg_inst;
1449
1450 #undef REG_STRUCT
1451 #define REG_STRUCT hpo_frl_stream_enc_regs
1452 hpo_frl_stream_encoder_reg_list(0),
1453 hpo_frl_stream_encoder_dme_reg_list(4);
1454
1455 /* Mapping of VPG, APG, DME register blocks to HPO block instance */
1456 if (eng_id == ENGINE_ID_HPO_0) {
1457 vpg_inst = 4;
1458 apg_inst = 4;
1459 } else
1460 return NULL;
1461
1462 /* allocate HPO stream encoder and create VPG, APG sub-blocks */
1463 hpo_enc60 = kzalloc_obj(struct dcn401_hpo_frl_stream_encoder);
1464 vpg = dcn60_vpg_create(ctx, vpg_inst);
1465 apg = dcn60_apg_create(ctx, apg_inst);
1466
1467 if (!hpo_enc60 || !vpg || !apg) {
1468 kfree(hpo_enc60);
1469 kfree(vpg);
1470 kfree(apg);
1471 return NULL;
1472 }
1473
1474 dcn60_hpo_frl_stream_encoder_construct(hpo_enc60, ctx, ctx->dc_bios,
1475 eng_id, vpg, apg,
1476 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0],
1477 &hpo_se_shift, &hpo_se_mask);
1478
1479 return &hpo_enc60->base;
1480 }
1481
dcn60_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1482 static struct hpo_frl_link_encoder *dcn60_hpo_frl_link_encoder_create(
1483 enum engine_id eng_id,
1484 struct dc_context *ctx)
1485 {
1486 struct dcn30_hpo_frl_link_encoder *hpo_link_enc;
1487 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1488
1489 #undef REG_STRUCT
1490 #define REG_STRUCT hpo_frl_link_enc_regs
1491 hpo_frl_link_encoder_reg_list(0);
1492
1493 /* allocate HPO link encoder */
1494 hpo_link_enc = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1495 if (!hpo_link_enc)
1496 return NULL; /* out of memory */
1497
1498 hpo_frl_link_encoder60_construct(hpo_link_enc, ctx, eng_id-ENGINE_ID_HPO_0,
1499 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0],
1500 &hpo_le_shift, &hpo_le_mask);
1501
1502 return &hpo_link_enc->base;
1503 }
1504
dcn60_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1505 static struct hpo_dp_stream_encoder *dcn60_hpo_dp_stream_encoder_create(
1506 enum engine_id eng_id,
1507 struct dc_context *ctx)
1508 {
1509 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc60;
1510 struct vpg *vpg;
1511 struct apg *apg;
1512 uint32_t hpo_dp_inst;
1513 uint32_t vpg_inst;
1514 uint32_t apg_inst;
1515
1516 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1517 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1518
1519 /* Mapping of VPG register blocks to HPO DP block instance:
1520 * VPG[6] -> HPO_DP[0]
1521 * VPG[7] -> HPO_DP[1]
1522 * VPG[8] -> HPO_DP[2]
1523 * VPG[9] -> HPO_DP[3]
1524 */
1525 vpg_inst = hpo_dp_inst + 5;
1526
1527 /* Mapping of APG register blocks to HPO DP block instance:
1528 * APG[0] -> HPO_DP[0]
1529 * APG[1] -> HPO_DP[1]
1530 * APG[2] -> HPO_DP[2]
1531 * APG[3] -> HPO_DP[3]
1532 */
1533 apg_inst = hpo_dp_inst;
1534
1535 /* allocate HPO stream encoder and create VPG sub-block */
1536 hpo_dp_enc60 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1537 vpg = dcn60_vpg_create(ctx, vpg_inst);
1538 apg = dcn60_apg_create(ctx, apg_inst);
1539
1540 if (!hpo_dp_enc60 || !vpg || !apg) {
1541 kfree(hpo_dp_enc60);
1542 kfree(vpg);
1543 kfree(apg);
1544 return NULL;
1545 }
1546
1547 #undef REG_STRUCT
1548 #define REG_STRUCT hpo_dp_stream_enc_regs
1549 hpo_dp_stream_encoder_reg_init(0),
1550 hpo_dp_stream_encoder_reg_init(1),
1551 hpo_dp_stream_encoder_reg_init(2),
1552 hpo_dp_stream_encoder_reg_init(3);
1553
1554 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc60, ctx, ctx->dc_bios,
1555 hpo_dp_inst, eng_id, vpg, apg,
1556 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1557 &hpo_dp_se_shift, &hpo_dp_se_mask);
1558
1559 return &hpo_dp_enc60->base;
1560 }
1561
dcn60_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1562 static struct hpo_dp_link_encoder *dcn60_hpo_dp_link_encoder_create(
1563 uint8_t inst,
1564 struct dc_context *ctx)
1565 {
1566 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc60;
1567
1568 /* allocate HPO link encoder */
1569 hpo_dp_enc60 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1570 if (!hpo_dp_enc60)
1571 return NULL; /* out of memory */
1572
1573 #undef REG_STRUCT
1574 #define REG_STRUCT hpo_dp_link_enc_regs
1575 hpo_dp_link_encoder_reg_init(0),
1576 hpo_dp_link_encoder_reg_init(1),
1577 hpo_dp_link_encoder_reg_init(2),
1578 hpo_dp_link_encoder_reg_init(3);
1579
1580 hpo_dp_link_encoder32_construct(hpo_dp_enc60, ctx, inst,
1581 &hpo_dp_link_enc_regs[inst],
1582 &hpo_dp_le_shift, &hpo_dp_le_mask);
1583
1584 return &hpo_dp_enc60->base;
1585 }
1586
dcn60_hwseq_create(struct dc_context * ctx)1587 static struct dce_hwseq *dcn60_hwseq_create(
1588 struct dc_context *ctx)
1589 {
1590 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1591
1592 #undef REG_STRUCT
1593 #define REG_STRUCT hwseq_reg
1594 hwseq_reg_init();
1595
1596 if (hws) {
1597 hws->ctx = ctx;
1598 hws->regs = &hwseq_reg;
1599 hws->shifts = &hwseq_shift;
1600 hws->masks = &hwseq_mask;
1601 }
1602
1603 return hws;
1604 }
1605 static const struct resource_create_funcs res_create_funcs = {
1606 .read_dce_straps = read_dce_straps,
1607 .create_audio = dcn60_create_audio,
1608 .create_stream_encoder = dcn60_stream_encoder_create,
1609 .create_hpo_frl_stream_encoder = dcn60_hpo_frl_stream_encoder_create,
1610 .create_hpo_dp_stream_encoder = dcn60_hpo_dp_stream_encoder_create,
1611 .create_hpo_dp_link_encoder = dcn60_hpo_dp_link_encoder_create,
1612 .create_hwseq = dcn60_hwseq_create,
1613 };
1614
dcn60_dsc_destroy(struct display_stream_compressor ** dsc)1615 static void dcn60_dsc_destroy(struct display_stream_compressor **dsc)
1616 {
1617 kfree(container_of(*dsc, struct dcn60_dsc, base));
1618 *dsc = NULL;
1619 }
1620
dcn60_resource_destruct(struct dcn60_resource_pool * pool)1621 static void dcn60_resource_destruct(struct dcn60_resource_pool *pool)
1622 {
1623 unsigned int i;
1624
1625 for (i = 0; i < pool->base.stream_enc_count; i++) {
1626 if (pool->base.stream_enc[i] != NULL) {
1627 if (pool->base.stream_enc[i]->vpg != NULL) {
1628 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1629 pool->base.stream_enc[i]->vpg = NULL;
1630 }
1631 if (pool->base.stream_enc[i]->apg != NULL) {
1632 kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg));
1633 pool->base.stream_enc[i]->apg = NULL;
1634 }
1635 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1636 pool->base.stream_enc[i] = NULL;
1637 }
1638 }
1639
1640 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1641 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1642 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1643 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1644 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1645 }
1646 if (pool->base.hpo_frl_stream_enc[i]->apg != NULL) {
1647 kfree(DCN31_APG_FROM_APG(pool->base.hpo_frl_stream_enc[i]->apg));
1648 pool->base.hpo_frl_stream_enc[i]->apg = NULL;
1649 }
1650 kfree(DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1651 pool->base.hpo_frl_stream_enc[i] = NULL;
1652 }
1653 }
1654
1655 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1656 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1657 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1658 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1659 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1660 }
1661 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1662 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1663 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1664 }
1665 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1666 pool->base.hpo_dp_stream_enc[i] = NULL;
1667 }
1668 }
1669
1670 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1671 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1672 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1673 pool->base.hpo_dp_link_enc[i] = NULL;
1674 }
1675 }
1676
1677 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1678 if (pool->base.dscs[i] != NULL)
1679 dcn60_dsc_destroy(&pool->base.dscs[i]);
1680 }
1681
1682 if (pool->base.mpc != NULL) {
1683 kfree(TO_DCN20_MPC(pool->base.mpc));
1684 pool->base.mpc = NULL;
1685 }
1686 if (pool->base.hubbub != NULL) {
1687 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1688 pool->base.hubbub = NULL;
1689 }
1690 for (i = 0; i < pool->base.pipe_count; i++) {
1691 if (pool->base.dpps[i] != NULL)
1692 dcn60_dpp_destroy(&pool->base.dpps[i]);
1693
1694 if (pool->base.ipps[i] != NULL)
1695 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1696
1697 if (pool->base.hubps[i] != NULL) {
1698 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1699 pool->base.hubps[i] = NULL;
1700 }
1701
1702 if (pool->base.irqs != NULL) {
1703 dal_irq_service_destroy(&pool->base.irqs);
1704 }
1705 }
1706
1707 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) {
1708 if (pool->base.engines[i] != NULL)
1709 dce110_engine_destroy(&pool->base.engines[i]);
1710 }
1711
1712 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1713 if (pool->base.hw_i2cs[i] != NULL) {
1714 kfree(pool->base.hw_i2cs[i]);
1715 pool->base.hw_i2cs[i] = NULL;
1716 }
1717 if (pool->base.sw_i2cs[i] != NULL) {
1718 kfree(pool->base.sw_i2cs[i]);
1719 pool->base.sw_i2cs[i] = NULL;
1720 }
1721 }
1722
1723 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1724 if (pool->base.opps[i] != NULL)
1725 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1726 }
1727
1728 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1729 if (pool->base.timing_generators[i] != NULL) {
1730 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1731 pool->base.timing_generators[i] = NULL;
1732 }
1733 }
1734
1735 for (i = 0; i < pool->base.audio_count; i++) {
1736 if (pool->base.audios[i])
1737 dce_aud_destroy(&pool->base.audios[i]);
1738 }
1739
1740 for (i = 0; i < pool->base.clk_src_count; i++) {
1741 if (pool->base.clock_sources[i] != NULL) {
1742 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1743 pool->base.clock_sources[i] = NULL;
1744 }
1745 }
1746
1747 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1748 if (pool->base.mpc_lut[i] != NULL) {
1749 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1750 pool->base.mpc_lut[i] = NULL;
1751 }
1752 if (pool->base.mpc_shaper[i] != NULL) {
1753 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1754 pool->base.mpc_shaper[i] = NULL;
1755 }
1756 }
1757
1758 if (pool->base.dp_clock_source != NULL) {
1759 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1760 pool->base.dp_clock_source = NULL;
1761 }
1762
1763 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1764 if (pool->base.multiple_abms[i] != NULL)
1765 dce_abm_destroy(&pool->base.multiple_abms[i]);
1766 }
1767
1768 if (pool->base.psr != NULL)
1769 dmub_psr_destroy(&pool->base.psr);
1770
1771 if (pool->base.dccg != NULL)
1772 dcn_dccg_destroy(&pool->base.dccg);
1773
1774 if (pool->base.oem_device != NULL) {
1775 struct dc *dc = pool->base.oem_device->ctx->dc;
1776
1777 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1778 }
1779 }
1780
dcn60_dsc_create(struct dc_context * ctx,uint32_t inst)1781 static struct display_stream_compressor *dcn60_dsc_create(
1782 struct dc_context *ctx, uint32_t inst)
1783 {
1784 struct dcn60_dsc *dsc =
1785 kzalloc_obj(struct dcn60_dsc);
1786
1787 if (!dsc) {
1788 BREAK_TO_DEBUGGER();
1789 return NULL;
1790 }
1791
1792 #undef REG_STRUCT
1793 #define REG_STRUCT dsc_regs
1794 dsc_regs_init(0),
1795 dsc_regs_init(1),
1796 dsc_regs_init(2),
1797 dsc_regs_init(3);
1798
1799 dsc60_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1800
1801 //dsc->max_image_width = 6016;
1802 dsc->max_image_width = 5760;
1803
1804 return &dsc->base;
1805 }
1806
dcn60_destroy_resource_pool(struct resource_pool ** pool)1807 static void dcn60_destroy_resource_pool(struct resource_pool **pool)
1808 {
1809 struct dcn60_resource_pool *dcn60_pool = TO_DCN60_RES_POOL(*pool);
1810
1811 dcn60_resource_destruct(dcn60_pool);
1812 kfree(dcn60_pool);
1813 *pool = NULL;
1814 }
1815
1816 static struct dc_cap_funcs cap_funcs = {
1817 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1818 };
1819
dcn60_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)1820 static void dcn60_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
1821 {
1822 (void)bw_params;
1823 dc_assert_fp_enabled();
1824
1825 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1826 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1827
1828 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1829 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1830 }
1831
dcn60_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1832 static void dcn60_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1833 {
1834 DC_FP_START();
1835 dcn60_update_bw_bounding_box_fpu(dc, bw_params);
1836 DC_FP_END();
1837 }
1838
dcn60_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1839 static void dcn60_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1840 {
1841 const struct dc_stream_state *stream = pipe_ctx->stream;
1842 struct dc_link *link = stream->link;
1843 struct link_encoder *link_enc = NULL;
1844 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1845
1846 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1847
1848 link_enc = link_enc_cfg_get_link_enc(link);
1849 if (link_enc)
1850 pixel_clk_params->encoder_object_id = link_enc->id;
1851
1852 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1853 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1854 /* TODO: un-hardcode*/
1855
1856 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1857
1858 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1859 LINK_RATE_REF_FREQ_IN_KHZ;
1860 pixel_clk_params->flags.ENABLE_SS = 0;
1861 pixel_clk_params->color_depth =
1862 stream->timing.display_color_depth;
1863 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1864 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1865
1866 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1867 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1868
1869 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1870 pixel_clk_params->requested_pix_clk_100hz *= 2;
1871 if (dc_is_tmds_signal(stream->signal) &&
1872 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1873 pixel_clk_params->requested_pix_clk_100hz /= 2;
1874
1875 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1876 pipe_ctx->clock_source,
1877 &pipe_ctx->stream_res.pix_clk_params,
1878 &pipe_ctx->pll_settings);
1879
1880 pixel_clk_params->dio_se_pix_per_cycle = 1;
1881 if (dc_is_tmds_signal(stream->signal) &&
1882 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1883 pixel_clk_params->dio_se_pix_per_cycle = 2;
1884 } else if (dc_is_dp_signal(stream->signal)) {
1885 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1886 if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1887 pixel_clk_params->dio_se_pix_per_cycle = 8;
1888 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1889 pixel_clk_params->dio_se_pix_per_cycle = 4;
1890 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1891 pixel_clk_params->dio_se_pix_per_cycle = 2;
1892 } else {
1893 pixel_clk_params->dio_se_pix_per_cycle = 1;
1894 }
1895 }
1896 }
1897
dcn60_get_power_profile(const struct dc_state * context)1898 static int dcn60_get_power_profile(const struct dc_state *context)
1899 {
1900 unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1901 int dpm_level = 0;
1902
1903 for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1904 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1905 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1906 break;
1907 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1908 dpm_level++;
1909 }
1910
1911 return dpm_level;
1912 }
1913
1914 static struct resource_funcs dcn60_res_pool_funcs = {
1915 .destroy = dcn60_destroy_resource_pool,
1916 .link_enc_create = dcn60_link_encoder_create,
1917 .link_enc_create_minimal = NULL,
1918 .hpo_frl_link_enc_create = dcn60_hpo_frl_link_encoder_create,
1919 .panel_cntl_create = dcn32_panel_cntl_create,
1920 .validate_bandwidth = dcn401_validate_bandwidth,
1921 .calculate_wm_and_dlg = NULL,
1922 .populate_dml_pipes = NULL,
1923 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1924 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1925 .release_pipe = dcn20_release_pipe,
1926 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1927 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1928 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1929 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1930 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1931 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1932 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1933 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1934 .update_bw_bounding_box = dcn60_update_bw_bounding_box,
1935 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1936 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1937 .add_phantom_pipes = dcn32_add_phantom_pipes,
1938 .build_pipe_pix_clk_params = dcn60_build_pipe_pix_clk_params,
1939 .get_power_profile = dcn60_get_power_profile,
1940 .program_mcache_pipe_config = dcn60_program_mcache_pipe_config,
1941 .get_default_tiling_info = dcn401_get_default_tiling_info
1942 };
1943
read_pipe_fuses(struct dc_context * ctx)1944 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1945 {
1946 (void)ctx;
1947 uint32_t value = 0; // CC_DC_PIPE_DIS in DCN6 only indicates DCN IP full fuse, not per pipe fuse
1948 return value;
1949 }
1950
dcn60_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn60_resource_pool * pool)1951 static bool dcn60_resource_construct(
1952 uint8_t num_virtual_links,
1953 struct dc *dc,
1954 struct dcn60_resource_pool *pool)
1955 {
1956 int i;
1957 unsigned int j;
1958 struct dc_context *ctx = dc->ctx;
1959 struct irq_service_init_data init_data;
1960 struct ddc_service_init_data ddc_init_data = {0};
1961 uint32_t pipe_fuses = 0;
1962 uint32_t num_pipes = 4;
1963
1964 #undef REG_STRUCT
1965 #define REG_STRUCT bios_regs
1966 bios_regs_init();
1967
1968 #undef REG_STRUCT
1969 #define REG_STRUCT clk_src_regs
1970 clk_src_regs_init(0, A),
1971 clk_src_regs_init(1, B),
1972 clk_src_regs_init(2, C),
1973 clk_src_regs_init(3, D);
1974
1975 #undef REG_STRUCT
1976 #define REG_STRUCT abm_regs
1977 abm_regs_init(0),
1978 abm_regs_init(1),
1979 abm_regs_init(2),
1980 abm_regs_init(3);
1981
1982 #undef REG_STRUCT
1983 #define REG_STRUCT dccg_regs
1984 dccg_regs_init();
1985
1986 ctx->dc_bios->regs = &bios_regs;
1987
1988 pool->base.res_cap = &res_cap_dcn6_0;
1989
1990 /* max number of pipes for ASIC before checking for pipe fuses */
1991 num_pipes = pool->base.res_cap->num_timing_generator;
1992 pipe_fuses = read_pipe_fuses(ctx);
1993
1994 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1995 if (pipe_fuses & 1 << i)
1996 num_pipes--;
1997
1998 if (pipe_fuses & 1)
1999 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2000
2001 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2002 ASSERT(0); //Entire DCN is harvested!
2003
2004 pool->base.funcs = &dcn60_res_pool_funcs;
2005
2006 /*************************************************
2007 * Resource + asic cap harcoding *
2008 *************************************************/
2009 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2010 pool->base.timing_generator_count = num_pipes;
2011 pool->base.pipe_count = num_pipes;
2012 pool->base.mpcc_count = num_pipes;
2013 dc->caps.max_downscale_ratio = 600;
2014 dc->caps.i2c_speed_in_khz = 95;
2015 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
2016 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
2017 dc->caps.max_cursor_size = 64;
2018 dc->caps.cursor_not_scaled = true;
2019 dc->caps.min_horizontal_blanking_period = 80;
2020 dc->caps.dmdata_alloc_size = 2048;
2021 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2022 dc->caps.cache_line_size = 64;
2023 dc->caps.cache_num_ways = 16;
2024
2025 dc->caps.max_slave_planes = 2;
2026 dc->caps.max_slave_yuv_planes = 2;
2027 dc->caps.max_slave_rgb_planes = 2;
2028 dc->caps.post_blend_color_processing = true;
2029 dc->caps.force_dp_tps4_for_cp2520 = true;
2030 dc->caps.hdmi_hpo = true;
2031 dc->caps.dp_hpo = true;
2032 dc->caps.dp_hdmi21_pcon_support = true;
2033 dc->caps.edp_dsc_support = true;
2034 dc->caps.extended_aux_timeout_support = true;
2035 dc->caps.dmcub_support = true;
2036 dc->caps.max_v_total = (1 << 15) - 1;
2037
2038 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
2039 dc->caps.dcc_plane_width_limit = 7680;
2040
2041 /* Color pipeline capabilities */
2042 dc->caps.color.dpp.dcn_arch = 1;
2043 dc->caps.color.dpp.input_lut_shared = 0;
2044 dc->caps.color.dpp.icsc = 1;
2045 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2046 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2047 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2048 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2049 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2050 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2051 dc->caps.color.dpp.post_csc = 1;
2052 dc->caps.color.dpp.gamma_corr = 1;
2053 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2054 dc->caps.color.dpp.upsp_pre_scaler = 1;
2055
2056 dc->caps.color.dpp.hw_3d_lut = 0;
2057 dc->caps.color.dpp.ogam_ram = 0;
2058 // no OGAM ROM on DCN2 and later ASICs
2059 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2060 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2061 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2062 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2063 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2064 dc->caps.color.dpp.ocsc = 0;
2065
2066 dc->caps.color.mpc.gamut_remap = 1;
2067 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2068 dc->caps.color.mpc.ogam_ram = 1;
2069 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2070 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2071 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2072 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2073 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2074 dc->caps.color.mpc.ocsc = 1;
2075 dc->caps.color.mpc.preblend = true;
2076 /* HACK: Force FRL support until BIOS is ready. */
2077 dc->config.force_hdmi21_frl_enc_enable = true;
2078 dc->config.use_spl = true;
2079 dc->config.prefer_easf = true;
2080
2081 dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
2082 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
2083 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
2084 dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
2085 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
2086 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
2087 dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
2088 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
2089 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
2090
2091 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
2092 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
2093 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
2094 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
2095 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
2096 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
2097 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
2098 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
2099 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
2100
2101 dc->config.enable_cursor_offload = true;
2102 dc->config.dc_mode_clk_limit_support = true;
2103 dc->config.enable_windowed_mpo_odm = true;
2104 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
2105 dc->config.dp_connector_no_native_i2c = true;
2106 /* read VBIOS LTTPR caps */
2107 {
2108 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2109 enum bp_result bp_query_result;
2110 uint8_t is_vbios_lttpr_enable = 0;
2111
2112 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2113 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2114 }
2115
2116 /* interop bit is implicit */
2117 {
2118 dc->caps.vbios_lttpr_aware = true;
2119 }
2120 }
2121 dc->check_config = config_defaults;
2122
2123 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2124 dc->debug = debug_defaults_drv;
2125
2126 // Init the vm_helper
2127 if (dc->vm_helper)
2128 vm_helper_init(dc->vm_helper, 16);
2129
2130 /*************************************************
2131 * Create resources *
2132 *************************************************/
2133
2134 /* Clock Sources for Pixel Clock*/
2135 pool->base.clock_sources[DCN60_CLK_SRC_PLL0] =
2136 dcn60_clock_source_create(ctx, ctx->dc_bios,
2137 CLOCK_SOURCE_COMBO_PHY_PLL0,
2138 &clk_src_regs[0], false);
2139 pool->base.clock_sources[DCN60_CLK_SRC_PLL1] =
2140 dcn60_clock_source_create(ctx, ctx->dc_bios,
2141 CLOCK_SOURCE_COMBO_PHY_PLL1,
2142 &clk_src_regs[1], false);
2143 pool->base.clock_sources[DCN60_CLK_SRC_PLL2] =
2144 dcn60_clock_source_create(ctx, ctx->dc_bios,
2145 CLOCK_SOURCE_COMBO_PHY_PLL2,
2146 &clk_src_regs[2], false);
2147 pool->base.clock_sources[DCN60_CLK_SRC_PLL3] =
2148 dcn60_clock_source_create(ctx, ctx->dc_bios,
2149 CLOCK_SOURCE_COMBO_PHY_PLL3,
2150 &clk_src_regs[3], false);
2151 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
2152 // dcn60_clock_source_create(ctx, ctx->dc_bios,
2153 // CLOCK_SOURCE_COMBO_PHY_PLL4,
2154 // &clk_src_regs[4], false);
2155
2156 pool->base.clk_src_count = DCN60_CLK_SRC_TOTAL;
2157
2158 /* todo: not reuse phy_pll registers */
2159 pool->base.dp_clock_source =
2160 dcn60_clock_source_create(ctx, ctx->dc_bios,
2161 CLOCK_SOURCE_ID_DP_DTO,
2162 &clk_src_regs[0], true);
2163
2164 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2165 if (pool->base.clock_sources[i] == NULL) {
2166 dm_error("DC: failed to create clock sources!\n");
2167 BREAK_TO_DEBUGGER();
2168 goto create_fail;
2169 }
2170 }
2171
2172 /* DCCG */
2173 pool->base.dccg = dccg60_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2174 if (pool->base.dccg == NULL) {
2175 dm_error("DC: failed to create dccg!\n");
2176 BREAK_TO_DEBUGGER();
2177 goto create_fail;
2178 }
2179
2180 /* IRQ Service */
2181 init_data.ctx = dc->ctx;
2182 pool->base.irqs = dal_irq_service_dcn60_create(&init_data);
2183 if (!pool->base.irqs)
2184 goto create_fail;
2185
2186 /* HUBBUB */
2187 pool->base.hubbub = dcn60_hubbub_create(ctx);
2188 if (pool->base.hubbub == NULL) {
2189 BREAK_TO_DEBUGGER();
2190 dm_error("DC: failed to create hubbub!\n");
2191 goto create_fail;
2192 }
2193
2194 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2195 for (i = 0, j = 0; i < (int)pool->base.res_cap->num_timing_generator; i++) {
2196
2197 /* if pipe is disabled, skip instance of HW pipe,
2198 * i.e, skip ASIC register instance
2199 */
2200 if (pipe_fuses & 1 << i)
2201 continue;
2202 pool->base.hubps[j] = dcn60_hubp_create(ctx, i);
2203 if (pool->base.hubps[j] == NULL) {
2204 BREAK_TO_DEBUGGER();
2205 dm_error(
2206 "DC: failed to create hubps!\n");
2207 goto create_fail;
2208 }
2209
2210 pool->base.dpps[j] = dcn60_dpp_create(ctx, i);
2211 if (pool->base.dpps[j] == NULL) {
2212 BREAK_TO_DEBUGGER();
2213 dm_error(
2214 "DC: failed to create dpps!\n");
2215 goto create_fail;
2216 }
2217
2218 pool->base.opps[j] = dcn60_opp_create(ctx, i);
2219 if (pool->base.opps[j] == NULL) {
2220 BREAK_TO_DEBUGGER();
2221 dm_error(
2222 "DC: failed to create output pixel processor!\n");
2223 goto create_fail;
2224 }
2225
2226 pool->base.timing_generators[j] = dcn60_timing_generator_create(
2227 ctx, i);
2228 if (pool->base.timing_generators[j] == NULL) {
2229 BREAK_TO_DEBUGGER();
2230 dm_error("DC: failed to create tg!\n");
2231 goto create_fail;
2232 }
2233
2234 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2235 &abm_regs[i],
2236 &abm_shift,
2237 &abm_mask);
2238 if (pool->base.multiple_abms[j] == NULL) {
2239 dm_error("DC: failed to create abm for pipe %d!\n", i);
2240 BREAK_TO_DEBUGGER();
2241 goto create_fail;
2242 }
2243
2244 /* index for resource pool arrays for next valid pipe */
2245 j++;
2246 }
2247
2248 /* PSR */
2249 pool->base.psr = dmub_psr_create(ctx);
2250 if (pool->base.psr == NULL) {
2251 dm_error("DC: failed to create psr obj!\n");
2252 BREAK_TO_DEBUGGER();
2253 goto create_fail;
2254 }
2255
2256 /* MPCCs */
2257 pool->base.mpc = dcn60_mpc_create(ctx, pool->base.res_cap->num_timing_generator,
2258 pool->base.res_cap->num_mpc_3dlut);
2259 if (pool->base.mpc == NULL) {
2260 BREAK_TO_DEBUGGER();
2261 dm_error("DC: failed to create mpc!\n");
2262 goto create_fail;
2263 }
2264
2265 /* DSCs */
2266 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2267 pool->base.dscs[i] = dcn60_dsc_create(ctx, i);
2268 if (pool->base.dscs[i] == NULL) {
2269 BREAK_TO_DEBUGGER();
2270 dm_error("DC: failed to create display stream compressor %d!\n", i);
2271 goto create_fail;
2272 }
2273 }
2274
2275 /* AUX */
2276 for (i = 0; i < pool->base.res_cap->num_aux; i++) {
2277 pool->base.engines[i] = dcn60_aux_engine_create(ctx, i);
2278 if (pool->base.engines[i] == NULL) {
2279 BREAK_TO_DEBUGGER();
2280 dm_error(
2281 "DC:failed to create aux engine!!\n");
2282 goto create_fail;
2283 }
2284 }
2285
2286 /* I2C */
2287 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2288 pool->base.hw_i2cs[i] = dcn60_i2c_hw_create(ctx, i);
2289 if (pool->base.hw_i2cs[i] == NULL) {
2290 BREAK_TO_DEBUGGER();
2291 dm_error(
2292 "DC:failed to create hw i2c!!\n");
2293 goto create_fail;
2294 }
2295 pool->base.sw_i2cs[i] = NULL;
2296 }
2297
2298 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2299 if (!resource_construct(num_virtual_links, dc, &pool->base,
2300 &res_create_funcs))
2301 goto create_fail;
2302
2303 /* HW Sequencer init functions and Plane caps */
2304 dcn60_hw_sequencer_init_functions(dc);
2305
2306 dc->caps.max_planes = pool->base.pipe_count;
2307
2308 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2309 dc->caps.planes[i] = plane_cap;
2310
2311 dc->caps.max_odm_combine_factor = 4;
2312
2313 dc->cap_funcs = cap_funcs;
2314
2315 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2316 ddc_init_data.ctx = dc->ctx;
2317 ddc_init_data.link = NULL;
2318 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2319 ddc_init_data.id.enum_id = 0;
2320 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2321 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2322 } else {
2323 pool->base.oem_device = NULL;
2324 }
2325
2326 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2327 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2328 dc->config.sdpif_request_limit_words_per_umc = 16;
2329
2330 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2331 dc->dml2_options.use_native_soc_bb_construction = true;
2332 dc->dml2_options.minimize_dispclk_using_odm = true;
2333 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2334 dc->dml2_options.force_tdlut_enable = true;
2335
2336 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2337 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch =
2338 &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2339
2340 dc->dml2_options.max_segments_per_hubp = 20;
2341 dc->dml2_options.det_segment_size = DCN6_0_CRB_SEGMENT_SIZE_KB;
2342
2343 /* SPL */
2344 dc->caps.scl_caps.sharpener_support = true;
2345
2346 /* init DC limited DML2 options */
2347 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2348 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2349
2350 return true;
2351
2352 create_fail:
2353
2354 dcn60_resource_destruct(pool);
2355
2356 return false;
2357 }
2358
dcn60_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2359 struct resource_pool *dcn60_create_resource_pool(
2360 const struct dc_init_data *init_data,
2361 struct dc *dc)
2362 {
2363 struct dcn60_resource_pool *pool =
2364 kzalloc_obj(struct dcn60_resource_pool);
2365
2366 if (!pool)
2367 return NULL;
2368
2369 if (dcn60_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2370 return &pool->base;
2371
2372 BREAK_TO_DEBUGGER();
2373 kfree(pool);
2374 return NULL;
2375 }
2376