1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright 2026 Advanced Micro Devices, Inc. 5 */ 6 7 #include "dm_services.h" 8 #include "dc.h" 9 10 #include "dcn32/dcn32_init.h" 11 #include "dcn42/dcn42_init.h" 12 #include "dcn42b/dcn42b_init.h" 13 14 #include "resource.h" 15 #include "include/irq_service_interface.h" 16 17 #include "dcn42b_resource.h" 18 #include "dcn20/dcn20_resource.h" 19 #include "dcn30/dcn30_resource.h" 20 #include "dcn31/dcn31_resource.h" 21 #include "dcn32/dcn32_resource.h" 22 #include "dcn35/dcn35_resource.h" 23 #include "dcn321/dcn321_resource.h" 24 #include "dcn401/dcn401_resource.h" 25 #include "dcn42/dcn42_resource_fpu.h" 26 27 #include "dcn10/dcn10_ipp.h" 28 #include "dcn35/dcn35_hubbub.h" 29 #include "dcn42/dcn42_hubbub.h" 30 #include "dcn401/dcn401_mpc.h" 31 #include "dcn42/dcn42_mpc.h" 32 #include "dcn35/dcn35_hubp.h" 33 #include "dcn42/dcn42_hubp.h" 34 #include "irq/dcn42/irq_service_dcn42.h" 35 #include "dcn42/dcn42_dpp.h" 36 #include "dcn401/dcn401_dsc.h" 37 #include "dcn42/dcn42_optc.h" 38 #include "dcn20/dcn20_hwseq.h" 39 #include "dcn30/dcn30_hwseq.h" 40 #include "dce110/dce110_hwseq.h" 41 #include "dcn35/dcn35_opp.h" 42 #include "dcn30/dcn30_vpg.h" 43 #include "dcn31/dcn31_vpg.h" 44 #include "dcn42/dcn42_dio_stream_encoder.h" 45 #include "dcn42/dcn42_pg_cntl.h" 46 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 47 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 48 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 49 #include "dcn42/dcn42_hpo_dp_link_encoder.h" 50 #include "dcn31/dcn31_apg.h" 51 #include "dcn31/dcn31_dio_link_encoder.h" 52 #include "dcn401/dcn401_dio_link_encoder.h" 53 #include "dcn10/dcn10_link_encoder.h" 54 #include "dcn321/dcn321_dio_link_encoder.h" 55 #include "dce/dce_clock_source.h" 56 #include "dce/dce_audio.h" 57 #include "dce/dce_hwseq.h" 58 #include "clk_mgr.h" 59 #include "dio/virtual/virtual_stream_encoder.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn42/dcn42_dccg.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "link_service.h" 64 #include "dcn31/dcn31_panel_cntl.h" 65 66 #include "dcn30/dcn30_dwb.h" 67 #include "dcn42/dcn42_mmhubbub.h" 68 #include "dcn42/dcn42_dio_link_encoder.h" 69 70 #include "dcn/dcn_4_2_1_offset.h" 71 #include "dcn/dcn_4_2_1_sh_mask.h" 72 #include "dpcs/dpcs_4_0_1_offset.h" 73 #include "dpcs/dpcs_4_0_1_sh_mask.h" 74 75 #include "reg_helper.h" 76 #include "dce/dmub_abm.h" 77 #include "dce/dmub_psr.h" 78 #include "dce/dmub_replay.h" 79 #include "dce/dce_aux.h" 80 #include "dce/dce_i2c.h" 81 82 #include "dml/dcn30/display_mode_vba_30.h" 83 #include "vm_helper.h" 84 #include "dcn20/dcn20_vmid.h" 85 86 #include "dc_state_priv.h" 87 #include "link_enc_cfg.h" 88 89 #include "dml2_0/dml2_wrapper.h" 90 91 #define DC_LOGGER_INIT(logger) 92 93 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b 94 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1 95 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e 96 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1 97 98 #define regAPG0_APG_DBG_GEN_CONTROL 0x2075 99 #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 100 #define regAPG1_APG_DBG_GEN_CONTROL 0x2199 101 #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 102 #define regAPG2_APG_DBG_GEN_CONTROL 0x22bd 103 #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 104 #define regAPG3_APG_DBG_GEN_CONTROL 0x23e1 105 #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 106 #define regAPG4_APG_DBG_GEN_CONTROL 0x2505 107 #define regAPG4_APG_DBG_GEN_CONTROL_BASE_IDX 2 108 #define regAPG5_APG_DBG_GEN_CONTROL 0x0915 109 #define regAPG5_APG_DBG_GEN_CONTROL_BASE_IDX 3 110 #define regAPG6_APG_DBG_GEN_CONTROL 0x3632 111 #define regAPG6_APG_DBG_GEN_CONTROL_BASE_IDX 2 112 #define regAPG7_APG_DBG_GEN_CONTROL 0x3706 113 #define regAPG7_APG_DBG_GEN_CONTROL_BASE_IDX 2 114 #define regAPG8_APG_DBG_GEN_CONTROL 0x37da 115 #define regAPG8_APG_DBG_GEN_CONTROL_BASE_IDX 2 116 #define regAPG9_APG_DBG_GEN_CONTROL 0x38ae 117 #define regAPG9_APG_DBG_GEN_CONTROL_BASE_IDX 2 118 119 enum dcn401_clk_src_array_id { 120 DCN401_CLK_SRC_PLL0, 121 DCN401_CLK_SRC_PLL1, 122 DCN401_CLK_SRC_PLL2, 123 DCN401_CLK_SRC_TOTAL 124 }; 125 126 /* begin 127 * macros to expend register list macro defined in HW object header file 128 */ 129 130 /* DCN */ 131 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 132 133 #define BASE(seg) BASE_INNER(seg) 134 135 #define SR(reg_name) \ 136 REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 137 reg##reg_name 138 #define SR_ARR(reg_name, id) \ 139 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 140 reg##reg_name 141 #define SR_ARR_INIT(reg_name, id, value) \ 142 REG_STRUCT[id].reg_name = value 143 144 #define SRI(reg_name, block, id) \ 145 REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 146 reg##block##id##_##reg_name 147 148 #define SRI_ARR(reg_name, block, id) \ 149 REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 150 reg##block##id##_##reg_name 151 152 /* 153 * Used when a reg_name would otherwise begin with an integer 154 */ 155 #define SRI_ARR_US(reg_name, block, id) \ 156 REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ 157 reg##block##id##reg_name 158 #define SR_ARR_I2C(reg_name, id) \ 159 REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 160 161 #define SRI_ARR_I2C(reg_name, block, id) \ 162 REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 163 reg##block##id##_##reg_name 164 165 #define SRI_ARR_ALPHABET(reg_name, block, index, id) \ 166 REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 167 reg##block##id##_##reg_name 168 169 #define SRI2(reg_name, block, id) \ 170 .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 171 reg##reg_name 172 #define SRI2_ARR(reg_name, block, id) \ 173 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ 174 reg##reg_name 175 176 #define SRIR(var_name, reg_name, block, id) \ 177 .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 178 reg##block##id##_##reg_name 179 180 #define SRII(reg_name, block, id) \ 181 REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 182 reg##block##id##_##reg_name 183 184 #define SRII_ARR_2(reg_name, block, id, inst) \ 185 REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 186 reg##block##id##_##reg_name 187 188 #define SRII_MPC_RMU(reg_name, block, id) \ 189 .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 190 reg##block##id##_##reg_name 191 192 #define SRII_DWB(reg_name, temp_name, block, id) \ 193 REG_STRUCT.reg_name[id] = \ 194 BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ 195 reg##block##id##_##temp_name 196 197 #define DCCG_SRII(reg_name, block, id) \ 198 REG_STRUCT.block##_##reg_name[id] = \ 199 BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ 200 reg##block##id##_##reg_name 201 202 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 203 .field_name = reg_name##__##field_name##post_fix 204 205 #define VUPDATE_SRII(reg_name, block, id) \ 206 REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ 207 reg##reg_name##_##block##id 208 209 /* NBIO */ 210 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 211 212 #define NBIO_BASE(seg) \ 213 NBIO_BASE_INNER(seg) 214 215 #define NBIO_SR(reg_name) \ 216 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_##reg_name##_BASE_IDX) + \ 217 regBIF_BX1_##reg_name 218 #define NBIO_SR_ARR(reg_name, id) \ 219 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_##reg_name##_BASE_IDX) + \ 220 regBIF_BX1_##reg_name 221 222 #define CTX ctx 223 #define REG(reg_name) \ 224 (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) 225 226 static struct bios_registers bios_regs; 227 228 #define bios_regs_init() \ 229 NBIO_SR(BIOS_SCRATCH_3), \ 230 NBIO_SR(BIOS_SCRATCH_6) 231 232 #define clk_src_regs_init(index, pllid) \ 233 CS_COMMON_REG_LIST_DCN42B_RI(index, pllid) 234 235 static struct dce110_clk_src_regs clk_src_regs[5]; 236 237 static const struct dce110_clk_src_shift cs_shift = { 238 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 239 }; 240 static const struct dce110_clk_src_mask cs_mask = { 241 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 242 }; 243 #define abm_regs_init(id) \ 244 ABM_DCN42B_REG_LIST_RI(id) 245 246 static struct dce_abm_registers abm_regs[4]; 247 248 static const struct dce_abm_shift abm_shift = { 249 ABM_MASK_SH_LIST_DCN42(__SHIFT)}; 250 251 static const struct dce_abm_mask abm_mask = { 252 ABM_MASK_SH_LIST_DCN42(_MASK)}; 253 254 #define audio_regs_init(id) \ 255 AUD_COMMON_REG_LIST_RI(id) 256 257 static struct dce_audio_registers audio_regs[5]; 258 259 /* DTO2 not present for DCN42b */ 260 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh) \ 261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh), \ 262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh), \ 263 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh), \ 264 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh), \ 265 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh), \ 266 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh), \ 267 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh), \ 268 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh), \ 269 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh), \ 270 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh), \ 271 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh), \ 272 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh), \ 273 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) 274 275 static const struct dce_audio_shift audio_shift = { 276 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)}; 277 278 static const struct dce_audio_mask audio_mask = { 279 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)}; 280 281 #define vpg_regs_init(id) \ 282 VPG_DCN401_REG_LIST_RI(id) 283 284 static struct dcn31_vpg_registers vpg_regs[10]; 285 286 static const struct dcn31_vpg_shift vpg_shift = { 287 DCN31_VPG_MASK_SH_LIST(__SHIFT)}; 288 289 static const struct dcn31_vpg_mask vpg_mask = { 290 DCN31_VPG_MASK_SH_LIST(_MASK)}; 291 292 #define apg_regs_init(id) \ 293 APG_DCN31_REG_LIST_RI(id) 294 295 static struct dcn31_apg_registers apg_regs[10]; 296 297 static const struct dcn31_apg_shift apg_shift = { 298 DCN42B_APG_MASK_SH_LIST(__SHIFT)}; 299 300 static const struct dcn31_apg_mask apg_mask = { 301 DCN42B_APG_MASK_SH_LIST(_MASK)}; 302 303 #define stream_enc_regs_init(id) \ 304 SE_DCN42B_REG_LIST_RI(id) 305 306 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 307 308 static const struct dcn10_stream_encoder_shift se_shift = { 309 SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; 310 311 static const struct dcn10_stream_encoder_mask se_mask = { 312 SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; 313 314 #define aux_regs_init(id) \ 315 DCN2_AUX_REG_LIST_RI(id) 316 317 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 318 319 #define hpd_regs_init(id) \ 320 HPD_REG_LIST_RI(id) 321 322 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 323 324 #define link_regs_init(id, phyid) \ 325 LE_DCN401_REG_LIST_RI(id) 326 327 static struct dcn10_link_enc_registers link_enc_regs[5]; 328 329 static const struct dcn10_link_enc_shift le_shift = { 330 LINK_ENCODER_MASK_SH_LIST_DCN42B(__SHIFT)}; 331 332 static const struct dcn10_link_enc_mask le_mask = { 333 LINK_ENCODER_MASK_SH_LIST_DCN42B(_MASK)}; 334 335 #define hpo_dp_stream_encoder_reg_init(id) \ 336 DCN42B_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 337 338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 339 340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 341 DCN4_2B_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; 342 343 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 344 DCN4_2B_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; 345 346 #define hpo_dp_link_encoder_reg_init(id) \ 347 DCN42B_HPO_DP_LINK_ENC_REG_LIST_RI(id) 348 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 349 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 350 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 351 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 352 353 /* DCN42B has 2 HPO DP link encoders */ 354 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 355 356 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 357 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; 358 359 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 360 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; 361 362 #define dpp_regs_init(id) \ 363 DPP_REG_LIST_DCN42B_COMMON_RI(id) 364 365 static struct dcn42_dpp_registers dpp_regs[4]; 366 367 static const struct dcn42_dpp_shift tf_shift = { 368 DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; 369 370 static const struct dcn42_dpp_mask tf_mask = { 371 DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; 372 373 #define opp_regs_init(id) \ 374 OPP_REG_LIST_DCN401_RI(id) 375 376 static struct dcn20_opp_registers opp_regs[4]; 377 378 static const struct dcn20_opp_shift opp_shift = { 379 OPP_MASK_SH_LIST_DCN20(__SHIFT)}; 380 381 static const struct dcn20_opp_mask opp_mask = { 382 OPP_MASK_SH_LIST_DCN20(_MASK)}; 383 384 #define aux_engine_regs_init(id) \ 385 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 386 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 387 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ 388 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) 389 390 static struct dce110_aux_registers aux_engine_regs[5]; 391 392 static const struct dce110_aux_registers_shift aux_shift = { 393 DCN_AUX_MASK_SH_LIST(__SHIFT)}; 394 395 static const struct dce110_aux_registers_mask aux_mask = { 396 DCN_AUX_MASK_SH_LIST(_MASK)}; 397 398 #define dwbc_regs_dcn401_init(id) \ 399 DWBC_COMMON_REG_LIST_DCN30_RI(id) 400 401 static struct dcn30_dwbc_registers dwbc401_regs[1]; 402 403 static const struct dcn30_dwbc_shift dwbc401_shift = { 404 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; 405 406 static const struct dcn30_dwbc_mask dwbc401_mask = { 407 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; 408 409 #define mcif_wb_regs_dcn3_init(id) \ 410 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) 411 412 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; 413 414 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { 415 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; 416 417 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { 418 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; 419 420 #define dsc_regs_init(id) \ 421 DSC_REG_LIST_DCN401_RI(id) 422 423 static struct dcn401_dsc_registers dsc_regs[4]; 424 425 static const struct dcn401_dsc_shift dsc_shift = { 426 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; 427 428 static const struct dcn401_dsc_mask dsc_mask = { 429 DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; 430 431 static struct dcn42_mpc_registers mpc_regs; 432 433 #define dcn_mpc_regs_init() \ 434 MPC_REG_LIST_DCN42(0), \ 435 MPC_REG_LIST_DCN42(1), \ 436 MPC_REG_LIST_DCN42(2), \ 437 MPC_REG_LIST_DCN42(3), \ 438 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ 439 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ 440 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ 441 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ 442 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ 443 MPC_RMCM_REG_LIST_DCN42(0), \ 444 MPC_RMCM_REG_LIST_DCN42(1) 445 446 static const struct dcn42_mpc_shift mpc_shift = { 447 MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; 448 449 static const struct dcn42_mpc_mask mpc_mask = { 450 MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; 451 452 #define optc_regs_init(id) \ 453 OPTC_COMMON_REG_LIST_DCN42B_RI(id) 454 455 static struct dcn_optc_registers optc_regs[4]; 456 457 static const struct dcn_optc_shift optc_shift = { 458 OPTC_COMMON_MASK_SH_LIST_DCN42B(__SHIFT)}; 459 460 static const struct dcn_optc_mask optc_mask = { 461 OPTC_COMMON_MASK_SH_LIST_DCN42B(_MASK)}; 462 463 #define hubp_regs_init(id) \ 464 HUBP_REG_LIST_DCN42B_RI(id) 465 466 static struct dcn_hubp2_registers hubp_regs[4]; 467 468 static const struct dcn_hubp2_shift hubp_shift = { 469 HUBP_MASK_SH_LIST_DCN42B(__SHIFT)}; 470 471 static const struct dcn_hubp2_mask hubp_mask = { 472 HUBP_MASK_SH_LIST_DCN42B(_MASK)}; 473 474 static struct dcn_hubbub_registers hubbub_reg; 475 476 #define hubbub_reg_init() \ 477 HUBBUB_REG_LIST_DCN42B(0) 478 479 static const struct dcn_hubbub_shift hubbub_shift = { 480 HUBBUB_MASK_SH_LIST_DCN42B(__SHIFT)}; 481 482 static const struct dcn_hubbub_mask hubbub_mask = { 483 HUBBUB_MASK_SH_LIST_DCN42B(_MASK)}; 484 485 static struct dccg_registers dccg_regs; 486 487 #define dccg_regs_init() \ 488 DCCG_REG_LIST_DCN42B_RI() 489 490 static const struct dccg_shift dccg_shift = { 491 DCCG_MASK_SH_LIST_DCN42_COMMON(__SHIFT)}; 492 493 static const struct dccg_mask dccg_mask = { 494 DCCG_MASK_SH_LIST_DCN42_COMMON(_MASK)}; 495 496 static struct pg_cntl_registers pg_cntl_regs; 497 498 #define pg_cntl_dcn42b_regs_init() \ 499 PG_CNTL_REG_LIST_DCN42B() 500 501 static const struct pg_cntl_shift pg_cntl_shift = { 502 PG_CNTL_MASK_SH_LIST_DCN42B(__SHIFT) 503 }; 504 505 static const struct pg_cntl_mask pg_cntl_mask = { 506 PG_CNTL_MASK_SH_LIST_DCN42B(_MASK) 507 }; 508 #define SRII2(reg_name_pre, reg_name_post, id) \ 509 .reg_name_pre##_##reg_name_post[id] = \ 510 BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ 511 reg##reg_name_pre##id##_##reg_name_post 512 513 /* Not in DCN42B: 514 * SRII(PIXEL_RATE_CNTL, OTG, 3), 515 * SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3), 516 * SR(DOMAIN19_PG_CONFIG), 517 * SR(DOMAIN19_PG_STATUS), 518 */ 519 #define HWSEQ_DCN42B_REG_LIST() \ 520 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 521 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 522 SR(DIO_MEM_PWR_CTRL), \ 523 SR(ODM_MEM_PWR_CTRL3), \ 524 SR(MMHUBBUB_MEM_PWR_CNTL), \ 525 SR(DCCG_GATE_DISABLE_CNTL), \ 526 SR(DCCG_GATE_DISABLE_CNTL2), \ 527 SR(DCCG_GATE_DISABLE_CNTL4), \ 528 SR(DCCG_GATE_DISABLE_CNTL5), \ 529 SR(DCFCLK_CNTL), \ 530 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 531 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 532 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 533 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 534 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ 535 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ 536 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ 537 SR(MICROSECOND_TIME_BASE_DIV), \ 538 SR(MILLISECOND_TIME_BASE_DIV), \ 539 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 540 SR(RBBMIF_TIMEOUT_DIS), \ 541 SR(RBBMIF_TIMEOUT_DIS_2), \ 542 SR(DCHUBBUB_CRC_CTRL), \ 543 SR(DPP_TOP0_DPP_CRC_CTRL), \ 544 SR(DPP_TOP0_DPP_CRC_VAL_R), \ 545 SR(DPP_TOP0_DPP_CRC_VAL_G), \ 546 SR(DPP_TOP0_DPP_CRC_VAL_B), \ 547 SR(DPP_TOP0_DPP_CRC_VAL_A), \ 548 SR(MPC_CRC_CTRL), \ 549 SR(MPC_CRC_RESULT_R), \ 550 SR(MPC_CRC_RESULT_G), \ 551 SR(MPC_CRC_RESULT_B), \ 552 SR(MPC_CRC_RESULT_A), \ 553 SR(DOMAIN0_PG_CONFIG), \ 554 SR(DOMAIN1_PG_CONFIG), \ 555 SR(DOMAIN2_PG_CONFIG), \ 556 SR(DOMAIN3_PG_CONFIG), \ 557 SR(DOMAIN16_PG_CONFIG), \ 558 SR(DOMAIN17_PG_CONFIG), \ 559 SR(DOMAIN18_PG_CONFIG), \ 560 SR(DOMAIN22_PG_CONFIG), \ 561 SR(DOMAIN23_PG_CONFIG), \ 562 SR(DOMAIN24_PG_CONFIG), \ 563 SR(DOMAIN25_PG_CONFIG), \ 564 SR(DOMAIN26_PG_CONFIG), \ 565 SR(DOMAIN0_PG_STATUS), \ 566 SR(DOMAIN1_PG_STATUS), \ 567 SR(DOMAIN2_PG_STATUS), \ 568 SR(DOMAIN3_PG_STATUS), \ 569 SR(DOMAIN16_PG_STATUS), \ 570 SR(DOMAIN17_PG_STATUS), \ 571 SR(DOMAIN18_PG_STATUS), \ 572 SR(DOMAIN22_PG_STATUS), \ 573 SR(DOMAIN23_PG_STATUS), \ 574 SR(DOMAIN24_PG_STATUS), \ 575 SR(DOMAIN25_PG_STATUS), \ 576 SR(DOMAIN26_PG_STATUS), \ 577 SR(DC_IP_REQUEST_CNTL), \ 578 SR(AZALIA_AUDIO_DTO), \ 579 SR(HPO_TOP_HW_CONTROL), \ 580 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 581 SR(DMU_CLK_CNTL) 582 583 static struct dce_hwseq_registers hwseq_reg; 584 585 #define hwseq_reg_init() \ 586 HWSEQ_DCN42B_REG_LIST() 587 588 /* Not in DCN42B 589 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 590 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 591 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 592 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ 593 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh), \ 594 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh), \ 595 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh), \ 596 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh), \ 597 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh), \ 598 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh), \ 599 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh), \ 600 */ 601 #define HWSEQ_DCN42B_MASK_SH_LIST(mask_sh) \ 602 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 603 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 604 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 605 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 608 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 609 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 610 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 611 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 612 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 613 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 614 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 615 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 616 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 617 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 618 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 619 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 620 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 621 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 622 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 623 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 624 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 625 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 626 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 627 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 628 HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 629 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 630 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 631 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 632 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 633 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 634 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 635 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 636 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 637 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 638 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 639 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 640 HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 641 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 642 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 643 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ 644 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 645 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 646 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 647 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ 648 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ 649 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ 650 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 651 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 652 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 653 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 654 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 655 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 656 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 657 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 658 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 659 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 660 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 661 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 662 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 663 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 664 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 665 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 666 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 667 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 668 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 669 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 670 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 671 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 672 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ 673 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 674 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 675 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 676 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 677 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 678 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 679 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh) 680 681 static const struct dce_hwseq_shift hwseq_shift = { 682 HWSEQ_DCN42B_MASK_SH_LIST(__SHIFT)}; 683 684 static const struct dce_hwseq_mask hwseq_mask = { 685 HWSEQ_DCN42B_MASK_SH_LIST(_MASK)}; 686 687 #define vmid_regs_init(id) \ 688 DCN20_VMID_REG_LIST_RI(id) 689 690 static struct dcn_vmid_registers vmid_regs[16]; 691 692 static const struct dcn20_vmid_shift vmid_shifts = { 693 DCN20_VMID_MASK_SH_LIST(__SHIFT)}; 694 695 static const struct dcn20_vmid_mask vmid_masks = { 696 DCN20_VMID_MASK_SH_LIST(_MASK)}; 697 698 static const struct resource_caps res_cap_dcn42b = { 699 .num_timing_generator = 3, 700 .num_opp = 3, 701 .num_dpp = 4, 702 .num_video_plane = 4, 703 .num_audio = 4, 704 .num_stream_encoder = 3, 705 .num_dig_link_enc = 3, 706 // .num_usb4_dpia = 6, 707 .num_hpo_dp_stream_encoder = 3, 708 .num_hpo_dp_link_encoder = 2, 709 .num_pll = 3, 710 .num_dwb = 1, 711 .num_ddc = 0, 712 .num_vmid = 16, 713 .num_mpc_3dlut = 2, 714 .num_dsc = 3, 715 .num_rmcm = 2, 716 .num_mpc = 4, 717 .num_aux = 3, 718 }; 719 720 static const struct dc_plane_cap plane_cap = { 721 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 722 .per_pixel_alpha = true, 723 724 .pixel_format_support = { 725 .argb8888 = true, 726 .nv12 = true, 727 .fp16 = true, 728 .p010 = true, 729 .ayuv = false, 730 }, 731 732 .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, 733 734 // 6:1 downscaling ratio: 1000/6 = 166.666 735 .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, 736 737 .min_width = 64, 738 .min_height = 64}; 739 740 static const struct dc_debug_options debug_defaults_drv = { 741 .disable_dmcu = true, 742 .force_abm_enable = false, 743 .clock_trace = true, 744 .disable_pplib_clock_request = false, 745 .disable_dpp_power_gate = true, 746 .disable_hubp_power_gate = true, 747 .disable_optc_power_gate = true, 748 .pipe_split_policy = MPC_SPLIT_AVOID, 749 .force_single_disp_pipe_split = false, 750 .disable_dcc = DCC_ENABLE, 751 .vsr_support = true, 752 .performance_trace = false, 753 .max_downscale_src_width = 4096, /*up to 4K*/ 754 .disable_pplib_wm_range = false, 755 .scl_reset_length10 = true, 756 .sanity_checks = false, 757 .underflow_assert_delay_us = 0xFFFFFFFF, 758 .dwb_fi_phase = -1, // -1 = disable, 759 .dmub_command_table = true, 760 .pstate_enabled = false, 761 .enable_mem_low_power = { 762 .bits = { 763 .vga = false, 764 .i2c = true, 765 .dscl = true, 766 .cm = true, 767 .mpc = true, 768 .optc = true, 769 .vpg = true, 770 }}, 771 .root_clock_optimization = { 772 .bits = { 773 .dpp = false, 774 .dsc = false,/*dscclk and dsc pg*/ 775 .hdmistream = false, 776 .hdmichar = false, 777 .dpstream = false, 778 .symclk32_se = false, 779 .symclk32_le = false, 780 .symclk_fe = false, 781 .physymclk = false, 782 .dpiasymclk = false, 783 } 784 }, 785 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 786 .enable_z9_disable_interface = false, /* Allow support for the PMFW interface for disable Z9*/ 787 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ 788 .support_eDP1_5 = true, 789 .use_max_lb = true, 790 .force_disable_subvp = false, 791 .exit_idle_opt_for_cursor_updates = true, 792 .using_dml2 = true, 793 .using_dml21 = true, 794 .enable_single_display_2to1_odm_policy = true, 795 796 // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 797 .enable_double_buffered_dsc_pg_support = true, 798 .enable_dp_dig_pixel_rate_div_policy = 1, 799 .allow_sw_cursor_fallback = false, 800 .psp_disabled_wa = true, 801 .alloc_extra_way_for_cursor = true, 802 .min_prefetch_in_strobe_ns = 60000, // 60us 803 .disable_unbounded_requesting = false, 804 .dcc_meta_propagation_delay_us = 10, 805 .disable_timeout = true, 806 .min_disp_clk_khz = 50000, 807 .static_screen_wait_frames = 2, 808 .disable_z10 = true, 809 .ignore_pg = true, 810 .disable_stutter_for_wm_program = true, 811 .min_deep_sleep_dcfclk_khz = 8000, 812 .replay_skip_crtc_disabled = true, 813 .psr_skip_crtc_disable = true, 814 }; 815 816 static const struct dc_check_config config_defaults = { 817 .enable_legacy_fast_update = false, 818 }; 819 820 static struct dce_aux *dcn42b_aux_engine_create( 821 struct dc_context *ctx, 822 uint32_t inst) 823 { 824 struct aux_engine_dce110 *aux_engine = 825 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 826 827 if (!aux_engine) 828 return NULL; 829 830 #undef REG_STRUCT 831 #define REG_STRUCT aux_engine_regs 832 aux_engine_regs_init(0), 833 aux_engine_regs_init(1), 834 aux_engine_regs_init(2); 835 /* Not in DCN42B: 836 * aux_engine_regs_init(3), 837 * aux_engine_regs_init(4); 838 */ 839 dce110_aux_engine_construct(aux_engine, ctx, inst, 840 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 841 &aux_engine_regs[inst], 842 &aux_mask, 843 &aux_shift, 844 ctx->dc->caps.extended_aux_timeout_support); 845 846 return &aux_engine->base; 847 } 848 849 #define i2c_inst_regs_init(id) \ 850 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 851 852 static struct dce_i2c_registers i2c_hw_regs[5]; 853 854 static const struct dce_i2c_shift i2c_shifts = { 855 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 856 }; 857 static const struct dce_i2c_mask i2c_masks = { 858 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) 859 }; 860 861 /* ========================================================== */ 862 863 /* 864 * DPIA index | Preferred Encoder | Host Router 865 * 0 | C | 0 866 * 1 | First Available | 0 867 * 2 | D | 1 868 * 3 | First Available | 1 869 * 4 | E | 2 870 * 5 | First Available | 2 871 */ 872 /* ========================================================== */ 873 /* DPIA is not included in DCN42B */ 874 /* 875 static const enum engine_id dpia_to_preferred_enc_id_table[] = { 876 ENGINE_ID_DIGC, 877 ENGINE_ID_DIGC, 878 ENGINE_ID_DIGD, 879 ENGINE_ID_DIGD, 880 ENGINE_ID_DIGE, 881 ENGINE_ID_DIGE 882 }; 883 884 static enum engine_id dcn42b_get_preferred_eng_id_dpia(unsigned int dpia_index) 885 { 886 return dpia_to_preferred_enc_id_table[dpia_index]; 887 } 888 */ 889 890 static struct dce_i2c_hw *dcn42b_i2c_hw_create( 891 struct dc_context *ctx, 892 uint32_t inst) 893 { 894 struct dce_i2c_hw *dce_i2c_hw = 895 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 896 897 if (!dce_i2c_hw) 898 return NULL; 899 900 #undef REG_STRUCT 901 #define REG_STRUCT i2c_hw_regs 902 i2c_inst_regs_init(1); 903 /* Not in DCN42B: 904 * i2c_inst_regs_init(2), 905 * i2c_inst_regs_init(3), 906 * i2c_inst_regs_init(4), 907 * i2c_inst_regs_init(5); 908 */ 909 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 910 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 911 912 return dce_i2c_hw; 913 } 914 915 static struct clock_source *dcn42b_clock_source_create( 916 struct dc_context *ctx, 917 struct dc_bios *bios, 918 enum clock_source_id id, 919 const struct dce110_clk_src_regs *regs, 920 bool dp_clk_src) 921 { 922 struct dce110_clk_src *clk_src = 923 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 924 925 if (!clk_src) 926 return NULL; 927 928 if (dcn401_clk_src_construct(clk_src, ctx, bios, id, 929 regs, &cs_shift, &cs_mask)) { 930 clk_src->base.dp_clk_src = dp_clk_src; 931 return &clk_src->base; 932 } 933 934 kfree(clk_src); 935 BREAK_TO_DEBUGGER(); 936 return NULL; 937 } 938 939 static struct hubbub *dcn42b_hubbub_create(struct dc_context *ctx) 940 { 941 int i; 942 943 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 944 GFP_KERNEL); 945 946 if (!hubbub3) 947 return NULL; 948 949 #undef REG_STRUCT 950 #define REG_STRUCT hubbub_reg 951 hubbub_reg_init(); 952 953 #undef REG_STRUCT 954 #define REG_STRUCT vmid_regs 955 vmid_regs_init(0), 956 vmid_regs_init(1), 957 vmid_regs_init(2), 958 vmid_regs_init(3), 959 vmid_regs_init(4), 960 vmid_regs_init(5), 961 vmid_regs_init(6), 962 vmid_regs_init(7), 963 vmid_regs_init(8), 964 vmid_regs_init(9), 965 vmid_regs_init(10), 966 vmid_regs_init(11), 967 vmid_regs_init(12), 968 vmid_regs_init(13), 969 vmid_regs_init(14), 970 vmid_regs_init(15); 971 972 hubbub42_construct(hubbub3, ctx, 973 &hubbub_reg, 974 &hubbub_shift, 975 &hubbub_mask, 976 DCN42_DEFAULT_DET_SIZE, 977 8, 978 DCN42_CRB_SIZE_KB); 979 for (i = 0; i < res_cap_dcn42b.num_vmid; i++) { 980 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 981 982 vmid->ctx = ctx; 983 984 vmid->regs = &vmid_regs[i]; 985 vmid->shifts = &vmid_shifts; 986 vmid->masks = &vmid_masks; 987 } 988 989 return &hubbub3->base; 990 } 991 992 static struct hubp *dcn42b_hubp_create( 993 struct dc_context *ctx, 994 uint32_t inst) 995 { 996 struct dcn20_hubp *hubp2 = 997 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 998 999 if (!hubp2) 1000 return NULL; 1001 1002 #undef REG_STRUCT 1003 #define REG_STRUCT hubp_regs 1004 hubp_regs_init(0), 1005 hubp_regs_init(1), 1006 hubp_regs_init(2), 1007 hubp_regs_init(3); 1008 1009 if (hubp42_construct(hubp2, ctx, inst, 1010 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1011 return &hubp2->base; 1012 1013 BREAK_TO_DEBUGGER(); 1014 kfree(hubp2); 1015 return NULL; 1016 } 1017 static const struct dc_panel_config dcn42b_panel_config_defaults = { 1018 .psr = { 1019 .disable_psr = true, 1020 .disallow_psrsu = true, 1021 .disallow_replay = true, 1022 }, 1023 .ilr = { 1024 .optimize_edp_link_rate = true, 1025 }, 1026 }; 1027 1028 static void dcn42b_dpp_destroy(struct dpp **dpp) 1029 { 1030 kfree(TO_DCN42_DPP(*dpp)); 1031 *dpp = NULL; 1032 } 1033 1034 static struct dpp *dcn42b_dpp_create( 1035 struct dc_context *ctx, 1036 uint32_t inst) 1037 { 1038 struct dcn42_dpp *dpp42b = 1039 kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); 1040 1041 if (!dpp42b) 1042 return NULL; 1043 1044 #undef REG_STRUCT 1045 #define REG_STRUCT dpp_regs 1046 dpp_regs_init(0), 1047 dpp_regs_init(1), 1048 dpp_regs_init(2), 1049 dpp_regs_init(3); 1050 1051 if (dpp42_construct(dpp42b, ctx, inst, 1052 &dpp_regs[inst], &tf_shift, &tf_mask)) 1053 return &dpp42b->base; 1054 1055 BREAK_TO_DEBUGGER(); 1056 kfree(dpp42b); 1057 return NULL; 1058 } 1059 1060 static struct mpc *dcn42b_mpc_create( 1061 struct dc_context *ctx, 1062 int num_mpcc, 1063 int num_rmu) 1064 { 1065 struct dcn42_mpc *mpc42b = kzalloc(sizeof(struct dcn42_mpc), 1066 GFP_KERNEL); 1067 1068 if (!mpc42b) 1069 return NULL; 1070 1071 #undef REG_STRUCT 1072 #define REG_STRUCT mpc_regs 1073 dcn_mpc_regs_init(); 1074 1075 dcn42_mpc_construct(mpc42b, ctx, 1076 &mpc_regs, 1077 &mpc_shift, 1078 &mpc_mask, 1079 num_mpcc, 1080 num_rmu); 1081 1082 return &mpc42b->base; 1083 } 1084 1085 static struct output_pixel_processor *dcn42b_opp_create( 1086 struct dc_context *ctx, uint32_t inst) 1087 { 1088 struct dcn20_opp *opp4 = 1089 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 1090 1091 if (!opp4) { 1092 BREAK_TO_DEBUGGER(); 1093 return NULL; 1094 } 1095 1096 #undef REG_STRUCT 1097 #define REG_STRUCT opp_regs 1098 opp_regs_init(0), 1099 opp_regs_init(1), 1100 opp_regs_init(2); 1101 //DCN42B has 3 OPP Pipes 1102 //opp_regs_init(3); 1103 dcn20_opp_construct(opp4, ctx, inst, 1104 &opp_regs[inst], &opp_shift, &opp_mask); 1105 return &opp4->base; 1106 } 1107 1108 static struct timing_generator *dcn42b_timing_generator_create( 1109 struct dc_context *ctx, 1110 uint32_t instance) 1111 { 1112 struct optc *tgn10 = 1113 kzalloc(sizeof(struct optc), GFP_KERNEL); 1114 1115 if (!tgn10) 1116 return NULL; 1117 #undef REG_STRUCT 1118 #define REG_STRUCT optc_regs 1119 optc_regs_init(0), 1120 optc_regs_init(1), 1121 optc_regs_init(2); 1122 //optc_regs_init(3); 1123 tgn10->base.inst = instance; 1124 tgn10->base.ctx = ctx; 1125 1126 tgn10->tg_regs = &optc_regs[instance]; 1127 tgn10->tg_shift = &optc_shift; 1128 tgn10->tg_mask = &optc_mask; 1129 1130 dcn42_timing_generator_init(tgn10); 1131 1132 return &tgn10->base; 1133 } 1134 1135 static const struct encoder_feature_support link_enc_feature = { 1136 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1137 .max_hdmi_pixel_clock = 600000, 1138 .hdmi_ycbcr420_supported = true, 1139 .dp_ycbcr420_supported = true, 1140 .fec_supported = true, 1141 .flags.bits.IS_HBR2_CAPABLE = true, 1142 .flags.bits.IS_HBR3_CAPABLE = true, 1143 .flags.bits.IS_TPS3_CAPABLE = true, 1144 .flags.bits.IS_TPS4_CAPABLE = true}; 1145 1146 static struct link_encoder *dcn42b_link_encoder_create( 1147 struct dc_context *ctx, 1148 const struct encoder_init_data *enc_init_data) 1149 { 1150 struct dcn20_link_encoder *enc20 = 1151 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1152 1153 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1154 return NULL; 1155 1156 #undef REG_STRUCT 1157 #define REG_STRUCT link_enc_aux_regs 1158 aux_regs_init(0), 1159 aux_regs_init(1), 1160 aux_regs_init(2); 1161 /* 1162 * Not included in DCN42B: 1163 * aux_regs_init(3), 1164 * aux_regs_init(4); 1165 */ 1166 #undef REG_STRUCT 1167 #define REG_STRUCT link_enc_hpd_regs 1168 hpd_regs_init(0), 1169 hpd_regs_init(1), 1170 hpd_regs_init(2); 1171 /* 1172 * Not included in DCN42B: 1173 * hpd_regs_init(3), 1174 * hpd_regs_init(4); 1175 */ 1176 #undef REG_STRUCT 1177 #define REG_STRUCT link_enc_regs 1178 link_regs_init(0, A), 1179 link_regs_init(1, B), 1180 link_regs_init(2, C); 1181 /* 1182 * Not included in DCN42B: 1183 * link_regs_init(3, D), 1184 * link_regs_init(4, E); 1185 */ 1186 1187 dcn42_link_encoder_construct(enc20, 1188 enc_init_data, 1189 &link_enc_feature, 1190 &link_enc_regs[enc_init_data->transmitter], 1191 &link_enc_aux_regs[enc_init_data->channel - 1], 1192 &link_enc_hpd_regs[enc_init_data->hpd_source], 1193 &le_shift, 1194 &le_mask); 1195 return &enc20->enc10.base; 1196 } 1197 1198 static void read_dce_straps( 1199 struct dc_context *ctx, 1200 struct resource_straps *straps) 1201 { 1202 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1203 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1204 } 1205 1206 static struct audio *dcn42b_create_audio( 1207 struct dc_context *ctx, unsigned int inst) 1208 { 1209 1210 #undef REG_STRUCT 1211 #define REG_STRUCT audio_regs 1212 audio_regs_init(0), 1213 audio_regs_init(1), 1214 audio_regs_init(2), 1215 audio_regs_init(3), 1216 audio_regs_init(4); 1217 1218 return dce_audio_create(ctx, inst, 1219 &audio_regs[inst], &audio_shift, &audio_mask); 1220 } 1221 1222 static struct vpg *dcn42b_vpg_create( 1223 struct dc_context *ctx, 1224 uint32_t inst) 1225 { 1226 struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1227 1228 if (!vpg4) 1229 return NULL; 1230 1231 #undef REG_STRUCT 1232 #define REG_STRUCT vpg_regs 1233 vpg_regs_init(0), 1234 vpg_regs_init(1), 1235 vpg_regs_init(2), 1236 vpg_regs_init(3), 1237 vpg_regs_init(4), 1238 vpg_regs_init(5), 1239 vpg_regs_init(6), 1240 vpg_regs_init(7), 1241 vpg_regs_init(8), 1242 vpg_regs_init(9); 1243 vpg31_construct(vpg4, ctx, inst, 1244 &vpg_regs[inst], 1245 &vpg_shift, 1246 &vpg_mask); 1247 1248 return &vpg4->base; 1249 } 1250 1251 static struct apg *dcn42b_apg_create( 1252 struct dc_context *ctx, 1253 uint32_t inst) 1254 { 1255 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1256 1257 if (!apg31) 1258 return NULL; 1259 1260 #undef REG_STRUCT 1261 #define REG_STRUCT apg_regs 1262 apg_regs_init(0), 1263 apg_regs_init(1), 1264 apg_regs_init(2), 1265 apg_regs_init(3), 1266 apg_regs_init(4), 1267 apg_regs_init(5), 1268 apg_regs_init(6), 1269 apg_regs_init(7), 1270 apg_regs_init(8), 1271 apg_regs_init(9); 1272 1273 apg31_construct(apg31, ctx, inst, 1274 &apg_regs[inst], 1275 &apg_shift, 1276 &apg_mask); 1277 1278 return &apg31->base; 1279 } 1280 1281 static struct stream_encoder *dcn42b_stream_encoder_create( 1282 enum engine_id eng_id, 1283 struct dc_context *ctx) 1284 { 1285 struct dcn10_stream_encoder *enc1; 1286 struct vpg *vpg; 1287 struct apg *apg; 1288 1289 uint32_t vpg_inst; 1290 uint32_t apg_inst; 1291 1292 /* Mapping of VPG, DME register blocks to DIO block instance */ 1293 if (eng_id <= ENGINE_ID_DIGF) { 1294 vpg_inst = eng_id; 1295 apg_inst = eng_id; 1296 } else 1297 return NULL; 1298 1299 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1300 vpg = dcn42b_vpg_create(ctx, vpg_inst); 1301 apg = dcn42b_apg_create(ctx, apg_inst); 1302 1303 if (!enc1 || !vpg || !apg) { 1304 kfree(enc1); 1305 kfree(vpg); 1306 kfree(apg); 1307 return NULL; 1308 } 1309 #undef REG_STRUCT 1310 #define REG_STRUCT stream_enc_regs 1311 stream_enc_regs_init(0), 1312 stream_enc_regs_init(1), 1313 stream_enc_regs_init(2); 1314 /* 1315 * stream_enc_regs_init(3), 1316 * stream_enc_regs_init(4); 1317 */ 1318 1319 dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1320 eng_id, vpg, apg, 1321 &stream_enc_regs[eng_id], 1322 &se_shift, &se_mask); 1323 return &enc1->base; 1324 } 1325 1326 static struct hpo_dp_stream_encoder *dcn42b_hpo_dp_stream_encoder_create( 1327 enum engine_id eng_id, 1328 struct dc_context *ctx) 1329 { 1330 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1331 struct vpg *vpg; 1332 struct apg *apg; 1333 uint32_t hpo_dp_inst; 1334 uint32_t vpg_inst; 1335 uint32_t apg_inst; 1336 1337 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1338 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1339 1340 /* Mapping of VPG register blocks to HPO DP block instance: 1341 * VPG[6] -> HPO_DP[0] 1342 * VPG[7] -> HPO_DP[1] 1343 * VPG[8] -> HPO_DP[2] 1344 * VPG[9] -> HPO_DP[3] 1345 */ 1346 //specific to DCN42B: regVPG6..regVPG9 are the four HPO DP VPGs 1347 vpg_inst = hpo_dp_inst + 6; 1348 1349 /* Mapping of APG register blocks to HPO DP block instance: 1350 * APG[6] -> HPO_DP[0] 1351 * APG[7] -> HPO_DP[1] 1352 * APG[8] -> HPO_DP[2] 1353 * APG[9] -> HPO_DP[3] 1354 */ 1355 //specific to DCN42B: APG slots 6..9 correspond to HPO DP encoders 0..3 1356 apg_inst = hpo_dp_inst + 6; 1357 1358 /* allocate HPO stream encoder and create VPG sub-block */ 1359 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1360 vpg = dcn42b_vpg_create(ctx, vpg_inst); 1361 apg = dcn42b_apg_create(ctx, apg_inst); 1362 1363 if (!hpo_dp_enc31 || !vpg || !apg) { 1364 kfree(hpo_dp_enc31); 1365 kfree(vpg); 1366 kfree(apg); 1367 return NULL; 1368 } 1369 1370 #undef REG_STRUCT 1371 #define REG_STRUCT hpo_dp_stream_enc_regs 1372 hpo_dp_stream_encoder_reg_init(0), 1373 hpo_dp_stream_encoder_reg_init(1), 1374 hpo_dp_stream_encoder_reg_init(2); 1375 //hpo_dp_stream_encoder_reg_init(3); 1376 1377 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1378 hpo_dp_inst, eng_id, vpg, apg, 1379 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1380 &hpo_dp_se_shift, &hpo_dp_se_mask); 1381 1382 return &hpo_dp_enc31->base; 1383 } 1384 1385 static struct hpo_dp_link_encoder *dcn42b_hpo_dp_link_encoder_create( 1386 uint8_t inst, 1387 struct dc_context *ctx) 1388 { 1389 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1390 1391 /* allocate HPO link encoder */ 1392 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1393 if (!hpo_dp_enc31) 1394 return NULL; /* out of memory */ 1395 1396 /* DCN42B has 2 HPO DP link encoders */ 1397 #undef REG_STRUCT 1398 #define REG_STRUCT hpo_dp_link_enc_regs 1399 hpo_dp_link_encoder_reg_init(0), 1400 hpo_dp_link_encoder_reg_init(1); 1401 1402 hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, 1403 &hpo_dp_link_enc_regs[inst], 1404 &hpo_dp_le_shift, &hpo_dp_le_mask); 1405 1406 return &hpo_dp_enc31->base; 1407 } 1408 1409 static struct dce_hwseq *dcn42b_hwseq_create( 1410 struct dc_context *ctx) 1411 { 1412 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1413 1414 #undef REG_STRUCT 1415 #define REG_STRUCT hwseq_reg 1416 hwseq_reg_init(); 1417 1418 if (hws) { 1419 hws->ctx = ctx; 1420 hws->regs = &hwseq_reg; 1421 hws->shifts = &hwseq_shift; 1422 hws->masks = &hwseq_mask; 1423 } 1424 1425 return hws; 1426 } 1427 1428 static const struct resource_create_funcs res_create_funcs = { 1429 .read_dce_straps = read_dce_straps, 1430 .create_audio = dcn42b_create_audio, 1431 .create_stream_encoder = dcn42b_stream_encoder_create, 1432 .create_hpo_dp_stream_encoder = dcn42b_hpo_dp_stream_encoder_create, 1433 .create_hpo_dp_link_encoder = dcn42b_hpo_dp_link_encoder_create, 1434 .create_hwseq = dcn42b_hwseq_create, 1435 }; 1436 1437 static void dcn42b_dsc_destroy(struct display_stream_compressor **dsc) 1438 { 1439 kfree(container_of(*dsc, struct dcn401_dsc, base)); 1440 *dsc = NULL; 1441 } 1442 1443 static void dcn42b_resource_destruct(struct dcn42b_resource_pool *pool) 1444 { 1445 unsigned int i; 1446 1447 for (i = 0; i < pool->base.stream_enc_count; i++) { 1448 if (pool->base.stream_enc[i] != NULL) { 1449 if (pool->base.stream_enc[i]->vpg != NULL) { 1450 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1451 pool->base.stream_enc[i]->vpg = NULL; 1452 } 1453 if (pool->base.stream_enc[i]->apg != NULL) { 1454 kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); 1455 pool->base.stream_enc[i]->apg = NULL; 1456 } 1457 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1458 pool->base.stream_enc[i] = NULL; 1459 } 1460 } 1461 1462 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1463 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1464 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1465 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1466 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1467 } 1468 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1469 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1470 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1471 } 1472 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1473 pool->base.hpo_dp_stream_enc[i] = NULL; 1474 } 1475 } 1476 1477 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1478 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1479 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1480 pool->base.hpo_dp_link_enc[i] = NULL; 1481 } 1482 } 1483 1484 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { 1485 if (pool->base.dscs[i] != NULL) 1486 dcn42b_dsc_destroy(&pool->base.dscs[i]); 1487 } 1488 1489 if (pool->base.mpc != NULL) { 1490 kfree(TO_DCN20_MPC(pool->base.mpc)); 1491 pool->base.mpc = NULL; 1492 } 1493 if (pool->base.hubbub != NULL) { 1494 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1495 pool->base.hubbub = NULL; 1496 } 1497 for (i = 0; i < pool->base.pipe_count; i++) { 1498 if (pool->base.dpps[i] != NULL) 1499 dcn42b_dpp_destroy(&pool->base.dpps[i]); 1500 1501 if (pool->base.ipps[i] != NULL) 1502 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1503 1504 if (pool->base.hubps[i] != NULL) { 1505 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1506 pool->base.hubps[i] = NULL; 1507 } 1508 1509 if (pool->base.irqs != NULL) 1510 dal_irq_service_destroy(&pool->base.irqs); 1511 } 1512 1513 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) { 1514 if (pool->base.engines[i] != NULL) 1515 dce110_engine_destroy(&pool->base.engines[i]); 1516 } 1517 1518 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 1519 if (pool->base.hw_i2cs[i] != NULL) { 1520 kfree(pool->base.hw_i2cs[i]); 1521 pool->base.hw_i2cs[i] = NULL; 1522 } 1523 if (pool->base.sw_i2cs[i] != NULL) { 1524 kfree(pool->base.sw_i2cs[i]); 1525 pool->base.sw_i2cs[i] = NULL; 1526 } 1527 } 1528 1529 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { 1530 if (pool->base.opps[i] != NULL) 1531 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1532 } 1533 1534 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1535 if (pool->base.timing_generators[i] != NULL) { 1536 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1537 pool->base.timing_generators[i] = NULL; 1538 } 1539 } 1540 1541 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { 1542 if (pool->base.dwbc[i] != NULL) { 1543 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1544 pool->base.dwbc[i] = NULL; 1545 } 1546 if (pool->base.mcif_wb[i] != NULL) { 1547 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1548 pool->base.mcif_wb[i] = NULL; 1549 } 1550 } 1551 1552 for (i = 0; i < pool->base.audio_count; i++) { 1553 if (pool->base.audios[i]) 1554 dce_aud_destroy(&pool->base.audios[i]); 1555 } 1556 1557 for (i = 0; i < pool->base.clk_src_count; i++) { 1558 if (pool->base.clock_sources[i] != NULL) { 1559 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1560 pool->base.clock_sources[i] = NULL; 1561 } 1562 } 1563 1564 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { 1565 if (pool->base.mpc_lut[i] != NULL) { 1566 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1567 pool->base.mpc_lut[i] = NULL; 1568 } 1569 if (pool->base.mpc_shaper[i] != NULL) { 1570 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1571 pool->base.mpc_shaper[i] = NULL; 1572 } 1573 } 1574 1575 if (pool->base.dp_clock_source != NULL) { 1576 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1577 pool->base.dp_clock_source = NULL; 1578 } 1579 1580 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1581 if (pool->base.multiple_abms[i] != NULL) 1582 dce_abm_destroy(&pool->base.multiple_abms[i]); 1583 } 1584 1585 if (pool->base.psr != NULL) 1586 dmub_psr_destroy(&pool->base.psr); 1587 1588 if (pool->base.pg_cntl != NULL) 1589 dcn_pg_cntl_destroy(&pool->base.pg_cntl); 1590 if (pool->base.replay != NULL) 1591 dmub_replay_destroy(&pool->base.replay); 1592 if (pool->base.dccg != NULL) 1593 dcn_dccg_destroy(&pool->base.dccg); 1594 1595 if (pool->base.oem_device != NULL) { 1596 struct dc *dc = pool->base.oem_device->ctx->dc; 1597 1598 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1599 } 1600 } 1601 1602 static void dcn42b_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) 1603 { 1604 const struct dc_stream_state *stream = pipe_ctx->stream; 1605 struct dc_link *link = stream->link; 1606 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 1607 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; 1608 1609 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1610 1611 if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) 1612 pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; 1613 1614 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 1615 link_enc = link_enc_cfg_get_link_enc(link); 1616 if (link_enc) 1617 pixel_clk_params->encoder_object_id = link_enc->id; 1618 1619 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1620 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1621 /* TODO: un-hardcode*/ 1622 1623 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ 1624 1625 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1626 LINK_RATE_REF_FREQ_IN_KHZ; 1627 pixel_clk_params->flags.ENABLE_SS = 0; 1628 pixel_clk_params->color_depth = 1629 stream->timing.display_color_depth; 1630 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1631 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1632 1633 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1634 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1635 1636 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1637 pixel_clk_params->requested_pix_clk_100hz *= 2; 1638 if (dc_is_tmds_signal(stream->signal) && 1639 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1640 pixel_clk_params->requested_pix_clk_100hz /= 2; 1641 1642 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1643 pipe_ctx->clock_source, 1644 &pipe_ctx->stream_res.pix_clk_params, 1645 &pipe_ctx->pll_settings); 1646 1647 pixel_clk_params->dio_se_pix_per_cycle = 1; 1648 if (dc_is_tmds_signal(stream->signal) && 1649 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1650 pixel_clk_params->dio_se_pix_per_cycle = 2; 1651 } else if (dc_is_dp_signal(stream->signal)) { 1652 /* round up to nearest power of 2, or max at 8 pixels per cycle */ 1653 if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1654 pixel_clk_params->dio_se_pix_per_cycle = 8; 1655 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1656 pixel_clk_params->dio_se_pix_per_cycle = 4; 1657 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1658 pixel_clk_params->dio_se_pix_per_cycle = 2; 1659 } else { 1660 pixel_clk_params->dio_se_pix_per_cycle = 1; 1661 } 1662 } 1663 } 1664 1665 static bool dcn42b_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1666 { 1667 unsigned int i; 1668 uint32_t dwb_count = pool->res_cap->num_dwb; 1669 1670 for (i = 0; i < dwb_count; i++) { 1671 struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), 1672 GFP_KERNEL); 1673 1674 if (!dwbc42) { 1675 dm_error("DC: failed to create dwbc42!\n"); 1676 return false; 1677 } 1678 1679 #undef REG_STRUCT 1680 #define REG_STRUCT dwbc401_regs 1681 dwbc_regs_dcn401_init(0); 1682 1683 dcn30_dwbc_construct(dwbc42, ctx, 1684 &dwbc401_regs[i], 1685 &dwbc401_shift, 1686 &dwbc401_mask, 1687 i); 1688 1689 pool->dwbc[i] = &dwbc42->base; 1690 } 1691 return true; 1692 } 1693 1694 static void dcn42b_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, 1695 struct dc_context *ctx) 1696 { 1697 dcn42_mmhubbub_set_fgcg( 1698 mcif_wb30, 1699 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); 1700 } 1701 1702 static bool dcn42b_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1703 { 1704 unsigned int i; 1705 uint32_t pipe_count = pool->res_cap->num_dwb; 1706 1707 for (i = 0; i < pipe_count; i++) { 1708 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1709 GFP_KERNEL); 1710 1711 if (!mcif_wb30) { 1712 dm_error("DC: failed to create mcif_wb30!\n"); 1713 return false; 1714 } 1715 1716 #undef REG_STRUCT 1717 #define REG_STRUCT mcif_wb35_regs 1718 mcif_wb_regs_dcn3_init(0); 1719 1720 dcn35_mmhubbub_construct(mcif_wb30, ctx, 1721 &mcif_wb35_regs[i], 1722 &mcif_wb35_shift, 1723 &mcif_wb35_mask, 1724 i); 1725 1726 dcn42b_mmhubbub_init(mcif_wb30, ctx); 1727 1728 pool->mcif_wb[i] = &mcif_wb30->base; 1729 } 1730 return true; 1731 } 1732 1733 static struct display_stream_compressor *dcn42b_dsc_create( 1734 struct dc_context *ctx, uint32_t inst) 1735 { 1736 struct dcn401_dsc *dsc = 1737 kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); 1738 1739 if (!dsc) { 1740 BREAK_TO_DEBUGGER(); 1741 return NULL; 1742 } 1743 1744 #undef REG_STRUCT 1745 #define REG_STRUCT dsc_regs 1746 dsc_regs_init(0), 1747 dsc_regs_init(1), 1748 dsc_regs_init(2); 1749 //Not in DCN42B: dsc_regs_init(3); 1750 1751 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1752 dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); 1753 1754 dsc->max_image_width = 5760; 1755 1756 return &dsc->base; 1757 } 1758 1759 static void dcn42b_destroy_resource_pool(struct resource_pool **pool) 1760 { 1761 struct dcn42b_resource_pool *dcn42b_pool = TO_DCN42B_RES_POOL(*pool); 1762 1763 dcn42b_resource_destruct(dcn42b_pool); 1764 kfree(dcn42b_pool); 1765 *pool = NULL; 1766 } 1767 1768 static struct dc_cap_funcs cap_funcs = { 1769 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; 1770 1771 static void dcn42b_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 1772 { 1773 (void)bw_params; 1774 dc_assert_fp_enabled(); 1775 1776 if (dc->current_state && dc->current_state->bw_ctx.dml2) 1777 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); 1778 } 1779 1780 static void dcn42b_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1781 { 1782 DC_FP_START(); 1783 dcn42b_update_bw_bounding_box_fpu(dc, bw_params); 1784 DC_FP_END(); 1785 } 1786 1787 enum dc_status dcn42b_validate_bandwidth(struct dc *dc, 1788 struct dc_state *context, 1789 enum dc_validate_mode validate_mode) 1790 { 1791 bool out = false; 1792 1793 DC_FP_START(); 1794 1795 out = dml2_validate(dc, context, context->bw_ctx.dml2, 1796 validate_mode); 1797 1798 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { 1799 /*not required for mode enumeration*/ 1800 dcn42_decide_zstate_support(dc, context); 1801 } 1802 1803 DC_FP_END(); 1804 1805 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1806 } 1807 void dcn42b_prepare_mcache_programming(struct dc *dc, 1808 struct dc_state *context) 1809 { 1810 if (dc->debug.using_dml21) { 1811 DC_FP_START(); 1812 dml2_prepare_mcache_programming(dc, context, 1813 context->power_source == DC_POWER_SOURCE_DC ? 1814 context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); 1815 DC_FP_END(); 1816 } 1817 } 1818 /* Create a minimal link encoder object not associated with a particular 1819 * physical connector. 1820 * resource_funcs.link_enc_create_minimal 1821 */ 1822 static struct link_encoder *dcn42b_link_enc_create_minimal( 1823 struct dc_context *ctx, enum engine_id eng_id) 1824 { 1825 struct dcn20_link_encoder *enc20; 1826 1827 if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1828 return NULL; 1829 1830 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1831 if (!enc20) 1832 return NULL; 1833 1834 dcn31_link_encoder_construct_minimal( 1835 enc20, 1836 ctx, 1837 &link_enc_feature, 1838 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1839 eng_id); 1840 1841 return &enc20->enc10.base; 1842 } 1843 static void dcn42b_get_panel_config_defaults(struct dc_panel_config *panel_config) 1844 { 1845 *panel_config = dcn42b_panel_config_defaults; 1846 } 1847 static unsigned int dcn42b_get_max_hw_cursor_size(const struct dc *dc, 1848 struct dc_state *state, 1849 const struct dc_stream_state *stream) 1850 { 1851 (void)state; 1852 (void)stream; 1853 1854 return dc->caps.max_cursor_size; 1855 } 1856 1857 static struct resource_funcs dcn42b_res_pool_funcs = { 1858 .destroy = dcn42b_destroy_resource_pool, 1859 .link_enc_create = dcn42b_link_encoder_create, 1860 .link_enc_create_minimal = dcn42b_link_enc_create_minimal, 1861 .link_encs_assign = link_enc_cfg_link_encs_assign, 1862 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1863 .panel_cntl_create = dcn32_panel_cntl_create, 1864 .validate_bandwidth = dcn42b_validate_bandwidth, 1865 .calculate_wm_and_dlg = NULL, 1866 .populate_dml_pipes = NULL, 1867 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, 1868 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, 1869 .release_pipe = dcn20_release_pipe, 1870 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1871 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1872 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1873 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1874 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1875 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1876 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1877 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1878 .update_bw_bounding_box = dcn42b_update_bw_bounding_box, 1879 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, 1880 .get_panel_config_defaults = dcn42b_get_panel_config_defaults, 1881 //.get_preferred_eng_id_dpia = dcn42b_get_preferred_eng_id_dpia, 1882 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1883 .add_phantom_pipes = dcn32_add_phantom_pipes, 1884 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, 1885 #ifdef CONFIG_DRM_AMD_DC_DML21 1886 .prepare_mcache_programming = dcn42b_prepare_mcache_programming, 1887 #endif 1888 .build_pipe_pix_clk_params = dcn42b_build_pipe_pix_clk_params, 1889 .get_power_profile = dcn401_get_power_profile, 1890 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, 1891 .get_default_tiling_info = dcn401_get_default_tiling_info, 1892 .get_max_hw_cursor_size = dcn42b_get_max_hw_cursor_size, 1893 }; 1894 1895 static bool dcn42b_resource_construct( 1896 uint8_t num_virtual_links, 1897 struct dc *dc, 1898 struct dcn42b_resource_pool *pool) 1899 { 1900 int i; 1901 struct dc_context *ctx = dc->ctx; 1902 struct irq_service_init_data init_data; 1903 uint32_t num_pipes = 4; 1904 1905 #undef REG_STRUCT 1906 #define REG_STRUCT bios_regs 1907 bios_regs_init(); 1908 1909 #undef REG_STRUCT 1910 #define REG_STRUCT clk_src_regs 1911 clk_src_regs_init(0, A), 1912 clk_src_regs_init(1, B), 1913 clk_src_regs_init(2, C), 1914 clk_src_regs_init(3, D), 1915 clk_src_regs_init(4, E); 1916 1917 #undef REG_STRUCT 1918 #define REG_STRUCT abm_regs 1919 abm_regs_init(0), 1920 abm_regs_init(1), 1921 abm_regs_init(2); 1922 //abm_regs_init(3); 1923 #undef REG_STRUCT 1924 #define REG_STRUCT dccg_regs 1925 dccg_regs_init(); 1926 1927 ctx->dc_bios->regs = &bios_regs; 1928 1929 pool->base.res_cap = &res_cap_dcn42b; 1930 1931 /* max number of pipes for ASIC before checking for pipe fuses */ 1932 num_pipes = pool->base.res_cap->num_dpp; 1933 pool->base.funcs = &dcn42b_res_pool_funcs; 1934 1935 /************************************************* 1936 * Resource + asic cap harcoding * 1937 *************************************************/ 1938 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; 1939 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1940 pool->base.pipe_count = num_pipes; 1941 pool->base.mpcc_count = num_pipes; 1942 dc->caps.ips_v2_support = true; 1943 dc->caps.max_downscale_ratio = 600; 1944 dc->caps.i2c_speed_in_khz = 100; 1945 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 1946 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 1947 dc->caps.max_cursor_size = 64; 1948 dc->caps.max_buffered_cursor_size = 64; 1949 dc->caps.cursor_not_scaled = true; 1950 dc->caps.min_horizontal_blanking_period = 80; 1951 dc->caps.dmdata_alloc_size = 2048; 1952 dc->caps.mall_size_per_mem_channel = 4; 1953 /* total size = mall per channel * num channels * 1024 * 1024 */ 1954 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1955 dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1956 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1957 dc->caps.cache_line_size = 64; 1958 dc->caps.cache_num_ways = 16; 1959 1960 /* Calculate the available MALL space */ 1961 dc->caps.max_cab_allocation_bytes = 1962 dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * 1963 dc->caps.mall_size_per_mem_channel * 1024 * 1024; 1964 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; 1965 1966 dc->caps.subvp_fw_processing_delay_us = 15; 1967 dc->caps.subvp_drr_max_vblank_margin_us = 40; 1968 dc->caps.subvp_prefetch_end_to_mall_start_us = 15; 1969 dc->caps.subvp_swath_height_margin_lines = 16; 1970 dc->caps.subvp_pstate_allow_width_us = 20; 1971 dc->caps.subvp_vertical_int_margin_us = 30; 1972 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin 1973 1974 dc->caps.max_slave_planes = 2; 1975 dc->caps.max_slave_yuv_planes = 2; 1976 dc->caps.max_slave_rgb_planes = 2; 1977 dc->caps.post_blend_color_processing = true; 1978 dc->caps.force_dp_tps4_for_cp2520 = true; 1979 if (dc->config.forceHBR2CP2520) 1980 dc->caps.force_dp_tps4_for_cp2520 = false; 1981 dc->caps.dp_hdmi21_pcon_support = true; 1982 dc->caps.dp_hpo = true; 1983 dc->caps.dp_hdmi21_pcon_support = true; 1984 dc->caps.edp_dsc_support = true; 1985 dc->caps.extended_aux_timeout_support = true; 1986 dc->caps.dmcub_support = true; 1987 dc->caps.is_apu = true; 1988 dc->caps.seamless_odm = true; 1989 dc->caps.zstate_support = false; 1990 dc->caps.ips_support = false; 1991 dc->caps.max_v_total = (1 << 15) - 1; 1992 dc->caps.vtotal_limited_by_fp2 = true; 1993 dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; 1994 1995 /* Color pipeline capabilities */ 1996 dc->caps.color.dpp.dcn_arch = 1; 1997 dc->caps.color.dpp.input_lut_shared = 0; 1998 dc->caps.color.dpp.icsc = 1; 1999 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2000 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2001 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2002 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2003 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2004 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2005 dc->caps.color.dpp.post_csc = 1; 2006 dc->caps.color.dpp.gamma_corr = 1; 2007 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2008 2009 dc->caps.color.dpp.hw_3d_lut = 0; 2010 dc->caps.color.dpp.ogam_ram = 0; 2011 // no OGAM ROM on DCN2 and later ASICs 2012 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2013 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2014 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2015 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2016 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2017 dc->caps.color.dpp.ocsc = 0; 2018 2019 dc->caps.color.mpc.gamut_remap = 1; 2020 //configurable to be before or after BLND in MPCC 2021 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; 2022 dc->caps.color.mpc.num_rmcm_3dluts = 2; 2023 dc->caps.color.mpc.ogam_ram = 1; 2024 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2025 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2026 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2027 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2028 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2029 dc->caps.color.mpc.ocsc = 1; 2030 dc->caps.color.mpc.preblend = true; 2031 dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; 2032 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; 2033 dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; 2034 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; 2035 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; 2036 dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; 2037 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; 2038 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; 2039 dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; 2040 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; 2041 dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; 2042 dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; 2043 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; 2044 dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; 2045 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; 2046 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; 2047 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; 2048 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; 2049 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; 2050 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; 2051 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; 2052 dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; 2053 2054 dc->caps.num_of_host_routers = 0; 2055 dc->caps.num_of_dpias_per_host_router = 0; 2056 2057 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 2058 * to provide some margin. 2059 * It's expected for furture ASIC to have equal or higher value, in order to 2060 * have determinstic power improvement from generate to genration. 2061 * (i.e., we should not expect new ASIC generation with lower vmin rate) 2062 */ 2063 dc->caps.max_disp_clock_khz_at_vmin = 650000; 2064 dc->config.use_spl = true; 2065 dc->config.prefer_easf = true; 2066 2067 dc->config.dcn_sharpness_range.sdr_rgb_min = 0; 2068 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; 2069 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; 2070 dc->config.dcn_sharpness_range.sdr_yuv_min = 0; 2071 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; 2072 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; 2073 dc->config.dcn_sharpness_range.hdr_rgb_min = 0; 2074 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; 2075 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; 2076 2077 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; 2078 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; 2079 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; 2080 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; 2081 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; 2082 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; 2083 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; 2084 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; 2085 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; 2086 2087 dc->config.use_pipe_ctx_sync_logic = true; 2088 dc->config.dc_mode_clk_limit_support = false; 2089 dc->config.enable_windowed_mpo_odm = true; 2090 /* Use psp mailbox to enable assr */ 2091 dc->config.use_assr_psp_message = true; 2092 /* dcn42 and afterward always support external panel replay */ 2093 dc->config.frame_update_cmd_version2 = true; 2094 2095 /* read VBIOS LTTPR caps */ 2096 { 2097 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2098 enum bp_result bp_query_result; 2099 uint8_t is_vbios_lttpr_enable = 0; 2100 2101 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2102 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2103 } 2104 2105 dc->caps.vbios_lttpr_aware = true; 2106 } 2107 dc->check_config = config_defaults; 2108 2109 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2110 dc->debug = debug_defaults_drv; 2111 /*HW default is to have all the FGCG enabled, SW no need to program them*/ 2112 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; 2113 // Init the vm_helper 2114 if (dc->vm_helper) 2115 vm_helper_init(dc->vm_helper, 16); 2116 2117 /************************************************* 2118 * Create resources * 2119 *************************************************/ 2120 2121 /* Clock Sources for Pixel Clock*/ 2122 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = 2123 dcn42b_clock_source_create(ctx, ctx->dc_bios, 2124 CLOCK_SOURCE_COMBO_PHY_PLL0, 2125 &clk_src_regs[0], false); 2126 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = 2127 dcn42b_clock_source_create(ctx, ctx->dc_bios, 2128 CLOCK_SOURCE_COMBO_PHY_PLL1, 2129 &clk_src_regs[1], false); 2130 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = 2131 dcn42b_clock_source_create(ctx, ctx->dc_bios, 2132 CLOCK_SOURCE_COMBO_PHY_PLL2, 2133 &clk_src_regs[2], false); 2134 2135 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; 2136 2137 /* todo: not reuse phy_pll registers */ 2138 pool->base.dp_clock_source = 2139 dcn42b_clock_source_create(ctx, ctx->dc_bios, 2140 CLOCK_SOURCE_ID_DP_DTO, 2141 &clk_src_regs[0], true); 2142 2143 for (i = 0; i < (int)pool->base.clk_src_count; i++) { 2144 if (pool->base.clock_sources[i] == NULL) { 2145 dm_error("DC: failed to create clock sources!\n"); 2146 BREAK_TO_DEBUGGER(); 2147 goto create_fail; 2148 } 2149 } 2150 2151 /* DCCG */ 2152 pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2153 if (pool->base.dccg == NULL) { 2154 dm_error("DC: failed to create dccg!\n"); 2155 BREAK_TO_DEBUGGER(); 2156 goto create_fail; 2157 } 2158 2159 #undef REG_STRUCT 2160 #define REG_STRUCT pg_cntl_regs 2161 pg_cntl_dcn42b_regs_init(); 2162 2163 pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); 2164 if (pool->base.pg_cntl == NULL) { 2165 dm_error("DC: failed to create power gate control!\n"); 2166 BREAK_TO_DEBUGGER(); 2167 goto create_fail; 2168 } 2169 /* IRQ Service */ 2170 init_data.ctx = dc->ctx; 2171 pool->base.irqs = dal_irq_service_dcn42_create(&init_data); 2172 if (!pool->base.irqs) 2173 goto create_fail; 2174 2175 /* HUBBUB */ 2176 pool->base.hubbub = dcn42b_hubbub_create(ctx); 2177 if (pool->base.hubbub == NULL) { 2178 BREAK_TO_DEBUGGER(); 2179 dm_error("DC: failed to create hubbub!\n"); 2180 goto create_fail; 2181 } 2182 2183 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2184 /* HUBPs */ 2185 for (i = 0; i < pool->base.res_cap->num_dpp; i++) { 2186 pool->base.hubps[i] = dcn42b_hubp_create(ctx, i); 2187 if (pool->base.hubps[i] == NULL) { 2188 BREAK_TO_DEBUGGER(); 2189 dm_error("DC: failed to create hubps!\n"); 2190 goto create_fail; 2191 } 2192 } 2193 2194 /* DPPs */ 2195 for (i = 0; i < pool->base.res_cap->num_dpp; i++) { 2196 pool->base.dpps[i] = dcn42b_dpp_create(ctx, i); 2197 if (pool->base.dpps[i] == NULL) { 2198 BREAK_TO_DEBUGGER(); 2199 dm_error("DC: failed to create dpps!\n"); 2200 goto create_fail; 2201 } 2202 } 2203 2204 /* OPPs */ 2205 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2206 pool->base.opps[i] = dcn42b_opp_create(ctx, i); 2207 if (pool->base.opps[i] == NULL) { 2208 BREAK_TO_DEBUGGER(); 2209 dm_error("DC: failed to create output pixel processor!\n"); 2210 goto create_fail; 2211 } 2212 } 2213 2214 /* TGs */ 2215 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2216 pool->base.timing_generators[i] = dcn42b_timing_generator_create(ctx, i); 2217 if (pool->base.timing_generators[i] == NULL) { 2218 BREAK_TO_DEBUGGER(); 2219 dm_error("DC: failed to create tg!\n"); 2220 goto create_fail; 2221 } 2222 } 2223 2224 /* ABMs */ 2225 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2226 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2227 &abm_regs[i], 2228 &abm_shift, 2229 &abm_mask); 2230 if (pool->base.multiple_abms[i] == NULL) { 2231 dm_error("DC: failed to create abm for pipe %d!\n", i); 2232 BREAK_TO_DEBUGGER(); 2233 goto create_fail; 2234 } 2235 } 2236 2237 /* PSR */ 2238 pool->base.psr = dmub_psr_create(ctx); 2239 if (pool->base.psr == NULL) { 2240 dm_error("DC: failed to create psr obj!\n"); 2241 BREAK_TO_DEBUGGER(); 2242 goto create_fail; 2243 } 2244 2245 /* Replay */ 2246 pool->base.replay = dmub_replay_create(ctx); 2247 if (pool->base.replay == NULL) { 2248 dm_error("DC: failed to create replay obj!\n"); 2249 BREAK_TO_DEBUGGER(); 2250 goto create_fail; 2251 } 2252 2253 /* Auto Test */ 2254 2255 /* MPCCs */ 2256 pool->base.mpc = dcn42b_mpc_create(ctx, pool->base.mpcc_count, 2257 pool->base.res_cap->num_mpc_3dlut); 2258 if (pool->base.mpc == NULL) { 2259 BREAK_TO_DEBUGGER(); 2260 dm_error("DC: failed to create mpc!\n"); 2261 goto create_fail; 2262 } 2263 2264 /* DSCs */ 2265 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2266 pool->base.dscs[i] = dcn42b_dsc_create(ctx, i); 2267 if (pool->base.dscs[i] == NULL) { 2268 BREAK_TO_DEBUGGER(); 2269 dm_error("DC: failed to create display stream compressor %d!\n", i); 2270 goto create_fail; 2271 } 2272 } 2273 2274 /* DWB */ 2275 if (!dcn42b_dwbc_create(ctx, &pool->base)) { 2276 BREAK_TO_DEBUGGER(); 2277 dm_error("DC: failed to create dwbc!\n"); 2278 goto create_fail; 2279 } 2280 2281 /* MMHUBBUB */ 2282 if (!dcn42b_mmhubbub_create(ctx, &pool->base)) { 2283 BREAK_TO_DEBUGGER(); 2284 dm_error("DC: failed to create mcif_wb!\n"); 2285 goto create_fail; 2286 } 2287 2288 /* AUX */ 2289 for (i = 0; i < pool->base.res_cap->num_aux; i++) { 2290 pool->base.engines[i] = dcn42b_aux_engine_create(ctx, i); 2291 if (pool->base.engines[i] == NULL) { 2292 BREAK_TO_DEBUGGER(); 2293 dm_error( 2294 "DC:failed to create aux engine!!\n"); 2295 goto create_fail; 2296 } 2297 } 2298 2299 /* I2C */ 2300 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2301 pool->base.hw_i2cs[i] = dcn42b_i2c_hw_create(ctx, i); 2302 if (pool->base.hw_i2cs[i] == NULL) { 2303 BREAK_TO_DEBUGGER(); 2304 dm_error( 2305 "DC:failed to create hw i2c!!\n"); 2306 goto create_fail; 2307 } 2308 pool->base.sw_i2cs[i] = NULL; 2309 } 2310 /* DCN4.2B has 0 DPIA */ 2311 /*pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; 2312 if (dc->debug.dpia_debug.bits.disable_dpia)*/ 2313 pool->base.usb4_dpia_count = 0; 2314 2315 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2316 if (!resource_construct(num_virtual_links, dc, &pool->base, 2317 &res_create_funcs)) 2318 goto create_fail; 2319 2320 /* HW Sequencer init functions and Plane caps */ 2321 dcn42b_hw_sequencer_init_functions(dc); 2322 2323 dc->caps.max_planes = pool->base.pipe_count; 2324 dc->config.dp_connector_no_native_i2c = true; 2325 2326 for (i = 0; i < (int)dc->caps.max_planes; ++i) 2327 dc->caps.planes[i] = plane_cap; 2328 2329 dc->caps.max_odm_combine_factor = 4; 2330 2331 dc->cap_funcs = cap_funcs; 2332 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 2333 2334 // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided 2335 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2336 dc->config.sdpif_request_limit_words_per_umc = 16; 2337 2338 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2339 /*this will use real soc clock table*/ 2340 dc->dml2_options.use_native_soc_bb_construction = true; 2341 dc->dml2_options.minimize_dispclk_using_odm = false; 2342 if (dc->config.EnableMinDispClkODM) 2343 dc->dml2_options.minimize_dispclk_using_odm = true; 2344 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; 2345 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2346 dc->dml2_options.force_tdlut_enable = true; 2347 2348 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2349 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = 2350 &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2351 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; 2352 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = 2353 pool->base.funcs->calculate_mall_ways_from_bytes; 2354 2355 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; 2356 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; 2357 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; 2358 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; 2359 2360 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; 2361 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; 2362 2363 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; 2364 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; 2365 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = 2366 dc->caps.max_cab_allocation_bytes; 2367 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; 2368 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; 2369 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; 2370 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; 2371 2372 dc->dml2_options.max_segments_per_hubp = 24; 2373 dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; 2374 dc->dml2_options.gpuvm_enable = true; 2375 dc->dml2_options.hostvm_enable = true; 2376 2377 /* SPL */ 2378 dc->caps.scl_caps.sharpener_support = true; 2379 2380 return true; 2381 2382 create_fail: 2383 2384 dcn42b_resource_destruct(pool); 2385 2386 return false; 2387 } 2388 struct resource_pool *dcn42b_create_resource_pool( 2389 const struct dc_init_data *init_data, 2390 struct dc *dc) 2391 { 2392 struct dcn42b_resource_pool *pool = 2393 kzalloc(sizeof(struct dcn42b_resource_pool), GFP_KERNEL); 2394 2395 if (!pool) 2396 return NULL; 2397 2398 if (dcn42b_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) 2399 return &pool->base; 2400 2401 BREAK_TO_DEBUGGER(); 2402 kfree(pool); 2403 return NULL; 2404 } 2405