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Searched refs:bw (Results 1 – 25 of 214) sorted by relevance

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/linux/drivers/net/wireless/broadcom/brcm80211/brcmutil/
H A Dd11.c28 static u16 d11n_bw(enum brcmu_chan_bw bw) in d11n_bw() argument
30 switch (bw) { in d11n_bw()
43 if (ch->bw == BRCMU_CHAN_BW_20) in brcmu_d11n_encchspec()
52 0, d11n_bw(ch->bw)); in brcmu_d11n_encchspec()
60 static u16 d11ac_bw(enum brcmu_chan_bw bw) in d11ac_bw() argument
62 switch (bw) { in d11ac_bw()
79 if (ch->bw == BRCMU_CHAN_BW_20 || ch->sb == BRCMU_CHAN_SB_NONE) in brcmu_d11ac_encchspec()
87 0, d11ac_bw(ch->bw)); in brcmu_d11ac_encchspec()
105 ch->bw = BRCMU_CHAN_BW_20; in brcmu_d11n_decchspec()
109 ch->bw = BRCMU_CHAN_BW_40; in brcmu_d11n_decchspec()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_wrapper_fpu.c64 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
67 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
70 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
72 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
73 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
74 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
106 …memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, siz… in dml21_calculate_rq_and_dlg_params()
108 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], in dml21_calculate_rq_and_dlg_params()
117 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
118 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
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H A Ddml21_utils.c178 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
182 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
231 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; in dml21_program_dc_pipe()
232 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
233 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
393 union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; in dml21_build_fams2_stream_programming_v2()
394 union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; in dml21_build_fams2_stream_programming_v2()
506 memset(&context->bw_ctx.bw in dml21_build_fams2_programming()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_utils.c186 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
190 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
191 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
192 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
193 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported;
288 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000; in dml2_calculate_rq_and_dlg_params()
289 context->bw_ctx.bw in dml2_calculate_rq_and_dlg_params()
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/linux/drivers/media/dvb-frontends/
H A Ddib7000m.c316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) in dib7000m_set_bandwidth() argument
320 if (!bw) in dib7000m_set_bandwidth()
321 bw = 8000; in dib7000m_set_bandwidth()
324 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
334 timf = timf * (bw / 50) / 160; in dib7000m_set_bandwidth()
382 … dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_config *bw) in dib7000m_reset_pll_common() argument
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
[all …]
H A Ddib7000p.c368 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw) in dib7000p_set_bandwidth() argument
373 state->current_bandwidth = bw; in dib7000p_set_bandwidth()
377 timf = state->cfg.bw->timf; in dib7000p_set_bandwidth()
383 timf = timf * (bw / 50) / 160; in dib7000p_set_bandwidth()
444 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; in dib7000p_reset_pll() local
448 …dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio <… in dib7000p_reset_pll()
453 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15)); in dib7000p_reset_pll()
456 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | in dib7000p_reset_pll()
457 …(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw-… in dib7000p_reset_pll()
462 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
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/linux/drivers/net/wireless/ath/ath11k/
H A Dreg.c501 u16 bw; in ath11k_reg_adjust_bw() local
506 bw = end_freq - start_freq; in ath11k_reg_adjust_bw()
507 bw = min_t(u16, bw, max_bw); in ath11k_reg_adjust_bw()
509 if (bw >= 80 && bw < 160) in ath11k_reg_adjust_bw()
510 bw = 80; in ath11k_reg_adjust_bw()
511 else if (bw >= 40 && bw < 80) in ath11k_reg_adjust_bw()
512 bw = 40; in ath11k_reg_adjust_bw()
513 else if (bw >= 20 && bw < 40) in ath11k_reg_adjust_bw()
514 bw = 20; in ath11k_reg_adjust_bw()
516 bw = 0; in ath11k_reg_adjust_bw()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c505 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
526 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = (uint32_t)(get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
527 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
528 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = (uint32_t)(get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
529 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = (uint32_t)(get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
530 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; in dcn31_calculate_wm_and_dlg_fp()
531 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = (uint32_t)(get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
532 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = (uint32_t)(get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
533 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = (uint32_t)(get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000); in dcn31_calculate_wm_and_dlg_fp()
534 context->bw_ctx.bw in dcn31_calculate_wm_and_dlg_fp()
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/linux/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf-tuner.c79 u8 bw) in mxl111sf_calc_phy_tune_regs() argument
84 switch (bw) { in mxl111sf_calc_phy_tune_regs()
186 static int mxl1x1sf_tune_rf(struct dvb_frontend *fe, u32 freq, u8 bw) in mxl1x1sf_tune_rf() argument
193 mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw); in mxl1x1sf_tune_rf()
206 reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw); in mxl1x1sf_tune_rf()
268 u8 bw; in mxl111sf_tuner_set_params() local
275 bw = 0; /* ATSC */ in mxl111sf_tuner_set_params()
278 bw = 1; /* US CABLE */ in mxl111sf_tuner_set_params()
283 bw = 6; in mxl111sf_tuner_set_params()
286 bw = 7; in mxl111sf_tuner_set_params()
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/linux/drivers/net/wireless/ath/ath12k/
H A Dreg.c511 u16 bw; in ath12k_reg_adjust_bw() local
513 bw = end_freq - start_freq; in ath12k_reg_adjust_bw()
514 bw = min_t(u16, bw, max_bw); in ath12k_reg_adjust_bw()
516 if (bw >= 80 && bw < 160) in ath12k_reg_adjust_bw()
517 bw = 80; in ath12k_reg_adjust_bw()
518 else if (bw >= 40 && bw < 80) in ath12k_reg_adjust_bw()
519 bw in ath12k_reg_adjust_bw()
528 ath12k_reg_update_rule(struct ieee80211_reg_rule * reg_rule,u32 start_freq,u32 end_freq,u32 bw,u32 ant_gain,u32 reg_pwr,s8 psd,u32 reg_flags) ath12k_reg_update_rule() argument
547 u16 bw; ath12k_reg_update_weather_radar_band() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c911 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
919 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
920 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
934 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce112_validate_bandwidth()
935 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce112_validate_bandwidth()
936 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
937 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
938 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce112_validate_bandwidth()
939 context->bw_ctx.bw in dce112_validate_bandwidth()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c988 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
998 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
999 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1013 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1014 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1015 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1016 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1017 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1018 context->bw_ctx.bw in dce110_validate_bandwidth()
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/linux/net/wireless/
H A Dutil.c1320 bitrate = (rate->bw == RATE_INFO_BW_40) ? 13500000 : 6500000; in cfg80211_calculate_bitrate_dmg()
1501 switch (rate->bw) { in cfg80211_calculate_bitrate_he()
1528 WARN_ONCE(1, "invalid rate bw=%d, mcs=%d, nss=%d\n", in cfg80211_calculate_bitrate_he()
1529 rate->bw, rate->mcs, rate->nss); in cfg80211_calculate_bitrate_he()
1573 if (rate->bw == RATE_INFO_BW_160 || in cfg80211_calculate_bitrate_he()
1574 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1577 else if (rate->bw == RATE_INFO_BW_80 || in _cfg80211_calculate_bitrate_eht_uhr()
1578 (rate->bw == RATE_INFO_BW_HE_RU && in _cfg80211_calculate_bitrate_eht_uhr()
1581 else if (rate->bw == RATE_INFO_BW_40 || in _cfg80211_calculate_bitrate_eht_uhr()
1582 (rate->bw in _cfg80211_calculate_bitrate_eht_uhr()
2793 ieee80211_get_vht_max_nss(struct ieee80211_vht_cap * cap,enum ieee80211_vht_chanwidth bw,int mcs,bool ext_nss_bw_capable,unsigned int max_vht_nss) ieee80211_get_vht_max_nss() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1157 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000.0); in dcn20_calculate_dlg_params()
1158 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000.0); in dcn20_calculate_dlg_params()
1159 context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0); in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000.0 / 16.0); in dcn20_calculate_dlg_params()
1162 if ((int)dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1165 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000.0); in dcn20_calculate_dlg_params()
1166 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000.0); in dcn20_calculate_dlg_params()
1167 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1174 context->bw_ctx.bw in dcn20_calculate_dlg_params()
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/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8814a.c113 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | in rtw8814a_init_hwcap()
125 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, in rtw8814a_init_hwcap()
549 static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw) in rtw8814a_set_bw_reg_adc() argument
553 if (bw == RTW_CHANNEL_WIDTH_20) in rtw8814a_set_bw_reg_adc()
555 else if (bw == RTW_CHANNEL_WIDTH_40) in rtw8814a_set_bw_reg_adc()
557 else if (bw == RTW_CHANNEL_WIDTH_80) in rtw8814a_set_bw_reg_adc()
563 static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw) in rtw8814a_set_bw_reg_agc() argument
567 if (bw == RTW_CHANNEL_WIDTH_20) { in rtw8814a_set_bw_reg_agc()
569 } else if (bw == RTW_CHANNEL_WIDTH_40) { in rtw8814a_set_bw_reg_agc()
574 } else if (bw == RTW_CHANNEL_WIDTH_80) { in rtw8814a_set_bw_reg_agc()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1634 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000); in dcn32_calculate_dlg_params()
1635 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000); in dcn32_calculate_dlg_params()
1636 context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000); in dcn32_calculate_dlg_params()
1637 context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16); in dcn32_calculate_dlg_params()
1638 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000); in dcn32_calculate_dlg_params()
1639 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000); in dcn32_calculate_dlg_params()
1640 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn32_calculate_dlg_params()
1647 context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; in dcn32_calculate_dlg_params()
1649 context->bw_ctx.bw in dcn32_calculate_dlg_params()
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/linux/include/net/
H A Dregulatory.h225 #define REG_RULE_EXT(start, end, bw, gain, eirp, dfs_cac, reg_flags) \ argument
229 .freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
236 #define REG_RULE(start, end, bw, gain, eirp, reg_flags) \ argument
237 REG_RULE_EXT(start, end, bw, gain, eirp, 0, reg_flags)
/linux/drivers/media/tuners/
H A Dmxl5007t.c374 enum mxl5007t_bw_mhz bw) in mxl5007t_set_bw_bits() argument
378 switch (bw) { in mxl5007t_set_bw_bits()
398 u32 rf_freq, enum mxl5007t_bw_mhz bw) in mxl5007t_calc_rf_tune_regs() argument
407 mxl5007t_set_bw_bits(state, bw); in mxl5007t_calc_rf_tune_regs()
521 enum mxl5007t_bw_mhz bw) in mxl5007t_tuner_rf_tune() argument
527 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw); in mxl5007t_tuner_rf_tune()
595 enum mxl5007t_bw_mhz bw; in mxl5007t_set_params() local
603 bw = MxL_BW_6MHz; in mxl5007t_set_params()
607 bw = MxL_BW_6MHz; in mxl5007t_set_params()
614 bw = MxL_BW_6MHz; in mxl5007t_set_params()
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c967 u32 freq, enum carl9170_bw bw) in carl9170_init_rf_bank4_pwr() argument
975 switch (bw) { in carl9170_init_rf_bank4_pwr()
1036 enum carl9170_bw bw) in carl9170_get_hw_dyn_params() argument
1052 return &carl9170_phy_freq_params[chanidx].params[bw]; in carl9170_get_hw_dyn_params()
1260 enum carl9170_bw bw, struct ar9170_calctl_edges edges[]) in carl9170_get_heavy_clip() argument
1271 if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE) in carl9170_get_heavy_clip()
1291 static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw) in carl9170_calc_ctl() argument
1366 freq, bw, EDGES(ctl_idx, 1)); in carl9170_calc_ctl()
1372 if (bw == CARL9170_BW_40_BELOW) in carl9170_calc_ctl()
1429 enum carl9170_bw bw) in carl9170_set_power_cal() argument
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dphy.c246 int bw = FIELD_GET(MT_RXWI_RATE_BW, rate); in mt7601u_phy_get_rssi() local
255 val -= lna[aux_lna][bw][lna_id]; in mt7601u_phy_get_rssi()
278 if (dev->bw != MT_BW_20) in mt7601u_set_bw_filter()
296 t = &bbp_mode_table[dev->temp_mode][dev->bw]; in mt7601u_load_bbp_temp_table_bw()
319 t[dev->bw].regs, t[dev->bw].n); in mt7601u_bbp_temp()
326 if (hw_chan != 14 || dev->bw != MT_BW_20) { in mt7601u_apply_ch14_fixup()
377 u8 bw; in __mt7601u_phy_set_channel() local
380 bw = MT_BW_20; in __mt7601u_phy_set_channel()
385 bw = MT_BW_40; in __mt7601u_phy_set_channel()
395 if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { in __mt7601u_phy_set_channel()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_sched.c3087 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_cir_bw() argument
3089 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_cir_bw()
3091 bw_t_info->cir_bw.bw = 0; in ice_set_clear_cir_bw()
3095 bw_t_info->cir_bw.bw = bw; in ice_set_clear_cir_bw()
3106 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_eir_bw() argument
3108 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_eir_bw()
3110 bw_t_info->eir_bw.bw = 0; in ice_set_clear_eir_bw()
3120 bw_t_info->eir_bw.bw = bw; in ice_set_clear_eir_bw()
3131 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_shared_bw() argument
3133 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_shared_bw()
[all …]
/linux/drivers/memory/samsung/
H A Dexynos-srom.c72 u32 cs, bw; in exynos_srom_configure_bank() local
90 bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW); in exynos_srom_configure_bank()
91 bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank); in exynos_srom_configure_bank()
92 writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW); in exynos_srom_configure_bank()
/linux/arch/x86/include/asm/shared/
H A Dio.h7 #define BUILDIO(bwl, bw, type) \ argument
10 asm volatile("out" #bwl " %" #bw "0, %w1" \
17 asm volatile("in" #bwl " %w1, %" #bw "0" \
/linux/net/mac80211/
H A Dairtime.c511 int bw, streams; in ieee80211_get_rate_duration() local
515 switch (status->bw) { in ieee80211_get_rate_duration()
517 bw = BW_20; in ieee80211_get_rate_duration()
520 bw = BW_40; in ieee80211_get_rate_duration()
523 bw = BW_80; in ieee80211_get_rate_duration()
526 bw = BW_160; in ieee80211_get_rate_duration()
529 bw = BW_320; in ieee80211_get_rate_duration()
540 group = VHT_GROUP_IDX(streams, sgi, bw); in ieee80211_get_rate_duration()
545 group = HT_GROUP_IDX(streams, sgi, bw); in ieee80211_get_rate_duration()
550 group = HE_GROUP_IDX(streams, status->he_gi, bw); in ieee80211_get_rate_duration()
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Drate.h137 u32 bw = rspec_get_bw(rspec); in rspec_is40mhz() local
139 return bw == PHY_TXC1_BW_40MHZ || bw == PHY_TXC1_BW_40MHZ_DUP; in rspec_is40mhz()
236 bool mcsallow, u8 bw, u8 txstreams);
243 void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw);

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