1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2025 Realtek Corporation 3 */ 4 5 #include <linux/usb.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "tx.h" 9 #include "phy.h" 10 #include "rtw8814a.h" 11 #include "rtw8814a_table.h" 12 #include "rtw88xxa.h" 13 #include "reg.h" 14 #include "debug.h" 15 #include "efuse.h" 16 #include "regd.h" 17 #include "usb.h" 18 19 static void rtw8814a_efuse_grant(struct rtw_dev *rtwdev, bool on) 20 { 21 if (on) { 22 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 23 24 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 25 rtw_write16_set(rtwdev, REG_SYS_CLKR, 26 BIT_LOADER_CLK_EN | BIT_ANA8M); 27 } else { 28 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 29 } 30 } 31 32 static void rtw8814a_read_rfe_type(struct rtw_dev *rtwdev) 33 { 34 struct rtw_efuse *efuse = &rtwdev->efuse; 35 36 if (!(efuse->rfe_option & BIT(7))) 37 return; 38 39 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 40 efuse->rfe_option = 0; 41 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 42 efuse->rfe_option = 1; 43 } 44 45 static void rtw8814a_read_amplifier_type(struct rtw_dev *rtwdev) 46 { 47 struct rtw_efuse *efuse = &rtwdev->efuse; 48 49 switch (efuse->rfe_option) { 50 case 1: 51 /* Internal 2G */ 52 efuse->pa_type_2g = 0; 53 efuse->lna_type_2g = 0; 54 /* External 5G */ 55 efuse->pa_type_5g = BIT(0); 56 efuse->lna_type_5g = BIT(3); 57 break; 58 case 2 ... 5: 59 /* External everything */ 60 efuse->pa_type_2g = BIT(4); 61 efuse->lna_type_2g = BIT(3); 62 efuse->pa_type_5g = BIT(0); 63 efuse->lna_type_5g = BIT(3); 64 break; 65 case 6: 66 efuse->lna_type_5g = BIT(3); 67 break; 68 default: 69 break; 70 } 71 } 72 73 static void rtw8814a_read_rf_type(struct rtw_dev *rtwdev, 74 struct rtw8814a_efuse *map) 75 { 76 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); 77 struct rtw_hal *hal = &rtwdev->hal; 78 79 switch (map->trx_antenna_option) { 80 case 0xff: /* 4T4R */ 81 case 0xee: /* 3T3R */ 82 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 83 rtwusb->udev->speed != USB_SPEED_SUPER) 84 hal->rf_type = RF_2T2R; 85 else 86 hal->rf_type = RF_3T3R; 87 88 break; 89 case 0x66: /* 2T2R */ 90 case 0x6f: /* 2T4R */ 91 default: 92 hal->rf_type = RF_2T2R; 93 break; 94 } 95 96 hal->rf_path_num = 4; 97 hal->rf_phy_num = 4; 98 99 if (hal->rf_type == RF_3T3R) { 100 hal->antenna_rx = BB_PATH_ABC; 101 hal->antenna_tx = BB_PATH_ABC; 102 } else { 103 hal->antenna_rx = BB_PATH_AB; 104 hal->antenna_tx = BB_PATH_AB; 105 } 106 } 107 108 static void rtw8814a_init_hwcap(struct rtw_dev *rtwdev) 109 { 110 struct rtw_efuse *efuse = &rtwdev->efuse; 111 struct rtw_hal *hal = &rtwdev->hal; 112 113 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | 114 BIT(RTW_CHANNEL_WIDTH_40) | 115 BIT(RTW_CHANNEL_WIDTH_80); 116 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT; 117 118 if (hal->rf_type == RF_3T3R) 119 efuse->hw_cap.nss = 3; 120 else 121 efuse->hw_cap.nss = 2; 122 123 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 124 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 125 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 126 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 127 } 128 129 static int rtw8814a_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 130 { 131 struct rtw_efuse *efuse = &rtwdev->efuse; 132 struct rtw8814a_efuse *map; 133 int i; 134 135 if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 136 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 137 log_map, rtwdev->chip->log_efuse_size, true); 138 139 map = (struct rtw8814a_efuse *)log_map; 140 141 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(4)); 142 efuse->rfe_option = map->rfe_option; 143 efuse->rf_board_option = map->rf_board_option; 144 efuse->crystal_cap = map->xtal_k; 145 efuse->channel_plan = map->channel_plan; 146 efuse->country_code[0] = map->country_code[0]; 147 efuse->country_code[1] = map->country_code[1]; 148 efuse->bt_setting = map->rf_bt_setting; 149 efuse->regd = map->rf_board_option & 0x7; 150 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 151 efuse->thermal_meter_k = map->thermal_meter; 152 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 153 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 154 155 rtw8814a_read_rfe_type(rtwdev); 156 rtw8814a_read_amplifier_type(rtwdev); 157 158 /* Override rtw_chip_parameter_setup() */ 159 rtw8814a_read_rf_type(rtwdev, map); 160 161 rtw8814a_init_hwcap(rtwdev); 162 163 for (i = 0; i < 4; i++) 164 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 165 166 switch (rtw_hci_type(rtwdev)) { 167 case RTW_HCI_TYPE_USB: 168 ether_addr_copy(efuse->addr, map->u.mac_addr); 169 break; 170 case RTW_HCI_TYPE_PCIE: 171 ether_addr_copy(efuse->addr, map->e.mac_addr); 172 break; 173 case RTW_HCI_TYPE_SDIO: 174 default: 175 /* unsupported now */ 176 return -EOPNOTSUPP; 177 } 178 179 return 0; 180 } 181 182 static void rtw8814a_init_rfe_reg(struct rtw_dev *rtwdev) 183 { 184 u8 rfe_option = rtwdev->efuse.rfe_option; 185 186 if (rfe_option == 2 || rfe_option == 1) { 187 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf); 188 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xf0); 189 } else if (rfe_option == 0) { 190 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf); 191 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xc0); 192 } 193 } 194 195 #define RTW_TXSCALE_SIZE 37 196 static const u32 rtw8814a_txscale_tbl[RTW_TXSCALE_SIZE] = { 197 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 198 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 199 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 200 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 201 }; 202 203 static u32 rtw8814a_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 rf_path) 204 { 205 static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 206 struct rtw_efuse *efuse = &rtwdev->efuse; 207 u8 tx_bb_swing; 208 209 if (band == RTW_BAND_2G) 210 tx_bb_swing = efuse->tx_bb_swing_setting_2g; 211 else 212 tx_bb_swing = efuse->tx_bb_swing_setting_5g; 213 214 tx_bb_swing >>= 2 * rf_path; 215 tx_bb_swing &= 0x3; 216 217 return swing2setting[tx_bb_swing]; 218 } 219 220 static u8 rtw8814a_get_swing_index(struct rtw_dev *rtwdev) 221 { 222 u32 swing, table_value; 223 u8 i; 224 225 swing = rtw8814a_get_bb_swing(rtwdev, rtwdev->hal.current_band_type, 226 RF_PATH_A); 227 228 for (i = 0; i < ARRAY_SIZE(rtw8814a_txscale_tbl); i++) { 229 table_value = rtw8814a_txscale_tbl[i]; 230 if (swing == table_value) 231 return i; 232 } 233 234 return 24; 235 } 236 237 static void rtw8814a_pwrtrack_init(struct rtw_dev *rtwdev) 238 { 239 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 240 u8 path; 241 242 dm_info->default_ofdm_index = rtw8814a_get_swing_index(rtwdev); 243 244 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 245 ewma_thermal_init(&dm_info->avg_thermal[path]); 246 dm_info->delta_power_index[path] = 0; 247 dm_info->delta_power_index_last[path] = 0; 248 } 249 dm_info->pwr_trk_triggered = false; 250 dm_info->pwr_trk_init_trigger = true; 251 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 252 } 253 254 static void rtw8814a_config_trx_path(struct rtw_dev *rtwdev) 255 { 256 /* RX CCK disable 2R CCA */ 257 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, 258 BIT_CCK0_2RX | BIT_CCK0_MRC); 259 /* pathB tx on, path A/C/D tx off */ 260 rtw_write32_mask(rtwdev, REG_CCK_RX, 0xf0000000, 0x4); 261 /* pathB rx */ 262 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5); 263 } 264 265 static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev) 266 { 267 /* CCK 2R CCA parameters */ 268 269 /* Disable Ant diversity */ 270 rtw_write32_mask(rtwdev, REG_RXSB, BIT_RXSB_ANA_DIV, 0x0); 271 /* Concurrent CCA at LSB & USB */ 272 rtw_write32_mask(rtwdev, REG_CCA, BIT_CCA_CO, 0); 273 /* RX path diversity enable */ 274 rtw_write32_mask(rtwdev, REG_ANTSEL, BIT_ANT_BYCO, 0); 275 /* r_en_mrc_antsel */ 276 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_DIS_CO_PATHSEL, 0); 277 /* MBC weighting */ 278 rtw_write32_mask(rtwdev, REG_CCA_MF, BIT_MBC_WIN, 1); 279 /* 2R CCA only */ 280 rtw_write32_mask(rtwdev, REG_CCKTX, BIT_CMB_CCA_2R, 1); 281 } 282 283 static void rtw8814a_phy_set_param(struct rtw_dev *rtwdev) 284 { 285 u32 crystal_cap, val32; 286 u8 val8, rf_path; 287 288 /* power on BB/RF domain */ 289 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 290 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_USBA); 291 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 292 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_PCIEA); 293 294 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, 295 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 296 297 /* Power on RF paths A..D */ 298 val8 = BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB; 299 rtw_write8(rtwdev, REG_RF_CTRL, val8); 300 rtw_write8(rtwdev, REG_RF_CTRL1, val8); 301 rtw_write8(rtwdev, REG_RF_CTRL2, val8); 302 rtw_write8(rtwdev, REG_RF_CTRL3, val8); 303 304 rtw_load_table(rtwdev, rtwdev->chip->bb_tbl); 305 rtw_load_table(rtwdev, rtwdev->chip->agc_tbl); 306 307 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 308 crystal_cap |= crystal_cap << 6; 309 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x07ff8000, crystal_cap); 310 311 rtw8814a_config_trx_path(rtwdev); 312 313 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) 314 rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]); 315 316 val32 = rtw_read_rf(rtwdev, RF_PATH_A, RF_RCK1_V1, RFREG_MASK); 317 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK1_V1, RFREG_MASK, val32); 318 rtw_write_rf(rtwdev, RF_PATH_C, RF_RCK1_V1, RFREG_MASK, val32); 319 rtw_write_rf(rtwdev, RF_PATH_D, RF_RCK1_V1, RFREG_MASK, val32); 320 321 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 322 323 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xFF); 324 325 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff); 326 327 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 328 329 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0); 330 331 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5)); 332 333 rtw8814a_config_cck_rx_antenna_init(rtwdev); 334 335 rtw_phy_init(rtwdev); 336 rtw8814a_pwrtrack_init(rtwdev); 337 338 rtw8814a_init_rfe_reg(rtwdev); 339 340 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3)); 341 342 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 235); 343 344 /* enable Tx report. */ 345 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x1F); 346 347 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 348 /* Reset USB mode switch setting */ 349 rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0); 350 rtw_write8(rtwdev, REG_ACLK_MON, 0x0); 351 } 352 } 353 354 static void rtw8814ae_enable_rf_1_2v(struct rtw_dev *rtwdev) 355 { 356 /* This is for fullsize card, because GPIO7 there is floating. 357 * We should pull GPIO7 high to enable RF 1.2V Switch Power Supply 358 */ 359 360 /* 1. set 0x40[1:0] to 0, BIT_GPIOSEL=0, select pin as GPIO */ 361 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(1) | BIT(0)); 362 363 /* 2. set 0x44[31] to 0 364 * mode=0: data port; 365 * mode=1 and BIT_GPIO_IO_SEL=0: interrupt mode; 366 */ 367 rtw_write8_clr(rtwdev, REG_GPIO_PIN_CTRL + 3, BIT(7)); 368 369 /* 3. data mode 370 * 3.1 set 0x44[23] to 1 371 * sel=0: input; 372 * sel=1: output; 373 */ 374 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 2, BIT(7)); 375 376 /* 3.2 set 0x44[15] to 1 377 * output high value; 378 */ 379 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 1, BIT(7)); 380 } 381 382 static int rtw8814a_mac_init(struct rtw_dev *rtwdev) 383 { 384 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); 385 386 rtw_write16(rtwdev, REG_CR, 387 MAC_TRX_ENABLE | BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN); 388 389 rtw_load_table(rtwdev, rtwdev->chip->mac_tbl); 390 391 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 392 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, 393 rtwdev->chip->usb_tx_agg_desc_num << 1); 394 395 rtw_write32(rtwdev, REG_HIMR0, 0); 396 rtw_write32(rtwdev, REG_HIMR1, 0); 397 398 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xfffff); 399 400 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030); 401 402 rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff); 403 rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400); 404 rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff); 405 406 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, 0x36); 407 rtw_write8(rtwdev, REG_MAX_AGGR_NUM + 1, 0x36); 408 409 /* Set Spec SIFS (used in NAV) */ 410 rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a); 411 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a); 412 413 /* Set SIFS for CCK */ 414 rtw_write16(rtwdev, REG_SIFS, 0x100a); 415 416 /* Set SIFS for OFDM */ 417 rtw_write16(rtwdev, REG_SIFS + 2, 0x100a); 418 419 /* TXOP */ 420 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 421 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 422 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 423 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 424 425 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7)); 426 427 rtw_write8(rtwdev, REG_ACKTO, 0x80); 428 429 rtw_write16(rtwdev, REG_BCN_CTRL, 430 BIT_DIS_TSF_UDT | (BIT_DIS_TSF_UDT << 8)); 431 rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME); 432 rtw_write8(rtwdev, REG_DRVERLYINT, 0x05); 433 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 434 rtw_write16(rtwdev, REG_BCNTCFG, 0x4413); 435 rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xFF); 436 437 rtw_write32(rtwdev, REG_FAST_EDCA_VOVI_SETTING, 0x08070807); 438 rtw_write32(rtwdev, REG_FAST_EDCA_BEBK_SETTING, 0x08070807); 439 440 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 441 rtwusb->udev->speed == USB_SPEED_SUPER) { 442 /* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */ 443 rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3)); 444 /* To avoid usb 3.0 H2C fail. */ 445 rtw_write16(rtwdev, 0xf002, 0); 446 447 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, 448 BIT_PRE_TX_CMD); 449 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) { 450 rtw8814ae_enable_rf_1_2v(rtwdev); 451 452 /* Force the antenna b to wifi. */ 453 rtw_write8_set(rtwdev, REG_PAD_CTRL1, BIT(2)); 454 rtw_write8_set(rtwdev, REG_PAD_CTRL1 + 1, BIT(0)); 455 rtw_write8_set(rtwdev, REG_LED_CFG + 3, 456 (BIT(27) | BIT_DPDT_WL_SEL) >> 24); 457 } 458 459 return 0; 460 } 461 462 static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev) 463 { 464 switch (rtwdev->efuse.rfe_option) { 465 case 2: 466 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270); 467 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270); 468 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270); 469 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770); 470 471 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 472 BIT_RFE_SELSW0_D, 0x72); 473 474 break; 475 case 1: 476 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 477 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 478 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 479 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777); 480 481 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 482 BIT_RFE_SELSW0_D, 0x77); 483 484 break; 485 case 0: 486 default: 487 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 488 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 489 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 490 /* Is it not necessary to set REG_RFE_PINMUX_D ? */ 491 492 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 493 BIT_RFE_SELSW0_D, 0x77); 494 495 break; 496 } 497 } 498 499 static void rtw8814a_set_rfe_reg_5g(struct rtw_dev *rtwdev) 500 { 501 switch (rtwdev->efuse.rfe_option) { 502 case 2: 503 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x37173717); 504 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x37173717); 505 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x37173717); 506 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717); 507 508 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 509 BIT_RFE_SELSW0_D, 0x37); 510 511 break; 512 case 1: 513 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x33173317); 514 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x33173317); 515 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x33173317); 516 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717); 517 518 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 519 BIT_RFE_SELSW0_D, 0x33); 520 521 break; 522 case 0: 523 default: 524 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54775477); 525 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54775477); 526 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x54775477); 527 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x54775477); 528 529 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 530 BIT_RFE_SELSW0_D, 0x54); 531 532 break; 533 } 534 } 535 536 static void rtw8814a_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band) 537 { 538 rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK, 539 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_A)); 540 rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK, 541 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_B)); 542 rtw_write32_mask(rtwdev, REG_TXSCALE_C, BB_SWING_MASK, 543 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_C)); 544 rtw_write32_mask(rtwdev, REG_TXSCALE_D, BB_SWING_MASK, 545 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_D)); 546 rtw8814a_pwrtrack_init(rtwdev); 547 } 548 549 static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw) 550 { 551 u32 adc = 0; 552 553 if (bw == RTW_CHANNEL_WIDTH_20) 554 adc = 0; 555 else if (bw == RTW_CHANNEL_WIDTH_40) 556 adc = 1; 557 else if (bw == RTW_CHANNEL_WIDTH_80) 558 adc = 2; 559 560 rtw_write32_mask(rtwdev, REG_ADCCLK, BIT(1) | BIT(0), adc); 561 } 562 563 static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw) 564 { 565 u32 agc = 7; 566 567 if (bw == RTW_CHANNEL_WIDTH_20) { 568 agc = 6; 569 } else if (bw == RTW_CHANNEL_WIDTH_40) { 570 if (new_band == RTW_BAND_5G) 571 agc = 8; 572 else 573 agc = 7; 574 } else if (bw == RTW_CHANNEL_WIDTH_80) { 575 agc = 3; 576 } 577 578 rtw_write32_mask(rtwdev, REG_CCASEL, 0xf000, agc); 579 } 580 581 static void rtw8814a_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw) 582 { 583 /* Clear 0x1000[16], When this bit is set to 0, CCK and OFDM 584 * are disabled, and clock are gated. Otherwise, CCK and OFDM 585 * are enabled. 586 */ 587 rtw_write8_clr(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB); 588 589 if (new_band == RTW_BAND_2G) { 590 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 0); 591 592 rtw8814a_set_rfe_reg_24g(rtwdev); 593 594 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x2); 595 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5); 596 597 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x3); 598 599 rtw_write8(rtwdev, REG_CCK_CHECK, 0); 600 601 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 0); 602 } else { 603 rtw_write8(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 604 605 /* Enable CCK Tx function, even when CCK is off */ 606 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 1); 607 608 rtw8814a_set_rfe_reg_5g(rtwdev); 609 610 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x0); 611 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf); 612 613 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x2); 614 } 615 616 rtw8814a_set_channel_bb_swing(rtwdev, new_band); 617 618 rtw8814a_set_bw_reg_adc(rtwdev, bw); 619 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw); 620 621 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB); 622 } 623 624 static void rtw8814a_switch_channel(struct rtw_dev *rtwdev, u8 channel) 625 { 626 struct rtw_hal *hal = &rtwdev->hal; 627 u32 fc_area, rf_mod_ag, cfgch; 628 u8 path; 629 630 switch (channel) { 631 case 36 ... 48: 632 fc_area = 0x494; 633 break; 634 case 50 ... 64: 635 fc_area = 0x453; 636 break; 637 case 100 ... 116: 638 fc_area = 0x452; 639 break; 640 default: 641 if (channel >= 118) 642 fc_area = 0x412; 643 else 644 fc_area = 0x96a; 645 break; 646 } 647 648 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area); 649 650 for (path = 0; path < hal->rf_path_num; path++) { 651 switch (channel) { 652 case 36 ... 64: 653 rf_mod_ag = 0x101; 654 break; 655 case 100 ... 140: 656 rf_mod_ag = 0x301; 657 break; 658 default: 659 if (channel > 140) 660 rf_mod_ag = 0x501; 661 else 662 rf_mod_ag = 0x000; 663 break; 664 } 665 666 cfgch = (rf_mod_ag << 8) | channel; 667 668 rtw_write_rf(rtwdev, path, RF_CFGCH, 669 RF18_RFSI_MASK | RF18_BAND_MASK | RF18_CHANNEL_MASK, cfgch); 670 } 671 672 switch (channel) { 673 case 36 ... 64: 674 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 1); 675 break; 676 case 100 ... 144: 677 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 2); 678 break; 679 default: 680 if (channel >= 149) 681 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 3); 682 683 break; 684 } 685 } 686 687 static void rtw8814a_24g_cck_tx_dfir(struct rtw_dev *rtwdev, u8 channel) 688 { 689 if (channel >= 1 && channel <= 11) { 690 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 691 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1317); 692 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000204); 693 } else if (channel >= 12 && channel <= 13) { 694 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 695 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1217); 696 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000305); 697 } else if (channel == 14) { 698 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 699 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x00000E17); 700 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000000); 701 } 702 } 703 704 static void rtw8814a_set_bw_reg_mac(struct rtw_dev *rtwdev, u8 bw) 705 { 706 u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL); 707 708 val16 &= ~BIT_RFMOD; 709 if (bw == RTW_CHANNEL_WIDTH_80) 710 val16 |= BIT_RFMOD_80M; 711 else if (bw == RTW_CHANNEL_WIDTH_40) 712 val16 |= BIT_RFMOD_40M; 713 714 rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16); 715 } 716 717 static void rtw8814a_set_bw_rf(struct rtw_dev *rtwdev, u8 bw) 718 { 719 u8 path; 720 721 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 722 switch (bw) { 723 case RTW_CHANNEL_WIDTH_5: 724 case RTW_CHANNEL_WIDTH_10: 725 case RTW_CHANNEL_WIDTH_20: 726 default: 727 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3); 728 break; 729 case RTW_CHANNEL_WIDTH_40: 730 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1); 731 break; 732 case RTW_CHANNEL_WIDTH_80: 733 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0); 734 break; 735 } 736 } 737 } 738 739 static void rtw8814a_adc_clk(struct rtw_dev *rtwdev) 740 { 741 static const u32 rxiqc_reg[2][4] = { 742 { REG_RX_IQC_AB_A, REG_RX_IQC_AB_B, 743 REG_RX_IQC_AB_C, REG_RX_IQC_AB_D }, 744 { REG_RX_IQC_CD_A, REG_RX_IQC_CD_B, 745 REG_RX_IQC_CD_C, REG_RX_IQC_CD_D } 746 }; 747 u32 bb_reg_8fc, bb_reg_808, rxiqc[4]; 748 u32 i = 0, mac_active = 1; 749 u8 mac_reg_522; 750 751 if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A) 752 return; 753 754 /* 1 Step1. MAC TX pause */ 755 mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE); 756 bb_reg_8fc = rtw_read32(rtwdev, REG_DBGSEL); 757 bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL); 758 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f); 759 760 /* 1 Step 2. Backup rxiqc & rxiqc = 0 */ 761 for (i = 0; i < 4; i++) { 762 rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]); 763 rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0); 764 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0); 765 } 766 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x3); 767 i = 0; 768 769 /* 1 Step 3. Monitor MAC IDLE */ 770 rtw_write32(rtwdev, REG_DBGSEL, 0x0); 771 while (mac_active) { 772 mac_active = rtw_read32(rtwdev, REG_DBGRPT) & 0x803e0008; 773 i++; 774 if (i > 1000) 775 break; 776 } 777 778 /* 1 Step 4. ADC clk flow */ 779 rtw_write8(rtwdev, REG_RXPSEL, 0x11); 780 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1); 781 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x3); 782 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1); 783 784 /* 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be 785 * written when bbrstb=0 786 * 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line 787 * 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut 788 */ 789 790 /* power_off/clk_off @ anapar_state=idle mode */ 791 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x15800002); 792 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x01808003); 793 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x15800002); 794 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x01808003); 795 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x15800002); 796 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x01808003); 797 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x15800002); 798 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x01808003); 799 800 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x0); 801 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0); 802 /* [19] = 1 to turn off ADC */ 803 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D080058); 804 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D080058); 805 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D080058); 806 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D080058); 807 808 /* power_on/clk_off */ 809 /* [19] = 0 to turn on ADC */ 810 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D000058); 811 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D000058); 812 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D000058); 813 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D000058); 814 815 /* power_on/clk_on @ anapar_state=BT mode */ 816 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032); 817 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032); 818 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032); 819 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032); 820 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x1); 821 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1); 822 823 /* recover original setting @ anapar_state=BT mode */ 824 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032); 825 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032); 826 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032); 827 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032); 828 829 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05800002); 830 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003); 831 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05800002); 832 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003); 833 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05800002); 834 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003); 835 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05800002); 836 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003); 837 838 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x0); 839 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0); 840 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x0); 841 842 /* 1 Step 5. Recover MAC TX & IQC */ 843 rtw_write8(rtwdev, REG_TXPAUSE, mac_reg_522); 844 rtw_write32(rtwdev, REG_DBGSEL, bb_reg_8fc); 845 rtw_write32(rtwdev, REG_RXPSEL, bb_reg_808); 846 for (i = 0; i < 4; i++) { 847 rtw_write32(rtwdev, rxiqc_reg[0][i], rxiqc[i]); 848 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x01000000); 849 } 850 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x0); 851 } 852 853 static void rtw8814a_spur_calibration_ch140(struct rtw_dev *rtwdev, u8 channel) 854 { 855 struct rtw_hal *hal = &rtwdev->hal; 856 857 /* Add for 8814AE module ch140 MP Rx */ 858 if (channel == 140) { 859 if (hal->ch_param[0] == 0) 860 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL); 861 if (hal->ch_param[1] == 0) 862 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH); 863 864 rtw_write32(rtwdev, REG_CCASEL, 0x75438170); 865 rtw_write32(rtwdev, REG_PDMFTH, 0x79a18a0a); 866 } else { 867 if (rtw_read32(rtwdev, REG_CCASEL) == 0x75438170 && 868 hal->ch_param[0] != 0) 869 rtw_write32(rtwdev, REG_CCASEL, hal->ch_param[0]); 870 871 if (rtw_read32(rtwdev, REG_PDMFTH) == 0x79a18a0a && 872 hal->ch_param[1] != 0) 873 rtw_write32(rtwdev, REG_PDMFTH, hal->ch_param[1]); 874 875 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL); 876 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH); 877 } 878 } 879 880 static void rtw8814a_set_nbi_reg(struct rtw_dev *rtwdev, u32 tone_idx) 881 { 882 /* tone_idx X 10 */ 883 static const u32 nbi_128[] = { 884 25, 55, 85, 115, 135, 885 155, 185, 205, 225, 245, 886 265, 285, 305, 335, 355, 887 375, 395, 415, 435, 455, 888 485, 505, 525, 555, 585, 615, 635 889 }; 890 u32 reg_idx = 0; 891 u32 i; 892 893 for (i = 0; i < ARRAY_SIZE(nbi_128); i++) { 894 if (tone_idx < nbi_128[i]) { 895 reg_idx = i + 1; 896 break; 897 } 898 } 899 900 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 0xfc000, reg_idx); 901 } 902 903 static void rtw8814a_nbi_setting(struct rtw_dev *rtwdev, u32 ch, u32 f_intf) 904 { 905 u32 fc, int_distance, tone_idx; 906 907 fc = 2412 + (ch - 1) * 5; 908 int_distance = abs_diff(fc, f_intf); 909 910 /* 10 * (int_distance / 0.3125) */ 911 tone_idx = int_distance << 5; 912 913 rtw8814a_set_nbi_reg(rtwdev, tone_idx); 914 915 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 1); 916 } 917 918 static void rtw8814a_spur_nbi_setting(struct rtw_dev *rtwdev) 919 { 920 u8 primary_channel = rtwdev->hal.primary_channel; 921 u8 rfe_type = rtwdev->efuse.rfe_option; 922 923 if (rfe_type != 0 && rfe_type != 1 && rfe_type != 6 && rfe_type != 7) 924 return; 925 926 if (primary_channel == 14) 927 rtw8814a_nbi_setting(rtwdev, primary_channel, 2480); 928 else if (primary_channel >= 4 && primary_channel <= 8) 929 rtw8814a_nbi_setting(rtwdev, primary_channel, 2440); 930 else 931 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 0); 932 } 933 934 /* A workaround to eliminate the 5280 MHz & 5600 MHz & 5760 MHz spur of 8814A */ 935 static void rtw8814a_spur_calibration(struct rtw_dev *rtwdev, u8 channel, u8 bw) 936 { 937 u8 rfe_type = rtwdev->efuse.rfe_option; 938 bool reset_nbi_csi = true; 939 940 if (rfe_type == 0) { 941 switch (bw) { 942 case RTW_CHANNEL_WIDTH_40: 943 if (channel == 54 || channel == 118) { 944 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 945 0x000fe000, 0x3e >> 1); 946 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 947 BIT(0), 1); 948 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 949 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK1, 950 BIT(0), 1); 951 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 952 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 953 954 reset_nbi_csi = false; 955 } else if (channel == 151) { 956 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 957 0x000fe000, 0x1e >> 1); 958 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 959 BIT(0), 1); 960 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0, 961 BIT(16), 1); 962 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 963 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 964 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 965 966 reset_nbi_csi = false; 967 } 968 break; 969 case RTW_CHANNEL_WIDTH_80: 970 if (channel == 58 || channel == 122) { 971 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 972 0x000fe000, 0x3a >> 1); 973 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 974 BIT(0), 1); 975 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 976 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 977 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 978 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 979 BIT(0), 1); 980 981 reset_nbi_csi = false; 982 } else if (channel == 155) { 983 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 984 0x000fe000, 0x5a >> 1); 985 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 986 BIT(0), 1); 987 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 988 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 989 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6, 990 BIT(16), 1); 991 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 992 993 reset_nbi_csi = false; 994 } 995 break; 996 case RTW_CHANNEL_WIDTH_20: 997 if (channel == 153) { 998 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 999 0x000fe000, 0x1e >> 1); 1000 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1001 BIT(0), 1); 1002 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1003 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1004 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1005 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 1006 BIT(16), 1); 1007 1008 reset_nbi_csi = false; 1009 } 1010 1011 rtw8814a_spur_calibration_ch140(rtwdev, channel); 1012 break; 1013 default: 1014 break; 1015 } 1016 } else if (rfe_type == 1 || rfe_type == 2) { 1017 switch (bw) { 1018 case RTW_CHANNEL_WIDTH_20: 1019 if (channel == 153) { 1020 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1021 0x000fe000, 0x1E >> 1); 1022 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1023 BIT(0), 1); 1024 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1025 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1026 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1027 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 1028 BIT(16), 1); 1029 1030 reset_nbi_csi = false; 1031 } 1032 break; 1033 case RTW_CHANNEL_WIDTH_40: 1034 if (channel == 151) { 1035 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1036 0x000fe000, 0x1e >> 1); 1037 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1038 BIT(0), 1); 1039 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0, 1040 BIT(16), 1); 1041 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1042 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1043 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1044 1045 reset_nbi_csi = false; 1046 } 1047 break; 1048 case RTW_CHANNEL_WIDTH_80: 1049 if (channel == 155) { 1050 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1051 0x000fe000, 0x5a >> 1); 1052 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1053 BIT(0), 1); 1054 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1055 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1056 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6, 1057 BIT(16), 1); 1058 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1059 1060 reset_nbi_csi = false; 1061 } 1062 break; 1063 default: 1064 break; 1065 } 1066 } 1067 1068 if (reset_nbi_csi) { 1069 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1070 0x000fe000, 0xfc >> 1); 1071 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, BIT(0), 0); 1072 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1073 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1074 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1075 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1076 } 1077 1078 rtw8814a_spur_nbi_setting(rtwdev); 1079 } 1080 1081 static void rtw8814a_set_bw_mode(struct rtw_dev *rtwdev, u8 new_band, 1082 u8 channel, u8 bw, u8 primary_chan_idx) 1083 { 1084 u8 txsc40 = 0, txsc20, txsc; 1085 1086 rtw8814a_set_bw_reg_mac(rtwdev, bw); 1087 1088 txsc20 = primary_chan_idx; 1089 if (bw == RTW_CHANNEL_WIDTH_80) { 1090 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 1091 txsc40 = RTW_SC_40_UPPER; 1092 else 1093 txsc40 = RTW_SC_40_LOWER; 1094 } 1095 1096 txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40); 1097 rtw_write8(rtwdev, REG_DATA_SC, txsc); 1098 1099 rtw8814a_set_bw_reg_adc(rtwdev, bw); 1100 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw); 1101 1102 if (bw == RTW_CHANNEL_WIDTH_80) { 1103 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc); 1104 } else if (bw == RTW_CHANNEL_WIDTH_40) { 1105 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc); 1106 1107 if (txsc == RTW_SC_20_UPPER) 1108 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 1109 else 1110 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 1111 } 1112 1113 rtw8814a_set_bw_rf(rtwdev, bw); 1114 1115 rtw8814a_adc_clk(rtwdev); 1116 1117 rtw8814a_spur_calibration(rtwdev, channel, bw); 1118 } 1119 1120 static void rtw8814a_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1121 u8 primary_chan_idx) 1122 { 1123 u8 old_band, new_band; 1124 1125 if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN) 1126 old_band = RTW_BAND_5G; 1127 else 1128 old_band = RTW_BAND_2G; 1129 1130 if (channel > 14) 1131 new_band = RTW_BAND_5G; 1132 else 1133 new_band = RTW_BAND_2G; 1134 1135 if (new_band != old_band) 1136 rtw8814a_switch_band(rtwdev, new_band, bw); 1137 1138 rtw8814a_switch_channel(rtwdev, channel); 1139 1140 rtw8814a_24g_cck_tx_dfir(rtwdev, channel); 1141 1142 rtw8814a_set_bw_mode(rtwdev, new_band, channel, bw, primary_chan_idx); 1143 } 1144 1145 static s8 rtw8814a_cck_rx_pwr(u8 lna_idx, u8 vga_idx) 1146 { 1147 s8 rx_pwr_all = 0; 1148 1149 switch (lna_idx) { 1150 case 7: 1151 rx_pwr_all = -38 - 2 * vga_idx; 1152 break; 1153 case 5: 1154 rx_pwr_all = -28 - 2 * vga_idx; 1155 break; 1156 case 3: 1157 rx_pwr_all = -8 - 2 * vga_idx; 1158 break; 1159 case 2: 1160 rx_pwr_all = -1 - 2 * vga_idx; 1161 break; 1162 default: 1163 break; 1164 } 1165 1166 return rx_pwr_all; 1167 } 1168 1169 static void rtw8814a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1170 struct rtw_rx_pkt_stat *pkt_stat) 1171 { 1172 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1173 struct rtw_jaguar_phy_status_rpt *rpt; 1174 u8 gain[RTW_RF_PATH_MAX], rssi, i; 1175 s8 rx_pwr_db, middle1, middle2; 1176 s8 snr[RTW_RF_PATH_MAX]; 1177 s8 evm[RTW_RF_PATH_MAX]; 1178 u8 rfmode, subchannel; 1179 u8 lna, vga; 1180 s8 cfo[2]; 1181 1182 rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status; 1183 1184 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1185 1186 if (pkt_stat->rate <= DESC_RATE11M) { 1187 lna = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX); 1188 vga = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX); 1189 1190 rx_pwr_db = rtw8814a_cck_rx_pwr(lna, vga); 1191 1192 pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db; 1193 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1194 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 1195 pkt_stat->signal_power = rx_pwr_db; 1196 } else { /* OFDM rate */ 1197 gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A); 1198 gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B); 1199 gain[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_GAIN_C); 1200 gain[RF_PATH_D] = le32_get_bits(rpt->w6, RTW_JGRPHY_W6_GAIN_D); 1201 1202 snr[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXSNR_A); 1203 snr[RF_PATH_B] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXSNR_B); 1204 snr[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_C); 1205 snr[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_D); 1206 1207 evm[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_1); 1208 evm[RF_PATH_B] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_2); 1209 evm[RF_PATH_C] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXEVM_3); 1210 evm[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXEVM_4); 1211 1212 if (pkt_stat->rate <= DESC_RATE54M) 1213 evm[RF_PATH_A] = le32_get_bits(rpt->w6, 1214 RTW_JGRPHY_W6_SIGEVM); 1215 1216 for (i = RF_PATH_A; i < RTW_RF_PATH_MAX; i++) { 1217 pkt_stat->rx_power[i] = gain[i] - 110; 1218 1219 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1); 1220 dm_info->rssi[i] = rssi; 1221 1222 pkt_stat->rx_snr[i] = snr[i]; 1223 dm_info->rx_snr[i] = snr[i] >> 1; 1224 1225 pkt_stat->rx_evm[i] = evm[i]; 1226 evm[i] = max_t(s8, -127, evm[i]); 1227 dm_info->rx_evm_dbm[i] = abs(evm[i]) >> 1; 1228 } 1229 1230 rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1231 RTW_RF_PATH_MAX); 1232 pkt_stat->rssi = rssi; 1233 1234 /* When power saving is enabled the hardware sometimes 1235 * reports unbelievably high gain for paths A and C 1236 * (e.g. one frame 64 68 68 72, the next frame 106 66 88 72, 1237 * the next 66 66 68 72), so use the second lowest gain 1238 * instead of the highest. 1239 */ 1240 middle1 = max(min(gain[RF_PATH_A], gain[RF_PATH_B]), 1241 min(gain[RF_PATH_C], gain[RF_PATH_D])); 1242 middle2 = min(max(gain[RF_PATH_A], gain[RF_PATH_B]), 1243 max(gain[RF_PATH_C], gain[RF_PATH_D])); 1244 rx_pwr_db = min(middle1, middle2); 1245 rx_pwr_db -= 110; 1246 pkt_stat->signal_power = rx_pwr_db; 1247 1248 rfmode = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_R_RFMOD); 1249 subchannel = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_SUB_CHNL); 1250 1251 if (rfmode == 1 && subchannel == 0) { 1252 pkt_stat->bw = RTW_CHANNEL_WIDTH_40; 1253 } else if (rfmode == 2) { 1254 if (subchannel == 0) 1255 pkt_stat->bw = RTW_CHANNEL_WIDTH_80; 1256 else if (subchannel == 9 || subchannel == 10) 1257 pkt_stat->bw = RTW_CHANNEL_WIDTH_40; 1258 } 1259 1260 cfo[RF_PATH_A] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_A); 1261 cfo[RF_PATH_B] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_B); 1262 1263 for (i = RF_PATH_A; i < 2; i++) { 1264 pkt_stat->cfo_tail[i] = cfo[i]; 1265 dm_info->cfo_tail[i] = (cfo[i] * 5) >> 1; 1266 } 1267 } 1268 } 1269 1270 static void 1271 rtw8814a_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 1272 { 1273 struct rtw_hal *hal = &rtwdev->hal; 1274 u32 txagc_table_wd; 1275 u8 rate, pwr_index; 1276 int j; 1277 1278 for (j = 0; j < rtw_rate_size[rs]; j++) { 1279 rate = rtw_rate_section[rs][j]; 1280 1281 pwr_index = hal->tx_pwr_tbl[path][rate] + 2; 1282 if (pwr_index > rtwdev->chip->max_power_index) 1283 pwr_index = rtwdev->chip->max_power_index; 1284 1285 txagc_table_wd = 0x00801000; 1286 txagc_table_wd |= (pwr_index << 24) | (path << 8) | rate; 1287 1288 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd); 1289 1290 /* first time to turn on the txagc table 1291 * second to write the addr0 1292 */ 1293 if (rate == DESC_RATE1M) 1294 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd); 1295 } 1296 } 1297 1298 static void rtw8814a_set_tx_power_index(struct rtw_dev *rtwdev) 1299 { 1300 struct rtw_hal *hal = &rtwdev->hal; 1301 int path; 1302 1303 for (path = 0; path < hal->rf_path_num; path++) { 1304 if (hal->current_band_type == RTW_BAND_2G) 1305 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1306 RTW_RATE_SECTION_CCK); 1307 1308 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1309 RTW_RATE_SECTION_OFDM); 1310 1311 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 1312 continue; 1313 1314 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1315 RTW_RATE_SECTION_HT_1S); 1316 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1317 RTW_RATE_SECTION_VHT_1S); 1318 1319 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1320 RTW_RATE_SECTION_HT_2S); 1321 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1322 RTW_RATE_SECTION_VHT_2S); 1323 1324 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1325 RTW_RATE_SECTION_HT_3S); 1326 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1327 RTW_RATE_SECTION_VHT_3S); 1328 } 1329 } 1330 1331 static void rtw8814a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1332 { 1333 } 1334 1335 static void rtw8814a_false_alarm_statistics(struct rtw_dev *rtwdev) 1336 { 1337 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1338 u32 cck_fa_cnt, ofdm_fa_cnt; 1339 u32 crc32_cnt, cca32_cnt; 1340 u32 cck_enable; 1341 1342 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 1343 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 1344 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 1345 1346 dm_info->cck_fa_cnt = cck_fa_cnt; 1347 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1348 dm_info->total_fa_cnt = ofdm_fa_cnt; 1349 if (cck_enable) 1350 dm_info->total_fa_cnt += cck_fa_cnt; 1351 1352 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 1353 dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1354 dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1355 1356 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 1357 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1358 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1359 1360 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 1361 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1362 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1363 1364 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 1365 dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1366 dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1367 1368 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 1369 dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD); 1370 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1371 if (cck_enable) { 1372 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 1373 dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD); 1374 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1375 } 1376 1377 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 1378 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 1379 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15)); 1380 rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15)); 1381 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 1382 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 1383 } 1384 1385 #define MAC_REG_NUM_8814 2 1386 #define BB_REG_NUM_8814 14 1387 #define RF_REG_NUM_8814 1 1388 1389 static void rtw8814a_iqk_backup_mac_bb(struct rtw_dev *rtwdev, 1390 u32 *mac_backup, u32 *bb_backup, 1391 const u32 *mac_regs, 1392 const u32 *bb_regs) 1393 { 1394 u32 i; 1395 1396 /* save MACBB default value */ 1397 for (i = 0; i < MAC_REG_NUM_8814; i++) 1398 mac_backup[i] = rtw_read32(rtwdev, mac_regs[i]); 1399 1400 for (i = 0; i < BB_REG_NUM_8814; i++) 1401 bb_backup[i] = rtw_read32(rtwdev, bb_regs[i]); 1402 } 1403 1404 static void rtw8814a_iqk_backup_rf(struct rtw_dev *rtwdev, 1405 u32 rf_backup[][4], const u32 *rf_regs) 1406 { 1407 u32 i; 1408 1409 /* Save RF Parameters */ 1410 for (i = 0; i < RF_REG_NUM_8814; i++) { 1411 rf_backup[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 1412 rf_regs[i], RFREG_MASK); 1413 rf_backup[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 1414 rf_regs[i], RFREG_MASK); 1415 rf_backup[i][RF_PATH_C] = rtw_read_rf(rtwdev, RF_PATH_C, 1416 rf_regs[i], RFREG_MASK); 1417 rf_backup[i][RF_PATH_D] = rtw_read_rf(rtwdev, RF_PATH_D, 1418 rf_regs[i], RFREG_MASK); 1419 } 1420 } 1421 1422 static void rtw8814a_iqk_afe_setting(struct rtw_dev *rtwdev, bool do_iqk) 1423 { 1424 if (do_iqk) { 1425 /* IQK AFE setting RX_WAIT_CCA mode */ 1426 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x0e808003); 1427 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x0e808003); 1428 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x0e808003); 1429 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x0e808003); 1430 } else { 1431 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003); 1432 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003); 1433 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003); 1434 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003); 1435 } 1436 1437 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1); 1438 1439 rtw_write8_set(rtwdev, REG_GNT_BT, BIT(2) | BIT(1)); 1440 rtw_write8_clr(rtwdev, REG_GNT_BT, BIT(2) | BIT(1)); 1441 1442 rtw_write32_set(rtwdev, REG_CCK_RPT_FORMAT, BIT(2)); 1443 rtw_write32_clr(rtwdev, REG_CCK_RPT_FORMAT, BIT(2)); 1444 } 1445 1446 static void rtw8814a_iqk_restore_mac_bb(struct rtw_dev *rtwdev, 1447 u32 *mac_backup, u32 *bb_backup, 1448 const u32 *mac_regs, 1449 const u32 *bb_regs) 1450 { 1451 u32 i; 1452 1453 /* Reload MacBB Parameters */ 1454 for (i = 0; i < MAC_REG_NUM_8814; i++) 1455 rtw_write32(rtwdev, mac_regs[i], mac_backup[i]); 1456 1457 for (i = 0; i < BB_REG_NUM_8814; i++) 1458 rtw_write32(rtwdev, bb_regs[i], bb_backup[i]); 1459 } 1460 1461 static void rtw8814a_iqk_restore_rf(struct rtw_dev *rtwdev, 1462 const u32 rf_backup[][4], 1463 const u32 *rf_regs) 1464 { 1465 u32 i; 1466 1467 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x0); 1468 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x0); 1469 rtw_write_rf(rtwdev, RF_PATH_C, RF_LUTWE, RFREG_MASK, 0x0); 1470 rtw_write_rf(rtwdev, RF_PATH_D, RF_LUTWE, RFREG_MASK, 0x0); 1471 1472 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001); 1473 rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x88001); 1474 rtw_write_rf(rtwdev, RF_PATH_C, RF_RXBB2, RFREG_MASK, 0x88001); 1475 rtw_write_rf(rtwdev, RF_PATH_D, RF_RXBB2, RFREG_MASK, 0x88001); 1476 1477 for (i = 0; i < RF_REG_NUM_8814; i++) { 1478 rtw_write_rf(rtwdev, RF_PATH_A, rf_regs[i], 1479 RFREG_MASK, rf_backup[i][RF_PATH_A]); 1480 rtw_write_rf(rtwdev, RF_PATH_B, rf_regs[i], 1481 RFREG_MASK, rf_backup[i][RF_PATH_B]); 1482 rtw_write_rf(rtwdev, RF_PATH_C, rf_regs[i], 1483 RFREG_MASK, rf_backup[i][RF_PATH_C]); 1484 rtw_write_rf(rtwdev, RF_PATH_D, rf_regs[i], 1485 RFREG_MASK, rf_backup[i][RF_PATH_D]); 1486 } 1487 } 1488 1489 static void rtw8814a_iqk_reset_nctl(struct rtw_dev *rtwdev) 1490 { 1491 rtw_write32(rtwdev, 0x1b00, 0xf8000000); 1492 rtw_write32(rtwdev, 0x1b80, 0x00000006); 1493 1494 rtw_write32(rtwdev, 0x1b00, 0xf8000000); 1495 rtw_write32(rtwdev, 0x1b80, 0x00000002); 1496 } 1497 1498 static void rtw8814a_iqk_configure_mac(struct rtw_dev *rtwdev) 1499 { 1500 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f); 1501 rtw_write32_clr(rtwdev, REG_BCN_CTRL, 1502 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION); 1503 1504 /* RX ante off */ 1505 rtw_write8(rtwdev, REG_RXPSEL, 0x00); 1506 /* CCA off */ 1507 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xe); 1508 /* CCK RX path off */ 1509 rtw_write32_set(rtwdev, REG_PRECTRL, BIT_IQ_WGT); 1510 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 1511 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 1512 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 1513 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777); 1514 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, BIT_RFE_SELSW0_D, 0x77); 1515 rtw_write32_mask(rtwdev, REG_PSD, BIT_PSD_INI, 0x0); 1516 1517 rtw_write32_mask(rtwdev, REG_RFE_INV0, 0xf, 0x0); 1518 } 1519 1520 static void rtw8814a_lok_one_shot(struct rtw_dev *rtwdev, u8 path) 1521 { 1522 u32 lok_temp1, lok_temp2; 1523 bool lok_ready; 1524 u8 ii; 1525 1526 /* ADC Clock source */ 1527 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1528 /* LOK: CMD ID = 0 1529 * {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} 1530 */ 1531 rtw_write32(rtwdev, 0x1b00, 0xf8000001 | (BIT(path) << 4)); 1532 1533 usleep_range(1000, 1100); 1534 1535 if (read_poll_timeout(!rtw_read32_mask, lok_ready, lok_ready, 1536 1000, 10000, false, 1537 rtwdev, 0x1b00, BIT(0))) { 1538 rtw_dbg(rtwdev, RTW_DBG_RFK, "==>S%d LOK timed out\n", path); 1539 1540 rtw8814a_iqk_reset_nctl(rtwdev); 1541 1542 rtw_write_rf(rtwdev, path, RF_DTXLOK, RFREG_MASK, 0x08400); 1543 1544 return; 1545 } 1546 1547 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1548 rtw_write32(rtwdev, 0x1bd4, 0x003f0001); 1549 1550 lok_temp2 = rtw_read32_mask(rtwdev, 0x1bfc, 0x003e0000); 1551 lok_temp2 = (lok_temp2 + 0x10) & 0x1f; 1552 1553 lok_temp1 = rtw_read32_mask(rtwdev, 0x1bfc, 0x0000003e); 1554 lok_temp1 = (lok_temp1 + 0x10) & 0x1f; 1555 1556 for (ii = 1; ii < 5; ii++) { 1557 lok_temp1 += (lok_temp1 & BIT(4 - ii)) << (ii * 2); 1558 lok_temp2 += (lok_temp2 & BIT(4 - ii)) << (ii * 2); 1559 } 1560 1561 rtw_dbg(rtwdev, RTW_DBG_RFK, 1562 "path %d lok_temp1 = %#x, lok_temp2 = %#x\n", 1563 path, lok_temp1 >> 4, lok_temp2 >> 4); 1564 1565 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0x07c00, lok_temp1 >> 4); 1566 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0xf8000, lok_temp2 >> 4); 1567 } 1568 1569 static void rtw8814a_iqk_tx_one_shot(struct rtw_dev *rtwdev, u8 path, 1570 u32 *tx_matrix, bool *tx_ok) 1571 { 1572 u8 bw = rtwdev->hal.current_band_width; 1573 u8 cal_retry; 1574 u32 iqk_cmd; 1575 1576 for (cal_retry = 0; cal_retry < 4; cal_retry++) { 1577 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1578 1579 iqk_cmd = 0xf8000001 | ((bw + 3) << 8) | (BIT(path) << 4); 1580 1581 rtw_dbg(rtwdev, RTW_DBG_RFK, "TXK_Trigger = %#x\n", iqk_cmd); 1582 1583 rtw_write32(rtwdev, 0x1b00, iqk_cmd); 1584 1585 usleep_range(10000, 11000); 1586 1587 if (read_poll_timeout(!rtw_read32_mask, *tx_ok, *tx_ok, 1588 1000, 20000, false, 1589 rtwdev, 0x1b00, BIT(0))) { 1590 rtw_dbg(rtwdev, RTW_DBG_RFK, 1591 "tx iqk S%d timed out\n", path); 1592 1593 rtw8814a_iqk_reset_nctl(rtwdev); 1594 } else { 1595 *tx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26)); 1596 1597 if (*tx_ok) 1598 break; 1599 } 1600 } 1601 1602 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b00 = 0x%x\n", 1603 path, rtw_read32(rtwdev, 0x1b00)); 1604 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b08 = 0x%x\n", 1605 path, rtw_read32(rtwdev, 0x1b08)); 1606 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> cal_retry = %x\n", 1607 path, cal_retry); 1608 1609 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1610 1611 if (*tx_ok) { 1612 *tx_matrix = rtw_read32(rtwdev, 0x1b38); 1613 1614 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n", 1615 path, *tx_matrix); 1616 } 1617 } 1618 1619 static void rtw8814a_iqk_rx_one_shot(struct rtw_dev *rtwdev, u8 path, 1620 u32 *tx_matrix, bool *tx_ok) 1621 { 1622 static const u16 iqk_apply[RTW_RF_PATH_MAX] = { 1623 REG_TXAGCIDX, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D 1624 }; 1625 u8 band = rtwdev->hal.current_band_type; 1626 u8 bw = rtwdev->hal.current_band_width; 1627 u32 rx_matrix; 1628 u8 cal_retry; 1629 u32 iqk_cmd; 1630 bool rx_ok; 1631 1632 for (cal_retry = 0; cal_retry < 4; cal_retry++) { 1633 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1634 1635 if (band == RTW_BAND_2G) { 1636 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x1); 1637 rtw_write_rf(rtwdev, path, RF_GAINTX, 0xfffff, 0x51ce1); 1638 1639 switch (path) { 1640 case 0: 1641 case 1: 1642 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 1643 0x54775477); 1644 break; 1645 case 2: 1646 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 1647 0x54775477); 1648 break; 1649 case 3: 1650 rtw_write32(rtwdev, REG_RFE_INVSEL_D, 0x75400000); 1651 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 1652 0x77777777); 1653 break; 1654 } 1655 } 1656 1657 iqk_cmd = 0xf8000001 | ((9 - bw) << 8) | (BIT(path) << 4); 1658 1659 rtw_dbg(rtwdev, RTW_DBG_RFK, "RXK_Trigger = 0x%x\n", iqk_cmd); 1660 1661 rtw_write32(rtwdev, 0x1b00, iqk_cmd); 1662 1663 usleep_range(10000, 11000); 1664 1665 if (read_poll_timeout(!rtw_read32_mask, rx_ok, rx_ok, 1666 1000, 20000, false, 1667 rtwdev, 0x1b00, BIT(0))) { 1668 rtw_dbg(rtwdev, RTW_DBG_RFK, 1669 "rx iqk S%d timed out\n", path); 1670 1671 rtw8814a_iqk_reset_nctl(rtwdev); 1672 } else { 1673 rx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26)); 1674 1675 if (rx_ok) 1676 break; 1677 } 1678 } 1679 1680 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b00 = 0x%x\n", 1681 path, rtw_read32(rtwdev, 0x1b00)); 1682 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b08 = 0x%x\n", 1683 path, rtw_read32(rtwdev, 0x1b08)); 1684 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> cal_retry = %x\n", 1685 path, cal_retry); 1686 1687 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1688 1689 if (rx_ok) { 1690 rtw_write32(rtwdev, 0x1b3c, 0x20000000); 1691 rx_matrix = rtw_read32(rtwdev, 0x1b3c); 1692 1693 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n", 1694 path, rx_matrix); 1695 } 1696 1697 if (*tx_ok) 1698 rtw_write32(rtwdev, 0x1b38, *tx_matrix); 1699 else 1700 rtw_write32_mask(rtwdev, iqk_apply[path], BIT(0), 0x0); 1701 1702 if (!rx_ok) 1703 rtw_write32_mask(rtwdev, iqk_apply[path], 1704 BIT(11) | BIT(10), 0x0); 1705 1706 if (band == RTW_BAND_2G) 1707 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x0); 1708 } 1709 1710 static void rtw8814a_iqk(struct rtw_dev *rtwdev) 1711 { 1712 u8 band = rtwdev->hal.current_band_type; 1713 u8 bw = rtwdev->hal.current_band_width; 1714 u32 tx_matrix[RTW_RF_PATH_MAX]; 1715 bool tx_ok[RTW_RF_PATH_MAX]; 1716 u8 path; 1717 1718 rtw_dbg(rtwdev, RTW_DBG_RFK, "IQK band = %d GHz bw = %d MHz\n", 1719 band == RTW_BAND_2G ? 2 : 5, (1 << (bw + 1)) * 10); 1720 1721 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, BIT(19), 0x1); 1722 rtw_write_rf(rtwdev, RF_PATH_B, RF_TXMOD, BIT(19), 0x1); 1723 rtw_write_rf(rtwdev, RF_PATH_C, RF_TXMOD, BIT(19), 0x1); 1724 rtw_write_rf(rtwdev, RF_PATH_D, RF_TXMOD, BIT(19), 0x1); 1725 1726 rtw_write32_mask(rtwdev, REG_TXAGCIDX, 1727 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1728 rtw_write32_mask(rtwdev, REG_TX_AGC_B, 1729 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1730 rtw_write32_mask(rtwdev, REG_TX_AGC_C, 1731 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1732 rtw_write32_mask(rtwdev, REG_TX_AGC_D, 1733 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1734 1735 if (band == RTW_BAND_5G) 1736 rtw_write32(rtwdev, 0x1b00, 0xf8000ff1); 1737 else 1738 rtw_write32(rtwdev, 0x1b00, 0xf8000ef1); 1739 1740 usleep_range(1000, 1100); 1741 1742 rtw_write32(rtwdev, 0x810, 0x20101063); 1743 rtw_write32(rtwdev, REG_DAC_RSTB, 0x0B00C000); 1744 1745 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1746 rtw8814a_lok_one_shot(rtwdev, path); 1747 1748 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1749 rtw8814a_iqk_tx_one_shot(rtwdev, path, 1750 &tx_matrix[path], &tx_ok[path]); 1751 1752 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1753 rtw8814a_iqk_rx_one_shot(rtwdev, path, 1754 &tx_matrix[path], &tx_ok[path]); 1755 } 1756 1757 static void rtw8814a_do_iqk(struct rtw_dev *rtwdev) 1758 { 1759 static const u32 backup_mac_reg[MAC_REG_NUM_8814] = {0x520, 0x550}; 1760 static const u32 backup_bb_reg[BB_REG_NUM_8814] = { 1761 0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0, 1762 0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910 1763 }; 1764 static const u32 backup_rf_reg[RF_REG_NUM_8814] = {0x0}; 1765 u32 rf_backup[RF_REG_NUM_8814][RTW_RF_PATH_MAX]; 1766 u32 mac_backup[MAC_REG_NUM_8814]; 1767 u32 bb_backup[BB_REG_NUM_8814]; 1768 1769 rtw8814a_iqk_backup_mac_bb(rtwdev, mac_backup, bb_backup, 1770 backup_mac_reg, backup_bb_reg); 1771 rtw8814a_iqk_afe_setting(rtwdev, true); 1772 rtw8814a_iqk_backup_rf(rtwdev, rf_backup, backup_rf_reg); 1773 rtw8814a_iqk_configure_mac(rtwdev); 1774 rtw8814a_iqk(rtwdev); 1775 rtw8814a_iqk_reset_nctl(rtwdev); /* for 3-wire to BB use */ 1776 rtw8814a_iqk_afe_setting(rtwdev, false); 1777 rtw8814a_iqk_restore_mac_bb(rtwdev, mac_backup, bb_backup, 1778 backup_mac_reg, backup_bb_reg); 1779 rtw8814a_iqk_restore_rf(rtwdev, rf_backup, backup_rf_reg); 1780 } 1781 1782 static void rtw8814a_phy_calibration(struct rtw_dev *rtwdev) 1783 { 1784 rtw8814a_do_iqk(rtwdev); 1785 } 1786 1787 static void rtw8814a_coex_cfg_init(struct rtw_dev *rtwdev) 1788 { 1789 } 1790 1791 static void rtw8814a_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 1792 u8 pos_type) 1793 { 1794 /* Override rtw_coex_coex_ctrl_owner(). RF path C does not 1795 * function when BIT_LTE_MUX_CTRL_PATH is set. 1796 */ 1797 rtw_write8_clr(rtwdev, REG_SYS_SDIO_CTRL + 3, 1798 BIT_LTE_MUX_CTRL_PATH >> 24); 1799 } 1800 1801 static void rtw8814a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1802 { 1803 } 1804 1805 static void rtw8814a_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1806 { 1807 } 1808 1809 static void rtw8814a_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1810 { 1811 struct rtw_coex *coex = &rtwdev->coex; 1812 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1813 1814 /* Only needed to make rtw8814a_coex_cfg_ant_switch() run. */ 1815 coex_rfe->ant_switch_exist = true; 1816 } 1817 1818 static void rtw8814a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1819 { 1820 } 1821 1822 static void rtw8814a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1823 { 1824 } 1825 1826 static void rtw8814a_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1827 u8 tx_pwr_idx_offset, 1828 s8 *txagc_idx, u8 *swing_idx) 1829 { 1830 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1831 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1832 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1833 u8 swing_index = dm_info->default_ofdm_index; 1834 u8 max_tx_pwr_idx_offset = 0xf; 1835 u8 swing_lower_bound = 0; 1836 s8 agc_index = 0; 1837 1838 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1839 1840 if (delta_pwr_idx >= 0) { 1841 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1842 agc_index = delta_pwr_idx; 1843 swing_index = dm_info->default_ofdm_index; 1844 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1845 agc_index = tx_pwr_idx_offset; 1846 swing_index = dm_info->default_ofdm_index + 1847 delta_pwr_idx - tx_pwr_idx_offset; 1848 swing_index = min_t(u8, swing_index, swing_upper_bound); 1849 } 1850 } else { 1851 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1852 swing_index = 1853 dm_info->default_ofdm_index + delta_pwr_idx; 1854 else 1855 swing_index = swing_lower_bound; 1856 swing_index = max_t(u8, swing_index, swing_lower_bound); 1857 1858 agc_index = 0; 1859 } 1860 1861 if (swing_index >= RTW_TXSCALE_SIZE) { 1862 rtw_warn(rtwdev, "swing index overflow\n"); 1863 swing_index = RTW_TXSCALE_SIZE - 1; 1864 } 1865 *txagc_idx = agc_index; 1866 *swing_idx = swing_index; 1867 } 1868 1869 static void rtw8814a_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1870 u8 pwr_idx_offset) 1871 { 1872 static const u32 txagc_reg[RTW_RF_PATH_MAX] = { 1873 REG_TX_AGC_A, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D 1874 }; 1875 static const u32 txscale_reg[RTW_RF_PATH_MAX] = { 1876 REG_TXSCALE_A, REG_TXSCALE_B, REG_TXSCALE_C, REG_TXSCALE_D 1877 }; 1878 s8 txagc_idx; 1879 u8 swing_idx; 1880 1881 rtw8814a_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1882 &txagc_idx, &swing_idx); 1883 rtw_write32_mask(rtwdev, txagc_reg[path], GENMASK(29, 25), 1884 txagc_idx); 1885 rtw_write32_mask(rtwdev, txscale_reg[path], BB_SWING_MASK, 1886 rtw8814a_txscale_tbl[swing_idx]); 1887 } 1888 1889 static void rtw8814a_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1890 { 1891 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1892 u8 band_width = rtwdev->hal.current_band_width; 1893 u8 channel = rtwdev->hal.current_channel; 1894 u8 tx_rate = rtwdev->dm_info.tx_rate; 1895 u8 regd = rtw_regd_get(rtwdev); 1896 u8 pwr_idx_offset, tx_pwr_idx; 1897 1898 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1899 band_width, channel, regd); 1900 1901 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1902 1903 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1904 1905 rtw8814a_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1906 } 1907 1908 static void rtw8814a_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1909 struct rtw_swing_table *swing_table, 1910 u8 path) 1911 { 1912 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1913 u8 power_idx_cur, power_idx_last; 1914 u8 delta; 1915 1916 /* 8814A only has one thermal meter at PATH A */ 1917 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1918 1919 power_idx_last = dm_info->delta_power_index[path]; 1920 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1921 path, RF_PATH_A, delta); 1922 1923 /* if delta of power indexes are the same, just skip */ 1924 if (power_idx_cur == power_idx_last) 1925 return; 1926 1927 dm_info->delta_power_index[path] = power_idx_cur; 1928 rtw8814a_pwrtrack_set(rtwdev, path); 1929 } 1930 1931 static void rtw8814a_phy_pwrtrack(struct rtw_dev *rtwdev) 1932 { 1933 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1934 struct rtw_swing_table swing_table; 1935 u8 thermal_value, path; 1936 1937 rtw_phy_config_swing_table(rtwdev, &swing_table); 1938 1939 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1940 return; 1941 1942 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1943 1944 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1945 1946 if (dm_info->pwr_trk_init_trigger) 1947 dm_info->pwr_trk_init_trigger = false; 1948 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1949 RF_PATH_A)) 1950 goto iqk; 1951 1952 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) 1953 rtw8814a_phy_pwrtrack_path(rtwdev, &swing_table, path); 1954 1955 iqk: 1956 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1957 rtw8814a_do_iqk(rtwdev); 1958 } 1959 1960 static void rtw8814a_pwr_track(struct rtw_dev *rtwdev) 1961 { 1962 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1963 1964 if (!dm_info->pwr_trk_triggered) { 1965 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1966 GENMASK(17, 16), 0x03); 1967 dm_info->pwr_trk_triggered = true; 1968 return; 1969 } 1970 1971 rtw8814a_phy_pwrtrack(rtwdev); 1972 dm_info->pwr_trk_triggered = false; 1973 } 1974 1975 static void rtw8814a_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1976 { 1977 static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed}; 1978 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1979 1980 /* Override rtw_phy_cck_pd_lv_link(). It implements something 1981 * like type 2/3/4. We need type 1 here. 1982 */ 1983 if (rtw_is_assoc(rtwdev)) { 1984 if (dm_info->min_rssi > 60) { 1985 new_lvl = CCK_PD_LV3; 1986 } else if (dm_info->min_rssi > 35) { 1987 new_lvl = CCK_PD_LV2; 1988 } else if (dm_info->min_rssi > 20) { 1989 if (dm_info->cck_fa_avg > 500) 1990 new_lvl = CCK_PD_LV2; 1991 else if (dm_info->cck_fa_avg < 250) 1992 new_lvl = CCK_PD_LV1; 1993 else 1994 return; 1995 } else { 1996 new_lvl = CCK_PD_LV1; 1997 } 1998 } 1999 2000 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 2001 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 2002 2003 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 2004 return; 2005 2006 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 2007 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 2008 2009 rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]); 2010 } 2011 2012 static void rtw8814a_led_set(struct led_classdev *led, 2013 enum led_brightness brightness) 2014 { 2015 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev); 2016 u32 led_gpio_cfg; 2017 2018 led_gpio_cfg = rtw_read32(rtwdev, REG_GPIO_PIN_CTRL_2); 2019 led_gpio_cfg |= BIT(16) | BIT(17) | BIT(21) | BIT(22); 2020 2021 if (brightness == LED_OFF) { 2022 led_gpio_cfg |= BIT(8) | BIT(9) | BIT(13) | BIT(14); 2023 } else { 2024 led_gpio_cfg &= ~(BIT(8) | BIT(9) | BIT(13) | BIT(14)); 2025 led_gpio_cfg &= ~(BIT(0) | BIT(1) | BIT(5) | BIT(6)); 2026 } 2027 2028 rtw_write32(rtwdev, REG_GPIO_PIN_CTRL_2, led_gpio_cfg); 2029 } 2030 2031 static void rtw8814a_fill_txdesc_checksum(struct rtw_dev *rtwdev, 2032 struct rtw_tx_pkt_info *pkt_info, 2033 u8 *txdesc) 2034 { 2035 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 2036 2037 fill_txdesc_checksum_common(txdesc, words); 2038 } 2039 2040 static const struct rtw_chip_ops rtw8814a_ops = { 2041 .power_on = rtw_power_on, 2042 .power_off = rtw_power_off, 2043 .phy_set_param = rtw8814a_phy_set_param, 2044 .read_efuse = rtw8814a_read_efuse, 2045 .query_phy_status = rtw8814a_query_phy_status, 2046 .set_channel = rtw8814a_set_channel, 2047 .mac_init = rtw8814a_mac_init, 2048 .read_rf = rtw_phy_read_rf, 2049 .write_rf = rtw_phy_write_rf_reg_sipi, 2050 .set_tx_power_index = rtw8814a_set_tx_power_index, 2051 .set_antenna = NULL, 2052 .cfg_ldo25 = rtw8814a_cfg_ldo25, 2053 .efuse_grant = rtw8814a_efuse_grant, 2054 .false_alarm_statistics = rtw8814a_false_alarm_statistics, 2055 .phy_calibration = rtw8814a_phy_calibration, 2056 .cck_pd_set = rtw8814a_phy_cck_pd_set, 2057 .pwr_track = rtw8814a_pwr_track, 2058 .config_bfee = NULL, 2059 .set_gid_table = NULL, 2060 .cfg_csi_rate = NULL, 2061 .led_set = rtw8814a_led_set, 2062 .fill_txdesc_checksum = rtw8814a_fill_txdesc_checksum, 2063 2064 .coex_set_init = rtw8814a_coex_cfg_init, 2065 .coex_set_ant_switch = rtw8814a_coex_cfg_ant_switch, 2066 .coex_set_gnt_fix = rtw8814a_coex_cfg_gnt_fix, 2067 .coex_set_gnt_debug = rtw8814a_coex_cfg_gnt_debug, 2068 .coex_set_rfe_type = rtw8814a_coex_cfg_rfe_type, 2069 .coex_set_wl_tx_power = rtw8814a_coex_cfg_wl_tx_power, 2070 .coex_set_wl_rx_gain = rtw8814a_coex_cfg_wl_rx_gain, 2071 }; 2072 2073 static const struct rtw_rqpn rqpn_table_8814a[] = { 2074 /* SDIO */ 2075 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, /* vo vi */ 2076 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, /* be bk */ 2077 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, /* mg hi */ 2078 /* PCIE */ 2079 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2080 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2081 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2082 /* USB, 2 bulk out */ 2083 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH, 2084 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2085 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2086 /* USB, 3 bulk out */ 2087 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2088 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2089 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2090 /* USB, 4 bulk out */ 2091 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2092 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2093 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2094 }; 2095 2096 static const struct rtw_prioq_addrs prioq_addrs_8814a = { 2097 .prio[RTW_DMA_MAPPING_EXTRA] = { 2098 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 2099 }, 2100 .prio[RTW_DMA_MAPPING_LOW] = { 2101 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 2102 }, 2103 .prio[RTW_DMA_MAPPING_NORMAL] = { 2104 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 2105 }, 2106 .prio[RTW_DMA_MAPPING_HIGH] = { 2107 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 2108 }, 2109 .wsize = true, 2110 }; 2111 2112 static const struct rtw_page_table page_table_8814a[] = { 2113 /* SDIO */ 2114 {0, 0, 0, 0, 0}, /* hq nq lq exq gapq */ 2115 /* PCIE */ 2116 {32, 32, 32, 32, 0}, 2117 /* USB, 2 bulk out */ 2118 {32, 32, 32, 32, 0}, 2119 /* USB, 3 bulk out */ 2120 {32, 32, 32, 32, 0}, 2121 /* USB, 4 bulk out */ 2122 {32, 32, 32, 32, 0}, 2123 }; 2124 2125 static const struct rtw_intf_phy_para_table phy_para_table_8814a = {}; 2126 2127 static const struct rtw_hw_reg rtw8814a_dig[] = { 2128 [0] = { .addr = 0xc50, .mask = 0x7f }, 2129 [1] = { .addr = 0xe50, .mask = 0x7f }, 2130 [2] = { .addr = 0x1850, .mask = 0x7f }, 2131 [3] = { .addr = 0x1a50, .mask = 0x7f }, 2132 }; 2133 2134 static const struct rtw_rfe_def rtw8814a_rfe_defs[] = { 2135 [0] = { .phy_pg_tbl = &rtw8814a_bb_pg_type0_tbl, 2136 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type0_tbl, 2137 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_type0_tbl }, 2138 [1] = { .phy_pg_tbl = &rtw8814a_bb_pg_tbl, 2139 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type1_tbl, 2140 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_tbl }, 2141 }; 2142 2143 /* rssi in percentage % (dbm = % - 100) */ 2144 static const u8 wl_rssi_step_8814a[] = {60, 50, 44, 30}; 2145 static const u8 bt_rssi_step_8814a[] = {30, 30, 30, 30}; 2146 2147 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2148 static const struct coex_rf_para rf_para_tx_8814a[] = { 2149 {0, 0, false, 7}, /* for normal */ 2150 {0, 16, false, 7}, /* for WL-CPT */ 2151 {4, 0, true, 1}, 2152 {3, 6, true, 1}, 2153 {2, 9, true, 1}, 2154 {1, 13, true, 1} 2155 }; 2156 2157 static const struct coex_rf_para rf_para_rx_8814a[] = { 2158 {0, 0, false, 7}, /* for normal */ 2159 {0, 16, false, 7}, /* for WL-CPT */ 2160 {4, 0, true, 1}, 2161 {3, 6, true, 1}, 2162 {2, 9, true, 1}, 2163 {1, 13, true, 1} 2164 }; 2165 2166 static_assert(ARRAY_SIZE(rf_para_tx_8814a) == ARRAY_SIZE(rf_para_rx_8814a)); 2167 2168 const struct rtw_chip_info rtw8814a_hw_spec = { 2169 .ops = &rtw8814a_ops, 2170 .id = RTW_CHIP_TYPE_8814A, 2171 .fw_name = "rtw88/rtw8814a_fw.bin", 2172 .wlan_cpu = RTW_WCPU_11AC, 2173 .tx_pkt_desc_sz = 40, 2174 .tx_buf_desc_sz = 16, 2175 .rx_pkt_desc_sz = 24, 2176 .rx_buf_desc_sz = 8, 2177 .phy_efuse_size = 1024, 2178 .log_efuse_size = 512, 2179 .ptct_efuse_size = 0, 2180 .txff_size = (2048 - 10) * TX_PAGE_SIZE, 2181 .rxff_size = 23552, 2182 .rsvd_drv_pg_num = 8, 2183 .band = RTW_BAND_2G | RTW_BAND_5G, 2184 .page_size = TX_PAGE_SIZE, 2185 .csi_buf_pg_num = 0, 2186 .dig_min = 0x1c, 2187 .txgi_factor = 1, 2188 .is_pwr_by_rate_dec = true, 2189 .rx_ldpc = true, 2190 .max_power_index = 0x3f, 2191 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 2192 .usb_tx_agg_desc_num = 3, 2193 .hw_feature_report = false, 2194 .c2h_ra_report_size = 6, 2195 .old_datarate_fb_limit = false, 2196 .ht_supported = true, 2197 .vht_supported = true, 2198 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2199 .sys_func_en = 0xDC, 2200 .pwr_on_seq = card_enable_flow_8814a, 2201 .pwr_off_seq = card_disable_flow_8814a, 2202 .rqpn_table = rqpn_table_8814a, 2203 .prioq_addrs = &prioq_addrs_8814a, 2204 .page_table = page_table_8814a, 2205 .intf_table = &phy_para_table_8814a, 2206 .dig = rtw8814a_dig, 2207 .dig_cck = NULL, 2208 .rf_base_addr = {0x2800, 0x2c00, 0x3800, 0x3c00}, 2209 .rf_sipi_addr = {0xc90, 0xe90, 0x1890, 0x1a90}, 2210 .ltecoex_addr = NULL, 2211 .mac_tbl = &rtw8814a_mac_tbl, 2212 .agc_tbl = &rtw8814a_agc_tbl, 2213 .bb_tbl = &rtw8814a_bb_tbl, 2214 .rf_tbl = {&rtw8814a_rf_a_tbl, &rtw8814a_rf_b_tbl, 2215 &rtw8814a_rf_c_tbl, &rtw8814a_rf_d_tbl}, 2216 .rfe_defs = rtw8814a_rfe_defs, 2217 .rfe_defs_size = ARRAY_SIZE(rtw8814a_rfe_defs), 2218 .iqk_threshold = 8, 2219 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2220 2221 .coex_para_ver = 0, 2222 .bt_desired_ver = 0, 2223 .scbd_support = false, 2224 .new_scbd10_def = false, 2225 .ble_hid_profile_support = false, 2226 .wl_mimo_ps_support = false, 2227 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2228 .bt_rssi_type = COEX_BTRSSI_RATIO, 2229 .ant_isolation = 15, 2230 .rssi_tolerance = 2, 2231 .wl_rssi_step = wl_rssi_step_8814a, 2232 .bt_rssi_step = bt_rssi_step_8814a, 2233 .table_sant_num = 0, 2234 .table_sant = NULL, 2235 .table_nsant_num = 0, 2236 .table_nsant = NULL, 2237 .tdma_sant_num = 0, 2238 .tdma_sant = NULL, 2239 .tdma_nsant_num = 0, 2240 .tdma_nsant = NULL, 2241 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8814a), 2242 .wl_rf_para_tx = rf_para_tx_8814a, 2243 .wl_rf_para_rx = rf_para_rx_8814a, 2244 .bt_afh_span_bw20 = 0x24, 2245 .bt_afh_span_bw40 = 0x36, 2246 .afh_5g_num = 0, 2247 .afh_5g = NULL, 2248 .coex_info_hw_regs_num = 0, 2249 .coex_info_hw_regs = NULL, 2250 }; 2251 EXPORT_SYMBOL(rtw8814a_hw_spec); 2252 2253 MODULE_FIRMWARE("rtw88/rtw8814a_fw.bin"); 2254 2255 MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>"); 2256 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8814a driver"); 2257 MODULE_LICENSE("Dual BSD/GPL"); 2258