xref: /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "link_encoder.h"
29 #include "stream_encoder.h"
30 
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 
36 #include "irq/dce110/irq_service_dce110.h"
37 #include "dce/dce_mem_input.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_clock_source.h"
45 
46 #include "dce/dce_hwseq.h"
47 #include "dce112/dce112_hwseq.h"
48 #include "dce/dce_abm.h"
49 #include "dce/dce_dmcu.h"
50 #include "dce/dce_aux.h"
51 #include "dce/dce_i2c.h"
52 #include "dce/dce_panel_cntl.h"
53 
54 #include "reg_helper.h"
55 
56 #include "dce/dce_11_2_d.h"
57 #include "dce/dce_11_2_sh_mask.h"
58 
59 #include "dce100/dce100_resource.h"
60 #include "dce112_resource.h"
61 
62 #define DC_LOGGER				\
63 		dc->ctx->logger
64 
65 #ifndef mmDP_DPHY_INTERNAL_CTRL
66 	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
67 	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
68 	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
69 	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
70 	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
71 	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
72 	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
73 	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
74 	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
75 	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
76 #endif
77 
78 #ifndef mmBIOS_SCRATCH_2
79 	#define mmBIOS_SCRATCH_2 0x05CB
80 	#define mmBIOS_SCRATCH_3 0x05CC
81 	#define mmBIOS_SCRATCH_6 0x05CF
82 #endif
83 
84 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
85 	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
86 	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
87 	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
88 	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
89 	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
90 	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
91 	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
92 	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
93 #endif
94 
95 #ifndef mmDP_DPHY_FAST_TRAINING
96 	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
97 	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
98 	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
99 	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
100 	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
101 	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
102 	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
103 	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
104 #endif
105 
106 enum dce112_clk_src_array_id {
107 	DCE112_CLK_SRC_PLL0,
108 	DCE112_CLK_SRC_PLL1,
109 	DCE112_CLK_SRC_PLL2,
110 	DCE112_CLK_SRC_PLL3,
111 	DCE112_CLK_SRC_PLL4,
112 	DCE112_CLK_SRC_PLL5,
113 
114 	DCE112_CLK_SRC_TOTAL
115 };
116 
117 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
118 	{
119 		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
121 	},
122 	{
123 		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
125 	},
126 	{
127 		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
129 	},
130 	{
131 		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
133 	},
134 	{
135 		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
136 		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
137 	},
138 	{
139 		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
140 		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
141 	}
142 };
143 
144 /* set register offset */
145 #define SR(reg_name)\
146 	.reg_name = mm ## reg_name
147 
148 /* set register offset with instance */
149 #define SRI(reg_name, block, id)\
150 	.reg_name = mm ## block ## id ## _ ## reg_name
151 
152 static const struct dce_dmcu_registers dmcu_regs = {
153 		DMCU_DCE110_COMMON_REG_LIST()
154 };
155 
156 static const struct dce_dmcu_shift dmcu_shift = {
157 		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
158 };
159 
160 static const struct dce_dmcu_mask dmcu_mask = {
161 		DMCU_MASK_SH_LIST_DCE110(_MASK)
162 };
163 
164 static const struct dce_abm_registers abm_regs = {
165 		ABM_DCE110_COMMON_REG_LIST()
166 };
167 
168 static const struct dce_abm_shift abm_shift = {
169 		ABM_MASK_SH_LIST_DCE110(__SHIFT)
170 };
171 
172 static const struct dce_abm_mask abm_mask = {
173 		ABM_MASK_SH_LIST_DCE110(_MASK)
174 };
175 
176 static const struct dce110_aux_registers_shift aux_shift = {
177 	DCE_AUX_MASK_SH_LIST(__SHIFT)
178 };
179 
180 static const struct dce110_aux_registers_mask aux_mask = {
181 	DCE_AUX_MASK_SH_LIST(_MASK)
182 };
183 
184 #define ipp_regs(id)\
185 [id] = {\
186 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
187 }
188 
189 static const struct dce_ipp_registers ipp_regs[] = {
190 		ipp_regs(0),
191 		ipp_regs(1),
192 		ipp_regs(2),
193 		ipp_regs(3),
194 		ipp_regs(4),
195 		ipp_regs(5)
196 };
197 
198 static const struct dce_ipp_shift ipp_shift = {
199 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
200 };
201 
202 static const struct dce_ipp_mask ipp_mask = {
203 		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
204 };
205 
206 #define transform_regs(id)\
207 [id] = {\
208 		XFM_COMMON_REG_LIST_DCE110(id)\
209 }
210 
211 static const struct dce_transform_registers xfm_regs[] = {
212 		transform_regs(0),
213 		transform_regs(1),
214 		transform_regs(2),
215 		transform_regs(3),
216 		transform_regs(4),
217 		transform_regs(5)
218 };
219 
220 static const struct dce_transform_shift xfm_shift = {
221 		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
222 };
223 
224 static const struct dce_transform_mask xfm_mask = {
225 		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
226 };
227 
228 #define aux_regs(id)\
229 [id] = {\
230 	AUX_REG_LIST(id)\
231 }
232 
233 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
234 		aux_regs(0),
235 		aux_regs(1),
236 		aux_regs(2),
237 		aux_regs(3),
238 		aux_regs(4),
239 		aux_regs(5)
240 };
241 
242 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
243 	{ DCE_PANEL_CNTL_REG_LIST() }
244 };
245 
246 static const struct dce_panel_cntl_shift panel_cntl_shift = {
247 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
248 };
249 
250 static const struct dce_panel_cntl_mask panel_cntl_mask = {
251 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
252 };
253 
254 #define hpd_regs(id)\
255 [id] = {\
256 	HPD_REG_LIST(id)\
257 }
258 
259 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
260 		hpd_regs(0),
261 		hpd_regs(1),
262 		hpd_regs(2),
263 		hpd_regs(3),
264 		hpd_regs(4),
265 		hpd_regs(5)
266 };
267 
268 #define link_regs(id)\
269 [id] = {\
270 	LE_DCE110_REG_LIST(id)\
271 }
272 
273 static const struct dce110_link_enc_registers link_enc_regs[] = {
274 	link_regs(0),
275 	link_regs(1),
276 	link_regs(2),
277 	link_regs(3),
278 	link_regs(4),
279 	link_regs(5),
280 	link_regs(6),
281 };
282 
283 #define stream_enc_regs(id)\
284 [id] = {\
285 	SE_COMMON_REG_LIST(id),\
286 	.TMDS_CNTL = 0,\
287 }
288 
289 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
290 	stream_enc_regs(0),
291 	stream_enc_regs(1),
292 	stream_enc_regs(2),
293 	stream_enc_regs(3),
294 	stream_enc_regs(4),
295 	stream_enc_regs(5)
296 };
297 
298 static const struct dce_stream_encoder_shift se_shift = {
299 		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
300 };
301 
302 static const struct dce_stream_encoder_mask se_mask = {
303 		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
304 };
305 
306 #define opp_regs(id)\
307 [id] = {\
308 	OPP_DCE_112_REG_LIST(id),\
309 }
310 
311 static const struct dce_opp_registers opp_regs[] = {
312 	opp_regs(0),
313 	opp_regs(1),
314 	opp_regs(2),
315 	opp_regs(3),
316 	opp_regs(4),
317 	opp_regs(5)
318 };
319 
320 static const struct dce_opp_shift opp_shift = {
321 	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
322 };
323 
324 static const struct dce_opp_mask opp_mask = {
325 	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
326 };
327 
328 #define aux_engine_regs(id)\
329 [id] = {\
330 	AUX_COMMON_REG_LIST(id), \
331 	.AUX_RESET_MASK = 0 \
332 }
333 
334 static const struct dce110_aux_registers aux_engine_regs[] = {
335 		aux_engine_regs(0),
336 		aux_engine_regs(1),
337 		aux_engine_regs(2),
338 		aux_engine_regs(3),
339 		aux_engine_regs(4),
340 		aux_engine_regs(5)
341 };
342 
343 #define audio_regs(id)\
344 [id] = {\
345 	AUD_COMMON_REG_LIST(id)\
346 }
347 
348 static const struct dce_audio_registers audio_regs[] = {
349 	audio_regs(0),
350 	audio_regs(1),
351 	audio_regs(2),
352 	audio_regs(3),
353 	audio_regs(4),
354 	audio_regs(5)
355 };
356 
357 static const struct dce_audio_shift audio_shift = {
358 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
359 };
360 
361 static const struct dce_audio_mask audio_mask = {
362 		AUD_COMMON_MASK_SH_LIST(_MASK)
363 };
364 
365 #define clk_src_regs(index, id)\
366 [index] = {\
367 	CS_COMMON_REG_LIST_DCE_112(id),\
368 }
369 
370 static const struct dce110_clk_src_regs clk_src_regs[] = {
371 	clk_src_regs(0, A),
372 	clk_src_regs(1, B),
373 	clk_src_regs(2, C),
374 	clk_src_regs(3, D),
375 	clk_src_regs(4, E),
376 	clk_src_regs(5, F)
377 };
378 
379 static const struct dce110_clk_src_shift cs_shift = {
380 		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
381 };
382 
383 static const struct dce110_clk_src_mask cs_mask = {
384 		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
385 };
386 
387 static const struct bios_registers bios_regs = {
388 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
389 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
390 };
391 
392 static const struct resource_caps polaris_10_resource_cap = {
393 		.num_timing_generator = 6,
394 		.num_audio = 6,
395 		.num_stream_encoder = 6,
396 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
397 		.num_ddc = 6,
398 };
399 
400 static const struct resource_caps polaris_11_resource_cap = {
401 		.num_timing_generator = 5,
402 		.num_audio = 5,
403 		.num_stream_encoder = 5,
404 		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
405 		.num_ddc = 5,
406 };
407 
408 static const struct dc_plane_cap plane_cap = {
409 	.type = DC_PLANE_TYPE_DCE_RGB,
410 
411 	.pixel_format_support = {
412 			.argb8888 = true,
413 			.nv12 = false,
414 			.fp16 = true
415 	},
416 
417 	.max_upscale_factor = {
418 			.argb8888 = 16000,
419 			.nv12 = 1,
420 			.fp16 = 1
421 	},
422 
423 	.max_downscale_factor = {
424 			.argb8888 = 250,
425 			.nv12 = 1,
426 			.fp16 = 1
427 	},
428 	64,
429 	64
430 };
431 
432 static const struct dc_debug_options debug_defaults = {
433 		.enable_legacy_fast_update = true,
434 };
435 
436 #define CTX  ctx
437 #define REG(reg) mm ## reg
438 
439 #ifndef mmCC_DC_HDMI_STRAPS
440 #define mmCC_DC_HDMI_STRAPS 0x4819
441 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
442 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
443 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
444 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
445 #endif
446 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)447 static int map_transmitter_id_to_phy_instance(
448 	enum transmitter transmitter)
449 {
450 	switch (transmitter) {
451 	case TRANSMITTER_UNIPHY_A:
452 		return 0;
453 	case TRANSMITTER_UNIPHY_B:
454 		return 1;
455 	case TRANSMITTER_UNIPHY_C:
456 		return 2;
457 	case TRANSMITTER_UNIPHY_D:
458 		return 3;
459 	case TRANSMITTER_UNIPHY_E:
460 		return 4;
461 	case TRANSMITTER_UNIPHY_F:
462 		return 5;
463 	case TRANSMITTER_UNIPHY_G:
464 		return 6;
465 	default:
466 		ASSERT(0);
467 		return 0;
468 	}
469 }
470 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)471 static void read_dce_straps(
472 	struct dc_context *ctx,
473 	struct resource_straps *straps)
474 {
475 	REG_GET_2(CC_DC_HDMI_STRAPS,
476 			HDMI_DISABLE, &straps->hdmi_disable,
477 			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
478 
479 	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
480 }
481 
create_audio(struct dc_context * ctx,unsigned int inst)482 static struct audio *create_audio(
483 		struct dc_context *ctx, unsigned int inst)
484 {
485 	return dce_audio_create(ctx, inst,
486 			&audio_regs[inst], &audio_shift, &audio_mask);
487 }
488 
489 
dce112_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)490 static struct timing_generator *dce112_timing_generator_create(
491 		struct dc_context *ctx,
492 		uint32_t instance,
493 		const struct dce110_timing_generator_offsets *offsets)
494 {
495 	struct dce110_timing_generator *tg110 =
496 		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
497 
498 	if (!tg110)
499 		return NULL;
500 
501 	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
502 	return &tg110->base;
503 }
504 
dce112_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)505 static struct stream_encoder *dce112_stream_encoder_create(
506 	enum engine_id eng_id,
507 	struct dc_context *ctx)
508 {
509 	struct dce110_stream_encoder *enc110 =
510 		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
511 
512 	if (!enc110)
513 		return NULL;
514 
515 	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
516 					&stream_enc_regs[eng_id],
517 					&se_shift, &se_mask);
518 	return &enc110->base;
519 }
520 
521 #define SRII(reg_name, block, id)\
522 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
523 
524 static const struct dce_hwseq_registers hwseq_reg = {
525 		HWSEQ_DCE112_REG_LIST()
526 };
527 
528 static const struct dce_hwseq_shift hwseq_shift = {
529 		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
530 };
531 
532 static const struct dce_hwseq_mask hwseq_mask = {
533 		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
534 };
535 
dce112_hwseq_create(struct dc_context * ctx)536 static struct dce_hwseq *dce112_hwseq_create(
537 	struct dc_context *ctx)
538 {
539 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
540 
541 	if (hws) {
542 		hws->ctx = ctx;
543 		hws->regs = &hwseq_reg;
544 		hws->shifts = &hwseq_shift;
545 		hws->masks = &hwseq_mask;
546 	}
547 	return hws;
548 }
549 
550 static const struct resource_create_funcs res_create_funcs = {
551 	.read_dce_straps = read_dce_straps,
552 	.create_audio = create_audio,
553 	.create_stream_encoder = dce112_stream_encoder_create,
554 	.create_hwseq = dce112_hwseq_create,
555 };
556 
557 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
558 static const struct dce_mem_input_registers mi_regs[] = {
559 		mi_inst_regs(0),
560 		mi_inst_regs(1),
561 		mi_inst_regs(2),
562 		mi_inst_regs(3),
563 		mi_inst_regs(4),
564 		mi_inst_regs(5),
565 };
566 
567 static const struct dce_mem_input_shift mi_shifts = {
568 		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
569 };
570 
571 static const struct dce_mem_input_mask mi_masks = {
572 		MI_DCE11_2_MASK_SH_LIST(_MASK)
573 };
574 
dce112_mem_input_create(struct dc_context * ctx,uint32_t inst)575 static struct mem_input *dce112_mem_input_create(
576 	struct dc_context *ctx,
577 	uint32_t inst)
578 {
579 	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
580 					       GFP_KERNEL);
581 
582 	if (!dce_mi) {
583 		BREAK_TO_DEBUGGER();
584 		return NULL;
585 	}
586 
587 	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
588 	return &dce_mi->base;
589 }
590 
dce112_transform_destroy(struct transform ** xfm)591 static void dce112_transform_destroy(struct transform **xfm)
592 {
593 	kfree(TO_DCE_TRANSFORM(*xfm));
594 	*xfm = NULL;
595 }
596 
dce112_transform_create(struct dc_context * ctx,uint32_t inst)597 static struct transform *dce112_transform_create(
598 	struct dc_context *ctx,
599 	uint32_t inst)
600 {
601 	struct dce_transform *transform =
602 		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
603 
604 	if (!transform)
605 		return NULL;
606 
607 	dce_transform_construct(transform, ctx, inst,
608 				&xfm_regs[inst], &xfm_shift, &xfm_mask);
609 	transform->lb_memory_size = 0x1404; /*5124*/
610 	return &transform->base;
611 }
612 
613 static const struct encoder_feature_support link_enc_feature = {
614 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
615 		.max_hdmi_pixel_clock = 600000,
616 		.hdmi_ycbcr420_supported = true,
617 		.dp_ycbcr420_supported = false,
618 		.flags.bits.IS_HBR2_CAPABLE = true,
619 		.flags.bits.IS_HBR3_CAPABLE = true,
620 		.flags.bits.IS_TPS3_CAPABLE = true,
621 		.flags.bits.IS_TPS4_CAPABLE = true
622 };
623 
dce112_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)624 static struct link_encoder *dce112_link_encoder_create(
625 	struct dc_context *ctx,
626 	const struct encoder_init_data *enc_init_data)
627 {
628 	struct dce110_link_encoder *enc110 =
629 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
630 	int link_regs_id;
631 
632 	if (!enc110)
633 		return NULL;
634 
635 	link_regs_id =
636 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
637 
638 	dce110_link_encoder_construct(enc110,
639 				      enc_init_data,
640 				      &link_enc_feature,
641 				      &link_enc_regs[link_regs_id],
642 				      &link_enc_aux_regs[enc_init_data->channel - 1],
643 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
644 	return &enc110->base;
645 }
646 
dce112_panel_cntl_create(const struct panel_cntl_init_data * init_data)647 static struct panel_cntl *dce112_panel_cntl_create(const struct panel_cntl_init_data *init_data)
648 {
649 	struct dce_panel_cntl *panel_cntl =
650 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
651 
652 	if (!panel_cntl)
653 		return NULL;
654 
655 	dce_panel_cntl_construct(panel_cntl,
656 			init_data,
657 			&panel_cntl_regs[init_data->inst],
658 			&panel_cntl_shift,
659 			&panel_cntl_mask);
660 
661 	return &panel_cntl->base;
662 }
663 
dce112_ipp_create(struct dc_context * ctx,uint32_t inst)664 static struct input_pixel_processor *dce112_ipp_create(
665 	struct dc_context *ctx, uint32_t inst)
666 {
667 	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
668 
669 	if (!ipp) {
670 		BREAK_TO_DEBUGGER();
671 		return NULL;
672 	}
673 
674 	dce_ipp_construct(ipp, ctx, inst,
675 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
676 	return &ipp->base;
677 }
678 
dce112_opp_create(struct dc_context * ctx,uint32_t inst)679 static struct output_pixel_processor *dce112_opp_create(
680 	struct dc_context *ctx,
681 	uint32_t inst)
682 {
683 	struct dce110_opp *opp =
684 		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
685 
686 	if (!opp)
687 		return NULL;
688 
689 	dce110_opp_construct(opp,
690 			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
691 	return &opp->base;
692 }
693 
dce112_aux_engine_create(struct dc_context * ctx,uint32_t inst)694 static struct dce_aux *dce112_aux_engine_create(
695 	struct dc_context *ctx,
696 	uint32_t inst)
697 {
698 	struct aux_engine_dce110 *aux_engine =
699 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
700 
701 	if (!aux_engine)
702 		return NULL;
703 
704 	dce110_aux_engine_construct(aux_engine, ctx, inst,
705 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
706 				    &aux_engine_regs[inst],
707 					&aux_mask,
708 					&aux_shift,
709 					ctx->dc->caps.extended_aux_timeout_support);
710 
711 	return &aux_engine->base;
712 }
713 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
714 
715 static const struct dce_i2c_registers i2c_hw_regs[] = {
716 		i2c_inst_regs(1),
717 		i2c_inst_regs(2),
718 		i2c_inst_regs(3),
719 		i2c_inst_regs(4),
720 		i2c_inst_regs(5),
721 		i2c_inst_regs(6),
722 };
723 
724 static const struct dce_i2c_shift i2c_shifts = {
725 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
726 };
727 
728 static const struct dce_i2c_mask i2c_masks = {
729 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
730 };
731 
dce112_i2c_hw_create(struct dc_context * ctx,uint32_t inst)732 static struct dce_i2c_hw *dce112_i2c_hw_create(
733 	struct dc_context *ctx,
734 	uint32_t inst)
735 {
736 	struct dce_i2c_hw *dce_i2c_hw =
737 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
738 
739 	if (!dce_i2c_hw)
740 		return NULL;
741 
742 	dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
743 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
744 
745 	return dce_i2c_hw;
746 }
dce112_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)747 static struct clock_source *dce112_clock_source_create(
748 	struct dc_context *ctx,
749 	struct dc_bios *bios,
750 	enum clock_source_id id,
751 	const struct dce110_clk_src_regs *regs,
752 	bool dp_clk_src)
753 {
754 	struct dce110_clk_src *clk_src =
755 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
756 
757 	if (!clk_src)
758 		return NULL;
759 
760 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
761 			regs, &cs_shift, &cs_mask)) {
762 		clk_src->base.dp_clk_src = dp_clk_src;
763 		return &clk_src->base;
764 	}
765 
766 	kfree(clk_src);
767 	BREAK_TO_DEBUGGER();
768 	return NULL;
769 }
770 
dce112_clock_source_destroy(struct clock_source ** clk_src)771 static void dce112_clock_source_destroy(struct clock_source **clk_src)
772 {
773 	kfree(TO_DCE110_CLK_SRC(*clk_src));
774 	*clk_src = NULL;
775 }
776 
dce112_resource_destruct(struct dce110_resource_pool * pool)777 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
778 {
779 	unsigned int i;
780 
781 	for (i = 0; i < pool->base.pipe_count; i++) {
782 		if (pool->base.opps[i] != NULL)
783 			dce110_opp_destroy(&pool->base.opps[i]);
784 
785 		if (pool->base.transforms[i] != NULL)
786 			dce112_transform_destroy(&pool->base.transforms[i]);
787 
788 		if (pool->base.ipps[i] != NULL)
789 			dce_ipp_destroy(&pool->base.ipps[i]);
790 
791 		if (pool->base.mis[i] != NULL) {
792 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
793 			pool->base.mis[i] = NULL;
794 		}
795 
796 		if (pool->base.timing_generators[i] != NULL) {
797 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
798 			pool->base.timing_generators[i] = NULL;
799 		}
800 	}
801 
802 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
803 		if (pool->base.engines[i] != NULL)
804 			dce110_engine_destroy(&pool->base.engines[i]);
805 		if (pool->base.hw_i2cs[i] != NULL) {
806 			kfree(pool->base.hw_i2cs[i]);
807 			pool->base.hw_i2cs[i] = NULL;
808 		}
809 		if (pool->base.sw_i2cs[i] != NULL) {
810 			kfree(pool->base.sw_i2cs[i]);
811 			pool->base.sw_i2cs[i] = NULL;
812 		}
813 	}
814 
815 	for (i = 0; i < pool->base.stream_enc_count; i++) {
816 		if (pool->base.stream_enc[i] != NULL)
817 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
818 	}
819 
820 	for (i = 0; i < pool->base.clk_src_count; i++) {
821 		if (pool->base.clock_sources[i] != NULL) {
822 			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
823 		}
824 	}
825 
826 	if (pool->base.dp_clock_source != NULL)
827 		dce112_clock_source_destroy(&pool->base.dp_clock_source);
828 
829 	for (i = 0; i < pool->base.audio_count; i++)	{
830 		if (pool->base.audios[i] != NULL) {
831 			dce_aud_destroy(&pool->base.audios[i]);
832 		}
833 	}
834 
835 	if (pool->base.abm != NULL)
836 		dce_abm_destroy(&pool->base.abm);
837 
838 	if (pool->base.dmcu != NULL)
839 		dce_dmcu_destroy(&pool->base.dmcu);
840 
841 	if (pool->base.irqs != NULL) {
842 		dal_irq_service_destroy(&pool->base.irqs);
843 	}
844 }
845 
find_matching_pll(struct resource_context * res_ctx,const struct resource_pool * pool,const struct dc_stream_state * const stream)846 static struct clock_source *find_matching_pll(
847 		struct resource_context *res_ctx,
848 		const struct resource_pool *pool,
849 		const struct dc_stream_state *const stream)
850 {
851 	switch (stream->link->link_enc->transmitter) {
852 	case TRANSMITTER_UNIPHY_A:
853 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
854 	case TRANSMITTER_UNIPHY_B:
855 		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
856 	case TRANSMITTER_UNIPHY_C:
857 		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
858 	case TRANSMITTER_UNIPHY_D:
859 		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
860 	case TRANSMITTER_UNIPHY_E:
861 		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
862 	case TRANSMITTER_UNIPHY_F:
863 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
864 	default:
865 		return NULL;
866 	}
867 }
868 
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)869 static enum dc_status build_mapped_resource(
870 		const struct dc *dc,
871 		struct dc_state *context,
872 		struct dc_stream_state *stream)
873 {
874 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
875 
876 	if (!pipe_ctx)
877 		return DC_ERROR_UNEXPECTED;
878 
879 	dce110_resource_build_pipe_hw_param(pipe_ctx);
880 
881 	resource_build_info_frame(pipe_ctx);
882 
883 	return DC_OK;
884 }
885 
dce112_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)886 bool dce112_validate_bandwidth(
887 	struct dc *dc,
888 	struct dc_state *context,
889 	bool fast_validate)
890 {
891 	bool result = false;
892 
893 	DC_LOG_BANDWIDTH_CALCS(
894 		"%s: start",
895 		__func__);
896 
897 	if (bw_calcs(
898 			dc->ctx,
899 			dc->bw_dceip,
900 			dc->bw_vbios,
901 			context->res_ctx.pipe_ctx,
902 			dc->res_pool->pipe_count,
903 			&context->bw_ctx.bw.dce))
904 		result = true;
905 
906 	if (!result)
907 		DC_LOG_BANDWIDTH_VALIDATION(
908 			"%s: Bandwidth validation failed!",
909 			__func__);
910 
911 	if (memcmp(&dc->current_state->bw_ctx.bw.dce,
912 			&context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
913 
914 		DC_LOG_BANDWIDTH_CALCS(
915 			"%s: finish,\n"
916 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
917 			"stutMark_b: %d stutMark_a: %d\n"
918 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
919 			"stutMark_b: %d stutMark_a: %d\n"
920 			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
921 			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
922 			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
923 			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
924 			,
925 			__func__,
926 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
927 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
928 			context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
929 			context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
930 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
931 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
932 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
933 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
934 			context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
935 			context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
936 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
937 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
938 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
939 			context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
940 			context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
941 			context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
942 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
943 			context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
944 			context->bw_ctx.bw.dce.stutter_mode_enable,
945 			context->bw_ctx.bw.dce.cpuc_state_change_enable,
946 			context->bw_ctx.bw.dce.cpup_state_change_enable,
947 			context->bw_ctx.bw.dce.nbp_state_change_enable,
948 			context->bw_ctx.bw.dce.all_displays_in_sync,
949 			context->bw_ctx.bw.dce.dispclk_khz,
950 			context->bw_ctx.bw.dce.sclk_khz,
951 			context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
952 			context->bw_ctx.bw.dce.yclk_khz,
953 			context->bw_ctx.bw.dce.blackout_recovery_time_us);
954 	}
955 	return result;
956 }
957 
resource_map_phy_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)958 enum dc_status resource_map_phy_clock_resources(
959 		const struct dc *dc,
960 		struct dc_state *context,
961 		struct dc_stream_state *stream)
962 {
963 
964 	/* acquire new resources */
965 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
966 			&context->res_ctx, stream);
967 
968 	if (!pipe_ctx)
969 		return DC_ERROR_UNEXPECTED;
970 
971 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
972 		|| dc_is_virtual_signal(pipe_ctx->stream->signal))
973 		pipe_ctx->clock_source =
974 				dc->res_pool->dp_clock_source;
975 	else {
976 		if (stream && stream->link && stream->link->link_enc)
977 			pipe_ctx->clock_source = find_matching_pll(
978 				&context->res_ctx, dc->res_pool,
979 				stream);
980 	}
981 
982 	if (pipe_ctx->clock_source == NULL)
983 		return DC_NO_CLOCK_SOURCE_RESOURCE;
984 
985 	resource_reference_clock_source(
986 		&context->res_ctx,
987 		dc->res_pool,
988 		pipe_ctx->clock_source);
989 
990 	return DC_OK;
991 }
992 
dce112_validate_surface_sets(struct dc_state * context)993 static bool dce112_validate_surface_sets(
994 		struct dc_state *context)
995 {
996 	int i;
997 
998 	for (i = 0; i < context->stream_count; i++) {
999 		if (context->stream_status[i].plane_count == 0)
1000 			continue;
1001 
1002 		if (context->stream_status[i].plane_count > 1)
1003 			return false;
1004 
1005 		if (context->stream_status[i].plane_states[0]->format
1006 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
1007 			return false;
1008 	}
1009 
1010 	return true;
1011 }
1012 
dce112_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1013 enum dc_status dce112_add_stream_to_ctx(
1014 		struct dc *dc,
1015 		struct dc_state *new_ctx,
1016 		struct dc_stream_state *dc_stream)
1017 {
1018 	enum dc_status result;
1019 
1020 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1021 
1022 	if (result == DC_OK)
1023 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1024 
1025 
1026 	if (result == DC_OK)
1027 		result = build_mapped_resource(dc, new_ctx, dc_stream);
1028 
1029 	return result;
1030 }
1031 
dce112_validate_global(struct dc * dc,struct dc_state * context)1032 static enum dc_status dce112_validate_global(
1033 		struct dc *dc,
1034 		struct dc_state *context)
1035 {
1036 	if (!dce112_validate_surface_sets(context))
1037 		return DC_FAIL_SURFACE_VALIDATE;
1038 
1039 	return DC_OK;
1040 }
1041 
dce112_destroy_resource_pool(struct resource_pool ** pool)1042 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1043 {
1044 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1045 
1046 	dce112_resource_destruct(dce110_pool);
1047 	kfree(dce110_pool);
1048 	*pool = NULL;
1049 }
1050 
1051 static const struct resource_funcs dce112_res_pool_funcs = {
1052 	.destroy = dce112_destroy_resource_pool,
1053 	.link_enc_create = dce112_link_encoder_create,
1054 	.panel_cntl_create = dce112_panel_cntl_create,
1055 	.validate_bandwidth = dce112_validate_bandwidth,
1056 	.validate_plane = dce100_validate_plane,
1057 	.add_stream_to_ctx = dce112_add_stream_to_ctx,
1058 	.validate_global = dce112_validate_global,
1059 	.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1060 };
1061 
bw_calcs_data_update_from_pplib(struct dc * dc)1062 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1063 {
1064 	struct dm_pp_clock_levels_with_latency eng_clks = {0};
1065 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
1066 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
1067 	struct dm_pp_clock_levels clks = {0};
1068 	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
1069 
1070 	if (!dc->bw_vbios)
1071 		return;
1072 
1073 	if (dc->bw_vbios->memory_type == bw_def_hbm)
1074 		memory_type_multiplier = MEMORY_TYPE_HBM;
1075 
1076 	/*do system clock  TODO PPLIB: after PPLIB implement,
1077 	 * then remove old way
1078 	 */
1079 	if (!dm_pp_get_clock_levels_by_type_with_latency(
1080 			dc->ctx,
1081 			DM_PP_CLOCK_TYPE_ENGINE_CLK,
1082 			&eng_clks)) {
1083 
1084 		/* This is only for temporary */
1085 		dm_pp_get_clock_levels_by_type(
1086 				dc->ctx,
1087 				DM_PP_CLOCK_TYPE_ENGINE_CLK,
1088 				&clks);
1089 		/* convert all the clock fro kHz to fix point mHz */
1090 		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1091 				clks.clocks_in_khz[clks.num_levels-1], 1000);
1092 		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1093 				clks.clocks_in_khz[clks.num_levels/8], 1000);
1094 		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1095 				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1096 		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1097 				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1098 		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1099 				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1100 		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1101 				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1102 		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1103 				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1104 		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1105 				clks.clocks_in_khz[0], 1000);
1106 
1107 		/*do memory clock*/
1108 		dm_pp_get_clock_levels_by_type(
1109 				dc->ctx,
1110 				DM_PP_CLOCK_TYPE_MEMORY_CLK,
1111 				&clks);
1112 
1113 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1114 			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
1115 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1116 			clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1117 			1000);
1118 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1119 			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1120 			1000);
1121 
1122 		return;
1123 	}
1124 
1125 	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1126 	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1127 		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1128 	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1129 		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1130 	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1131 		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1132 	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1133 		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1134 	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1135 		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1136 	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1137 		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1138 	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1139 		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1140 	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1141 			eng_clks.data[0].clocks_in_khz, 1000);
1142 
1143 	/*do memory clock*/
1144 	dm_pp_get_clock_levels_by_type_with_latency(
1145 			dc->ctx,
1146 			DM_PP_CLOCK_TYPE_MEMORY_CLK,
1147 			&mem_clks);
1148 
1149 	/* we don't need to call PPLIB for validation clock since they
1150 	 * also give us the highest sclk and highest mclk (UMA clock).
1151 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1152 	 * YCLK = UMACLK*m_memoryTypeMultiplier
1153 	 */
1154 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1155 		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
1156 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1157 		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
1158 		1000);
1159 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1160 		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
1161 		1000);
1162 
1163 	/* Now notify PPLib/SMU about which Watermarks sets they should select
1164 	 * depending on DPM state they are in. And update BW MGR GFX Engine and
1165 	 * Memory clock member variables for Watermarks calculations for each
1166 	 * Watermark Set
1167 	 */
1168 	clk_ranges.num_wm_sets = 4;
1169 	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1170 	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1171 			eng_clks.data[0].clocks_in_khz;
1172 	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1173 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1174 	clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1175 			mem_clks.data[0].clocks_in_khz;
1176 	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1177 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1178 
1179 	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1180 	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1181 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1182 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1183 	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1184 	clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1185 			mem_clks.data[0].clocks_in_khz;
1186 	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1187 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1188 
1189 	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1190 	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1191 			eng_clks.data[0].clocks_in_khz;
1192 	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1193 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1194 	clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1195 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1196 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1197 	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1198 
1199 	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1200 	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1201 			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1202 	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1203 	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1204 	clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1205 			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1206 	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1207 	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1208 
1209 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1210 	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1211 }
1212 
dce112_resource_cap(struct hw_asic_id * asic_id)1213 static const struct resource_caps *dce112_resource_cap(
1214 	struct hw_asic_id *asic_id)
1215 {
1216 	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1217 	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1218 		return &polaris_11_resource_cap;
1219 	else
1220 		return &polaris_10_resource_cap;
1221 }
1222 
dce112_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1223 static bool dce112_resource_construct(
1224 	uint8_t num_virtual_links,
1225 	struct dc *dc,
1226 	struct dce110_resource_pool *pool)
1227 {
1228 	unsigned int i;
1229 	struct dc_context *ctx = dc->ctx;
1230 
1231 	ctx->dc_bios->regs = &bios_regs;
1232 
1233 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1234 	pool->base.funcs = &dce112_res_pool_funcs;
1235 
1236 	/*************************************************
1237 	 *  Resource + asic cap harcoding                *
1238 	 *************************************************/
1239 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1240 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1241 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1242 	dc->caps.max_downscale_ratio = 200;
1243 	dc->caps.i2c_speed_in_khz = 100;
1244 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1245 	dc->caps.max_cursor_size = 128;
1246 	dc->caps.min_horizontal_blanking_period = 80;
1247 	dc->caps.dual_link_dvi = true;
1248 	dc->caps.extended_aux_timeout_support = false;
1249 	dc->debug = debug_defaults;
1250 
1251 	/*************************************************
1252 	 *  Create resources                             *
1253 	 *************************************************/
1254 
1255 	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1256 			dce112_clock_source_create(
1257 				ctx, ctx->dc_bios,
1258 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1259 				&clk_src_regs[0], false);
1260 	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1261 			dce112_clock_source_create(
1262 				ctx, ctx->dc_bios,
1263 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1264 				&clk_src_regs[1], false);
1265 	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1266 			dce112_clock_source_create(
1267 				ctx, ctx->dc_bios,
1268 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1269 				&clk_src_regs[2], false);
1270 	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1271 			dce112_clock_source_create(
1272 				ctx, ctx->dc_bios,
1273 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1274 				&clk_src_regs[3], false);
1275 	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1276 			dce112_clock_source_create(
1277 				ctx, ctx->dc_bios,
1278 				CLOCK_SOURCE_COMBO_PHY_PLL4,
1279 				&clk_src_regs[4], false);
1280 	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1281 			dce112_clock_source_create(
1282 				ctx, ctx->dc_bios,
1283 				CLOCK_SOURCE_COMBO_PHY_PLL5,
1284 				&clk_src_regs[5], false);
1285 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1286 
1287 	pool->base.dp_clock_source =  dce112_clock_source_create(
1288 		ctx, ctx->dc_bios,
1289 		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1290 
1291 
1292 	for (i = 0; i < pool->base.clk_src_count; i++) {
1293 		if (pool->base.clock_sources[i] == NULL) {
1294 			dm_error("DC: failed to create clock sources!\n");
1295 			BREAK_TO_DEBUGGER();
1296 			goto res_create_fail;
1297 		}
1298 	}
1299 
1300 	pool->base.dmcu = dce_dmcu_create(ctx,
1301 			&dmcu_regs,
1302 			&dmcu_shift,
1303 			&dmcu_mask);
1304 	if (pool->base.dmcu == NULL) {
1305 		dm_error("DC: failed to create dmcu!\n");
1306 		BREAK_TO_DEBUGGER();
1307 		goto res_create_fail;
1308 	}
1309 
1310 	pool->base.abm = dce_abm_create(ctx,
1311 			&abm_regs,
1312 			&abm_shift,
1313 			&abm_mask);
1314 	if (pool->base.abm == NULL) {
1315 		dm_error("DC: failed to create abm!\n");
1316 		BREAK_TO_DEBUGGER();
1317 		goto res_create_fail;
1318 	}
1319 
1320 	{
1321 		struct irq_service_init_data init_data;
1322 		init_data.ctx = dc->ctx;
1323 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1324 		if (!pool->base.irqs)
1325 			goto res_create_fail;
1326 	}
1327 
1328 	for (i = 0; i < pool->base.pipe_count; i++) {
1329 		pool->base.timing_generators[i] =
1330 				dce112_timing_generator_create(
1331 					ctx,
1332 					i,
1333 					&dce112_tg_offsets[i]);
1334 		if (pool->base.timing_generators[i] == NULL) {
1335 			BREAK_TO_DEBUGGER();
1336 			dm_error("DC: failed to create tg!\n");
1337 			goto res_create_fail;
1338 		}
1339 
1340 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1341 		if (pool->base.mis[i] == NULL) {
1342 			BREAK_TO_DEBUGGER();
1343 			dm_error(
1344 				"DC: failed to create memory input!\n");
1345 			goto res_create_fail;
1346 		}
1347 
1348 		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1349 		if (pool->base.ipps[i] == NULL) {
1350 			BREAK_TO_DEBUGGER();
1351 			dm_error(
1352 				"DC:failed to create input pixel processor!\n");
1353 			goto res_create_fail;
1354 		}
1355 
1356 		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1357 		if (pool->base.transforms[i] == NULL) {
1358 			BREAK_TO_DEBUGGER();
1359 			dm_error(
1360 				"DC: failed to create transform!\n");
1361 			goto res_create_fail;
1362 		}
1363 
1364 		pool->base.opps[i] = dce112_opp_create(
1365 			ctx,
1366 			i);
1367 		if (pool->base.opps[i] == NULL) {
1368 			BREAK_TO_DEBUGGER();
1369 			dm_error(
1370 				"DC:failed to create output pixel processor!\n");
1371 			goto res_create_fail;
1372 		}
1373 	}
1374 
1375 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1376 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1377 		if (pool->base.engines[i] == NULL) {
1378 			BREAK_TO_DEBUGGER();
1379 			dm_error(
1380 				"DC:failed to create aux engine!!\n");
1381 			goto res_create_fail;
1382 		}
1383 		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1384 		if (pool->base.hw_i2cs[i] == NULL) {
1385 			BREAK_TO_DEBUGGER();
1386 			dm_error(
1387 				"DC:failed to create i2c engine!!\n");
1388 			goto res_create_fail;
1389 		}
1390 		pool->base.sw_i2cs[i] = NULL;
1391 	}
1392 
1393 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1394 			  &res_create_funcs))
1395 		goto res_create_fail;
1396 
1397 	dc->caps.max_planes =  pool->base.pipe_count;
1398 
1399 	for (i = 0; i < dc->caps.max_planes; ++i)
1400 		dc->caps.planes[i] = plane_cap;
1401 
1402 	/* Create hardware sequencer */
1403 	dce112_hw_sequencer_construct(dc);
1404 
1405 	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1406 
1407 	bw_calcs_data_update_from_pplib(dc);
1408 
1409 	return true;
1410 
1411 res_create_fail:
1412 	dce112_resource_destruct(pool);
1413 	return false;
1414 }
1415 
dce112_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1416 struct resource_pool *dce112_create_resource_pool(
1417 	uint8_t num_virtual_links,
1418 	struct dc *dc)
1419 {
1420 	struct dce110_resource_pool *pool =
1421 		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1422 
1423 	if (!pool)
1424 		return NULL;
1425 
1426 	if (dce112_resource_construct(num_virtual_links, dc, pool))
1427 		return &pool->base;
1428 
1429 	kfree(pool);
1430 	BREAK_TO_DEBUGGER();
1431 	return NULL;
1432 }
1433